Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc: (24 commits)
MMC: Use timeout values from CSR
MMC: CSD and CID timeout values
sdhci: 'scratch' may be used uninitialized
mmc: explicitly mention SDIO support in Kconfig
mmc: remove redundant "depends on"
Fix comment in include/linux/mmc/host.h
sdio: high-speed support
mmc_block: hard code 512 byte block size
sdhci: force high speed capability on some controllers
mmc_block: filter out PC requests
mmc_block: indicate strict ordering
mmc_block: inform block layer about sector count restriction
sdio: give sdio irq thread a host specific name
sdio: make sleep on error interruptable
sdhci: reduce card detection delay
sdhci: let the controller wait for busy state to end
atmel-mci: Add missing flush_dcache_page() in PIO transfer code
atmel-mci: Don't overwrite error bits when NOTBUSY is set
atmel-mci: Add experimental DMA support
atmel-mci: support multiple mmc slots
...

+1303 -516
+5 -2
arch/avr32/boards/atngw100/setup.c
··· 53 53 }; 54 54 55 55 static struct mci_platform_data __initdata mci0_data = { 56 - .detect_pin = GPIO_PIN_PC(25), 57 - .wp_pin = GPIO_PIN_PE(0), 56 + .slot[0] = { 57 + .bus_width = 4, 58 + .detect_pin = GPIO_PIN_PC(25), 59 + .wp_pin = GPIO_PIN_PE(0), 60 + }, 58 61 }; 59 62 60 63 /*
+11 -7
arch/avr32/boards/atstk1000/atstk1002.c
··· 264 264 265 265 #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM 266 266 267 + static struct mci_platform_data __initdata mci0_data = { 268 + .slot[0] = { 269 + .bus_width = 4, 270 + 267 271 /* MMC card detect requires MACB0 *NOT* be used */ 268 272 #ifdef CONFIG_BOARD_ATSTK1002_SW6_CUSTOM 269 - static struct mci_platform_data __initdata mci0_data = { 270 - .detect_pin = GPIO_PIN_PC(14), /* gpio30/sdcd */ 271 - .wp_pin = GPIO_PIN_PC(15), /* gpio31/sdwp */ 272 - }; 273 - #define MCI_PDATA &mci0_data 273 + .detect_pin = GPIO_PIN_PC(14), /* gpio30/sdcd */ 274 + .wp_pin = GPIO_PIN_PC(15), /* gpio31/sdwp */ 274 275 #else 275 - #define MCI_PDATA NULL 276 + .detect_pin = -ENODEV, 277 + .wp_pin = -ENODEV, 276 278 #endif /* SW6 for sd{cd,wp} routing */ 279 + }, 280 + }; 277 281 278 282 #endif /* SW2 for MMC signal routing */ 279 283 ··· 330 326 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info)); 331 327 #endif 332 328 #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM 333 - at32_add_device_mci(0, MCI_PDATA); 329 + at32_add_device_mci(0, &mci0_pdata); 334 330 #endif 335 331 #ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM 336 332 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
+11 -1
arch/avr32/boards/atstk1000/atstk1003.c
··· 66 66 } }; 67 67 #endif 68 68 69 + #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM 70 + static struct mci_platform_data __initdata mci0_data = { 71 + .slot[0] = { 72 + .bus_width = 4, 73 + .detect_pin = -ENODEV, 74 + .wp_pin = -ENODEV, 75 + }, 76 + }; 77 + #endif 78 + 69 79 #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC 70 80 static void __init atstk1003_setup_extdac(void) 71 81 { ··· 164 154 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info)); 165 155 #endif 166 156 #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM 167 - at32_add_device_mci(0, NULL); 157 + at32_add_device_mci(0, &mci0_data); 168 158 #endif 169 159 at32_add_device_usba(0, NULL); 170 160 #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
+11 -1
arch/avr32/boards/atstk1000/atstk1004.c
··· 71 71 } }; 72 72 #endif 73 73 74 + #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM 75 + static struct mci_platform_data __initdata mci0_data = { 76 + .slot[0] = { 77 + .bus_width = 4, 78 + .detect_pin = -ENODEV, 79 + .wp_pin = -ENODEV, 80 + }, 81 + }; 82 + #endif 83 + 74 84 #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC 75 85 static void __init atstk1004_setup_extdac(void) 76 86 { ··· 147 137 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info)); 148 138 #endif 149 139 #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM 150 - at32_add_device_mci(0, NULL); 140 + at32_add_device_mci(0, &mci0_data); 151 141 #endif 152 142 at32_add_device_lcdc(0, &atstk1000_lcdc_data, 153 143 fbmem_start, fbmem_size, 0);
+31 -1
arch/avr32/include/asm/atmel-mci.h
··· 1 1 #ifndef __ASM_AVR32_ATMEL_MCI_H 2 2 #define __ASM_AVR32_ATMEL_MCI_H 3 3 4 - struct mci_platform_data { 4 + #define ATMEL_MCI_MAX_NR_SLOTS 2 5 + 6 + struct dma_slave; 7 + 8 + /** 9 + * struct mci_slot_pdata - board-specific per-slot configuration 10 + * @bus_width: Number of data lines wired up the slot 11 + * @detect_pin: GPIO pin wired to the card detect switch 12 + * @wp_pin: GPIO pin wired to the write protect sensor 13 + * 14 + * If a given slot is not present on the board, @bus_width should be 15 + * set to 0. The other fields are ignored in this case. 16 + * 17 + * Any pins that aren't available should be set to a negative value. 18 + * 19 + * Note that support for multiple slots is experimental -- some cards 20 + * might get upset if we don't get the clock management exactly right. 21 + * But in most cases, it should work just fine. 22 + */ 23 + struct mci_slot_pdata { 24 + unsigned int bus_width; 5 25 int detect_pin; 6 26 int wp_pin; 27 + }; 28 + 29 + /** 30 + * struct mci_platform_data - board-specific MMC/SDcard configuration 31 + * @dma_slave: DMA slave interface to use in data transfers, or NULL. 32 + * @slot: Per-slot configuration data. 33 + */ 34 + struct mci_platform_data { 35 + struct dma_slave *dma_slave; 36 + struct mci_slot_pdata slot[ATMEL_MCI_MAX_NR_SLOTS]; 7 37 }; 8 38 9 39 #endif /* __ASM_AVR32_ATMEL_MCI_H */
+70 -18
arch/avr32/mach-at32ap/at32ap700x.c
··· 1272 1272 struct platform_device *__init 1273 1273 at32_add_device_mci(unsigned int id, struct mci_platform_data *data) 1274 1274 { 1275 - struct mci_platform_data _data; 1276 1275 struct platform_device *pdev; 1276 + struct dw_dma_slave *dws; 1277 1277 1278 - if (id != 0) 1278 + if (id != 0 || !data) 1279 + return NULL; 1280 + 1281 + /* Must have at least one usable slot */ 1282 + if (!data->slot[0].bus_width && !data->slot[1].bus_width) 1279 1283 return NULL; 1280 1284 1281 1285 pdev = platform_device_alloc("atmel_mci", id); ··· 1290 1286 ARRAY_SIZE(atmel_mci0_resource))) 1291 1287 goto fail; 1292 1288 1293 - if (!data) { 1294 - data = &_data; 1295 - memset(data, -1, sizeof(struct mci_platform_data)); 1296 - data->detect_pin = GPIO_PIN_NONE; 1297 - data->wp_pin = GPIO_PIN_NONE; 1298 - } 1289 + if (data->dma_slave) 1290 + dws = kmemdup(to_dw_dma_slave(data->dma_slave), 1291 + sizeof(struct dw_dma_slave), GFP_KERNEL); 1292 + else 1293 + dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL); 1294 + 1295 + dws->slave.dev = &pdev->dev; 1296 + dws->slave.dma_dev = &dw_dmac0_device.dev; 1297 + dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT; 1298 + dws->cfg_hi = (DWC_CFGH_SRC_PER(0) 1299 + | DWC_CFGH_DST_PER(1)); 1300 + dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL 1301 + | DWC_CFGL_HS_SRC_POL); 1302 + 1303 + data->dma_slave = &dws->slave; 1299 1304 1300 1305 if (platform_device_add_data(pdev, data, 1301 1306 sizeof(struct mci_platform_data))) 1302 1307 goto fail; 1303 1308 1304 - select_peripheral(PA(10), PERIPH_A, 0); /* CLK */ 1305 - select_peripheral(PA(11), PERIPH_A, 0); /* CMD */ 1306 - select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */ 1307 - select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */ 1308 - select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */ 1309 - select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */ 1309 + /* CLK line is common to both slots */ 1310 + select_peripheral(PA(10), PERIPH_A, 0); 1310 1311 1311 - if (gpio_is_valid(data->detect_pin)) 1312 - at32_select_gpio(data->detect_pin, 0); 1313 - if (gpio_is_valid(data->wp_pin)) 1314 - at32_select_gpio(data->wp_pin, 0); 1312 + switch (data->slot[0].bus_width) { 1313 + case 4: 1314 + select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */ 1315 + select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */ 1316 + select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */ 1317 + /* fall through */ 1318 + case 1: 1319 + select_peripheral(PA(11), PERIPH_A, 0); /* CMD */ 1320 + select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */ 1321 + 1322 + if (gpio_is_valid(data->slot[0].detect_pin)) 1323 + at32_select_gpio(data->slot[0].detect_pin, 0); 1324 + if (gpio_is_valid(data->slot[0].wp_pin)) 1325 + at32_select_gpio(data->slot[0].wp_pin, 0); 1326 + break; 1327 + case 0: 1328 + /* Slot is unused */ 1329 + break; 1330 + default: 1331 + goto fail; 1332 + } 1333 + 1334 + switch (data->slot[1].bus_width) { 1335 + case 4: 1336 + select_peripheral(PB(8), PERIPH_B, 0); /* DATA1 */ 1337 + select_peripheral(PB(9), PERIPH_B, 0); /* DATA2 */ 1338 + select_peripheral(PB(10), PERIPH_B, 0); /* DATA3 */ 1339 + /* fall through */ 1340 + case 1: 1341 + select_peripheral(PB(6), PERIPH_B, 0); /* CMD */ 1342 + select_peripheral(PB(7), PERIPH_B, 0); /* DATA0 */ 1343 + 1344 + if (gpio_is_valid(data->slot[1].detect_pin)) 1345 + at32_select_gpio(data->slot[1].detect_pin, 0); 1346 + if (gpio_is_valid(data->slot[1].wp_pin)) 1347 + at32_select_gpio(data->slot[1].wp_pin, 0); 1348 + break; 1349 + case 0: 1350 + /* Slot is unused */ 1351 + break; 1352 + default: 1353 + if (!data->slot[0].bus_width) 1354 + goto fail; 1355 + 1356 + data->slot[1].bus_width = 0; 1357 + break; 1358 + } 1315 1359 1316 1360 atmel_mci0_pclk.dev = &pdev->dev; 1317 1361
+5 -4
drivers/mmc/Kconfig
··· 3 3 # 4 4 5 5 menuconfig MMC 6 - tristate "MMC/SD card support" 6 + tristate "MMC/SD/SDIO card support" 7 7 depends on HAS_IOMEM 8 8 help 9 - MMC is the "multi-media card" bus protocol. 9 + This selects MultiMediaCard, Secure Digital and Secure 10 + Digital I/O support. 10 11 11 - If you want MMC support, you should say Y here and also 12 - to the specific driver for your MMC interface. 12 + If you want MMC/SD/SDIO support, you should say Y here and 13 + also to your specific host controller driver. 13 14 14 15 config MMC_DEBUG 15 16 bool "MMC debugging"
+1 -2
drivers/mmc/card/Kconfig
··· 2 2 # MMC/SD card drivers 3 3 # 4 4 5 - comment "MMC/SD Card Drivers" 5 + comment "MMC/SD/SDIO Card Drivers" 6 6 7 7 config MMC_BLOCK 8 8 tristate "MMC block device driver" ··· 34 34 35 35 config SDIO_UART 36 36 tristate "SDIO UART/GPS class support" 37 - depends on MMC 38 37 help 39 38 SDIO function driver for SDIO cards that implements the UART 40 39 class, as well as the GPS class which appears like a UART.
+6 -40
drivers/mmc/card/block.c
··· 58 58 struct mmc_queue queue; 59 59 60 60 unsigned int usage; 61 - unsigned int block_bits; 62 61 unsigned int read_only; 63 62 }; 64 63 ··· 215 216 struct mmc_blk_data *md = mq->data; 216 217 struct mmc_card *card = md->queue.card; 217 218 struct mmc_blk_request brq; 218 - int ret = 1, data_size, i; 219 - struct scatterlist *sg; 219 + int ret = 1; 220 220 221 221 mmc_claim_host(card->host); 222 222 ··· 231 233 if (!mmc_card_blockaddr(card)) 232 234 brq.cmd.arg <<= 9; 233 235 brq.cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC; 234 - brq.data.blksz = 1 << md->block_bits; 236 + brq.data.blksz = 512; 235 237 brq.stop.opcode = MMC_STOP_TRANSMISSION; 236 238 brq.stop.arg = 0; 237 239 brq.stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC; 238 - brq.data.blocks = req->nr_sectors >> (md->block_bits - 9); 239 - if (brq.data.blocks > card->host->max_blk_count) 240 - brq.data.blocks = card->host->max_blk_count; 240 + brq.data.blocks = req->nr_sectors; 241 241 242 242 if (brq.data.blocks > 1) { 243 243 /* SPI multiblock writes terminate using a special ··· 266 270 brq.data.sg_len = mmc_queue_map_sg(mq); 267 271 268 272 mmc_queue_bounce_pre(mq); 269 - 270 - /* 271 - * Adjust the sg list so it is the same size as the 272 - * request. 273 - */ 274 - if (brq.data.blocks != 275 - (req->nr_sectors >> (md->block_bits - 9))) { 276 - data_size = brq.data.blocks * brq.data.blksz; 277 - for_each_sg(brq.data.sg, sg, brq.data.sg_len, i) { 278 - data_size -= sg->length; 279 - if (data_size <= 0) { 280 - sg->length += data_size; 281 - i++; 282 - break; 283 - } 284 - } 285 - brq.data.sg_len = i; 286 - } 287 273 288 274 mmc_wait_for_req(card->host, &brq.mrq); 289 275 ··· 351 373 if (rq_data_dir(req) != READ) { 352 374 if (mmc_card_sd(card)) { 353 375 u32 blocks; 354 - unsigned int bytes; 355 376 356 377 blocks = mmc_sd_num_wr_blocks(card); 357 378 if (blocks != (u32)-1) { 358 - if (card->csd.write_partial) 359 - bytes = blocks << md->block_bits; 360 - else 361 - bytes = blocks << 9; 362 379 spin_lock_irq(&md->lock); 363 - ret = __blk_end_request(req, 0, bytes); 380 + ret = __blk_end_request(req, 0, blocks << 9); 364 381 spin_unlock_irq(&md->lock); 365 382 } 366 383 } else { ··· 405 432 */ 406 433 md->read_only = mmc_blk_readonly(card); 407 434 408 - /* 409 - * Both SD and MMC specifications state (although a bit 410 - * unclearly in the MMC case) that a block size of 512 411 - * bytes must always be supported by the card. 412 - */ 413 - md->block_bits = 9; 414 - 415 435 md->disk = alloc_disk(1 << MMC_SHIFT); 416 436 if (md->disk == NULL) { 417 437 ret = -ENOMEM; ··· 442 476 443 477 sprintf(md->disk->disk_name, "mmcblk%d", devidx); 444 478 445 - blk_queue_hardsect_size(md->queue.queue, 1 << md->block_bits); 479 + blk_queue_hardsect_size(md->queue.queue, 512); 446 480 447 481 if (!mmc_card_sd(card) && mmc_card_blockaddr(card)) { 448 482 /* ··· 480 514 481 515 mmc_claim_host(card->host); 482 516 cmd.opcode = MMC_SET_BLOCKLEN; 483 - cmd.arg = 1 << md->block_bits; 517 + cmd.arg = 512; 484 518 cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC; 485 519 err = mmc_wait_for_cmd(card->host, &cmd, 5); 486 520 mmc_release_host(card->host);
+16 -7
drivers/mmc/card/queue.c
··· 31 31 /* 32 32 * We only like normal block requests. 33 33 */ 34 - if (!blk_fs_request(req) && !blk_pc_request(req)) { 34 + if (!blk_fs_request(req)) { 35 35 blk_dump_rq_flags(req, "MMC bad request"); 36 36 return BLKPREP_KILL; 37 37 } ··· 131 131 mq->req = NULL; 132 132 133 133 blk_queue_prep_rq(mq->queue, mmc_prep_request); 134 + blk_queue_ordered(mq->queue, QUEUE_ORDERED_DRAIN, NULL); 134 135 135 136 #ifdef CONFIG_MMC_BLOCK_BOUNCE 136 137 if (host->max_hw_segs == 1) { ··· 143 142 bouncesz = host->max_req_size; 144 143 if (bouncesz > host->max_seg_size) 145 144 bouncesz = host->max_seg_size; 145 + if (bouncesz > (host->max_blk_count * 512)) 146 + bouncesz = host->max_blk_count * 512; 146 147 147 - mq->bounce_buf = kmalloc(bouncesz, GFP_KERNEL); 148 - if (!mq->bounce_buf) { 149 - printk(KERN_WARNING "%s: unable to allocate " 150 - "bounce buffer\n", mmc_card_name(card)); 151 - } else { 148 + if (bouncesz > 512) { 149 + mq->bounce_buf = kmalloc(bouncesz, GFP_KERNEL); 150 + if (!mq->bounce_buf) { 151 + printk(KERN_WARNING "%s: unable to " 152 + "allocate bounce buffer\n", 153 + mmc_card_name(card)); 154 + } 155 + } 156 + 157 + if (mq->bounce_buf) { 152 158 blk_queue_bounce_limit(mq->queue, BLK_BOUNCE_ANY); 153 159 blk_queue_max_sectors(mq->queue, bouncesz / 512); 154 160 blk_queue_max_phys_segments(mq->queue, bouncesz / 512); ··· 183 175 184 176 if (!mq->bounce_buf) { 185 177 blk_queue_bounce_limit(mq->queue, limit); 186 - blk_queue_max_sectors(mq->queue, host->max_req_size / 512); 178 + blk_queue_max_sectors(mq->queue, 179 + min(host->max_blk_count, host->max_req_size / 512)); 187 180 blk_queue_max_phys_segments(mq->queue, host->max_phys_segs); 188 181 blk_queue_max_hw_segments(mq->queue, host->max_hw_segs); 189 182 blk_queue_max_segment_size(mq->queue, host->max_seg_size);
+6 -2
drivers/mmc/core/mmc_ops.c
··· 248 248 249 249 sg_init_one(&sg, data_buf, len); 250 250 251 - if (card) 252 - mmc_set_data_timeout(&data, card); 251 + /* 252 + * The spec states that CSR and CID accesses have a timeout 253 + * of 64 clock cycles. 254 + */ 255 + data.timeout_ns = 0; 256 + data.timeout_clks = 64; 253 257 254 258 mmc_wait_for_req(host, &mrq); 255 259
+49 -3
drivers/mmc/core/sdio.c
··· 165 165 } 166 166 167 167 /* 168 + * Test if the card supports high-speed mode and, if so, switch to it. 169 + */ 170 + static int sdio_enable_hs(struct mmc_card *card) 171 + { 172 + int ret; 173 + u8 speed; 174 + 175 + if (!(card->host->caps & MMC_CAP_SD_HIGHSPEED)) 176 + return 0; 177 + 178 + if (!card->cccr.high_speed) 179 + return 0; 180 + 181 + ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_SPEED, 0, &speed); 182 + if (ret) 183 + return ret; 184 + 185 + speed |= SDIO_SPEED_EHS; 186 + 187 + ret = mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_SPEED, speed, NULL); 188 + if (ret) 189 + return ret; 190 + 191 + mmc_card_set_highspeed(card); 192 + mmc_set_timing(card->host, MMC_TIMING_SD_HS); 193 + 194 + return 0; 195 + } 196 + 197 + /* 168 198 * Host is being removed. Free up the current card. 169 199 */ 170 200 static void mmc_sdio_remove(struct mmc_host *host) ··· 363 333 goto remove; 364 334 365 335 /* 366 - * No support for high-speed yet, so just set 367 - * the card's maximum speed. 336 + * Switch to high-speed (if supported). 368 337 */ 369 - mmc_set_clock(host, card->cis.max_dtr); 338 + err = sdio_enable_hs(card); 339 + if (err) 340 + goto remove; 341 + 342 + /* 343 + * Change to the card's maximum speed. 344 + */ 345 + if (mmc_card_highspeed(card)) { 346 + /* 347 + * The SDIO specification doesn't mention how 348 + * the CIS transfer speed register relates to 349 + * high-speed, but it seems that 50 MHz is 350 + * mandatory. 351 + */ 352 + mmc_set_clock(host, 50000000); 353 + } else { 354 + mmc_set_clock(host, card->cis.max_dtr); 355 + } 370 356 371 357 /* 372 358 * Switch to wider bus (if supported).
+11 -5
drivers/mmc/core/sdio_irq.c
··· 5 5 * Created: June 18, 2007 6 6 * Copyright: MontaVista Software Inc. 7 7 * 8 + * Copyright 2008 Pierre Ossman 9 + * 8 10 * This program is free software; you can redistribute it and/or modify 9 11 * it under the terms of the GNU General Public License as published by 10 12 * the Free Software Foundation; either version 2 of the License, or (at ··· 109 107 110 108 /* 111 109 * Give other threads a chance to run in the presence of 112 - * errors. FIXME: determine if due to card removal and 113 - * possibly exit this thread if so. 110 + * errors. 114 111 */ 115 - if (ret < 0) 116 - ssleep(1); 112 + if (ret < 0) { 113 + set_current_state(TASK_INTERRUPTIBLE); 114 + if (!kthread_should_stop()) 115 + schedule_timeout(HZ); 116 + set_current_state(TASK_RUNNING); 117 + } 117 118 118 119 /* 119 120 * Adaptive polling frequency based on the assumption ··· 159 154 if (!host->sdio_irqs++) { 160 155 atomic_set(&host->sdio_irq_thread_abort, 0); 161 156 host->sdio_irq_thread = 162 - kthread_run(sdio_irq_thread, host, "ksdiorqd"); 157 + kthread_run(sdio_irq_thread, host, "ksdioirqd/%s", 158 + mmc_hostname(host)); 163 159 if (IS_ERR(host->sdio_irq_thread)) { 164 160 int err = PTR_ERR(host->sdio_irq_thread); 165 161 host->sdio_irqs--;
+21 -9
drivers/mmc/host/Kconfig
··· 2 2 # MMC/SD host controller drivers 3 3 # 4 4 5 - comment "MMC/SD Host Controller Drivers" 5 + comment "MMC/SD/SDIO Host Controller Drivers" 6 6 7 7 config MMC_ARMMMCI 8 8 tristate "ARM AMBA Multimedia Card Interface support" ··· 114 114 115 115 If unsure, say N. 116 116 117 + config MMC_ATMELMCI_DMA 118 + bool "Atmel MCI DMA support (EXPERIMENTAL)" 119 + depends on MMC_ATMELMCI && DMA_ENGINE && EXPERIMENTAL 120 + help 121 + Say Y here to have the Atmel MCI driver use a DMA engine to 122 + do data transfers and thus increase the throughput and 123 + reduce the CPU utilization. Note that this is highly 124 + experimental and may cause the driver to lock up. 125 + 126 + If unsure, say N. 127 + 117 128 config MMC_IMX 118 129 tristate "Motorola i.MX Multimedia Card Interface support" 119 130 depends on ARCH_IMX ··· 152 141 module will be called tifm_sd. 153 142 154 143 config MMC_SPI 155 - tristate "MMC/SD over SPI" 156 - depends on MMC && SPI_MASTER && !HIGHMEM && HAS_DMA 144 + tristate "MMC/SD/SDIO over SPI" 145 + depends on SPI_MASTER && !HIGHMEM && HAS_DMA 157 146 select CRC7 158 147 select CRC_ITU_T 159 148 help 160 - Some systems accss MMC/SD cards using a SPI controller instead of 161 - using a "native" MMC/SD controller. This has a disadvantage of 162 - being relatively high overhead, but a compensating advantage of 163 - working on many systems without dedicated MMC/SD controllers. 149 + Some systems accss MMC/SD/SDIO cards using a SPI controller 150 + instead of using a "native" MMC/SD/SDIO controller. This has a 151 + disadvantage of being relatively high overhead, but a compensating 152 + advantage of working on many systems without dedicated MMC/SD/SDIO 153 + controllers. 164 154 165 155 If unsure, or if your system has no SPI master driver, say N. 166 156 167 157 config MMC_S3C 168 158 tristate "Samsung S3C SD/MMC Card Interface support" 169 - depends on ARCH_S3C2410 && MMC 159 + depends on ARCH_S3C2410 170 160 help 171 161 This selects a driver for the MCI interface found in 172 162 Samsung's S3C2410, S3C2412, S3C2440, S3C2442 CPUs. ··· 178 166 179 167 config MMC_SDRICOH_CS 180 168 tristate "MMC/SD driver for Ricoh Bay1Controllers (EXPERIMENTAL)" 181 - depends on EXPERIMENTAL && MMC && PCI && PCMCIA 169 + depends on EXPERIMENTAL && PCI && PCMCIA 182 170 help 183 171 Say Y here if your Notebook reports a Ricoh Bay1Controller PCMCIA 184 172 card whenever you insert a MMC or SD card into the card slot.
+4 -2
drivers/mmc/host/atmel-mci-regs.h
··· 25 25 #define MCI_SDCR 0x000c /* SD Card / SDIO */ 26 26 # define MCI_SDCSEL_SLOT_A ( 0 << 0) /* Select SD slot A */ 27 27 # define MCI_SDCSEL_SLOT_B ( 1 << 0) /* Select SD slot A */ 28 - # define MCI_SDCBUS_1BIT ( 0 << 7) /* 1-bit data bus */ 29 - # define MCI_SDCBUS_4BIT ( 1 << 7) /* 4-bit data bus */ 28 + # define MCI_SDCSEL_MASK ( 3 << 0) 29 + # define MCI_SDCBUS_1BIT ( 0 << 6) /* 1-bit data bus */ 30 + # define MCI_SDCBUS_4BIT ( 2 << 6) /* 4-bit data bus */ 31 + # define MCI_SDCBUS_MASK ( 3 << 6) 30 32 #define MCI_ARGR 0x0010 /* Command Argument */ 31 33 #define MCI_CMDR 0x0014 /* Command */ 32 34 # define MCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
+982 -390
drivers/mmc/host/atmel-mci.c
··· 11 11 #include <linux/clk.h> 12 12 #include <linux/debugfs.h> 13 13 #include <linux/device.h> 14 + #include <linux/dmaengine.h> 15 + #include <linux/dma-mapping.h> 14 16 #include <linux/err.h> 15 17 #include <linux/gpio.h> 16 18 #include <linux/init.h> ··· 35 33 #include "atmel-mci-regs.h" 36 34 37 35 #define ATMCI_DATA_ERROR_FLAGS (MCI_DCRCE | MCI_DTOE | MCI_OVRE | MCI_UNRE) 36 + #define ATMCI_DMA_THRESHOLD 16 38 37 39 38 enum { 40 39 EVENT_CMD_COMPLETE = 0, 41 - EVENT_DATA_ERROR, 42 - EVENT_DATA_COMPLETE, 43 - EVENT_STOP_SENT, 44 - EVENT_STOP_COMPLETE, 45 40 EVENT_XFER_COMPLETE, 41 + EVENT_DATA_COMPLETE, 42 + EVENT_DATA_ERROR, 46 43 }; 47 44 45 + enum atmel_mci_state { 46 + STATE_IDLE = 0, 47 + STATE_SENDING_CMD, 48 + STATE_SENDING_DATA, 49 + STATE_DATA_BUSY, 50 + STATE_SENDING_STOP, 51 + STATE_DATA_ERROR, 52 + }; 53 + 54 + struct atmel_mci_dma { 55 + #ifdef CONFIG_MMC_ATMELMCI_DMA 56 + struct dma_client client; 57 + struct dma_chan *chan; 58 + struct dma_async_tx_descriptor *data_desc; 59 + #endif 60 + }; 61 + 62 + /** 63 + * struct atmel_mci - MMC controller state shared between all slots 64 + * @lock: Spinlock protecting the queue and associated data. 65 + * @regs: Pointer to MMIO registers. 66 + * @sg: Scatterlist entry currently being processed by PIO code, if any. 67 + * @pio_offset: Offset into the current scatterlist entry. 68 + * @cur_slot: The slot which is currently using the controller. 69 + * @mrq: The request currently being processed on @cur_slot, 70 + * or NULL if the controller is idle. 71 + * @cmd: The command currently being sent to the card, or NULL. 72 + * @data: The data currently being transferred, or NULL if no data 73 + * transfer is in progress. 74 + * @dma: DMA client state. 75 + * @data_chan: DMA channel being used for the current data transfer. 76 + * @cmd_status: Snapshot of SR taken upon completion of the current 77 + * command. Only valid when EVENT_CMD_COMPLETE is pending. 78 + * @data_status: Snapshot of SR taken upon completion of the current 79 + * data transfer. Only valid when EVENT_DATA_COMPLETE or 80 + * EVENT_DATA_ERROR is pending. 81 + * @stop_cmdr: Value to be loaded into CMDR when the stop command is 82 + * to be sent. 83 + * @tasklet: Tasklet running the request state machine. 84 + * @pending_events: Bitmask of events flagged by the interrupt handler 85 + * to be processed by the tasklet. 86 + * @completed_events: Bitmask of events which the state machine has 87 + * processed. 88 + * @state: Tasklet state. 89 + * @queue: List of slots waiting for access to the controller. 90 + * @need_clock_update: Update the clock rate before the next request. 91 + * @need_reset: Reset controller before next request. 92 + * @mode_reg: Value of the MR register. 93 + * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 94 + * rate and timeout calculations. 95 + * @mapbase: Physical address of the MMIO registers. 96 + * @mck: The peripheral bus clock hooked up to the MMC controller. 97 + * @pdev: Platform device associated with the MMC controller. 98 + * @slot: Slots sharing this MMC controller. 99 + * 100 + * Locking 101 + * ======= 102 + * 103 + * @lock is a softirq-safe spinlock protecting @queue as well as 104 + * @cur_slot, @mrq and @state. These must always be updated 105 + * at the same time while holding @lock. 106 + * 107 + * @lock also protects mode_reg and need_clock_update since these are 108 + * used to synchronize mode register updates with the queue 109 + * processing. 110 + * 111 + * The @mrq field of struct atmel_mci_slot is also protected by @lock, 112 + * and must always be written at the same time as the slot is added to 113 + * @queue. 114 + * 115 + * @pending_events and @completed_events are accessed using atomic bit 116 + * operations, so they don't need any locking. 117 + * 118 + * None of the fields touched by the interrupt handler need any 119 + * locking. However, ordering is important: Before EVENT_DATA_ERROR or 120 + * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 121 + * interrupts must be disabled and @data_status updated with a 122 + * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 123 + * CMDRDY interupt must be disabled and @cmd_status updated with a 124 + * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 125 + * bytes_xfered field of @data must be written. This is ensured by 126 + * using barriers. 127 + */ 48 128 struct atmel_mci { 49 - struct mmc_host *mmc; 129 + spinlock_t lock; 50 130 void __iomem *regs; 51 131 52 132 struct scatterlist *sg; 53 133 unsigned int pio_offset; 54 134 135 + struct atmel_mci_slot *cur_slot; 55 136 struct mmc_request *mrq; 56 137 struct mmc_command *cmd; 57 138 struct mmc_data *data; 58 139 140 + struct atmel_mci_dma dma; 141 + struct dma_chan *data_chan; 142 + 59 143 u32 cmd_status; 60 144 u32 data_status; 61 - u32 stop_status; 62 145 u32 stop_cmdr; 63 - 64 - u32 mode_reg; 65 - u32 sdc_reg; 66 146 67 147 struct tasklet_struct tasklet; 68 148 unsigned long pending_events; 69 149 unsigned long completed_events; 150 + enum atmel_mci_state state; 151 + struct list_head queue; 70 152 71 - int present; 72 - int detect_pin; 73 - int wp_pin; 74 - 75 - /* For detect pin debouncing */ 76 - struct timer_list detect_timer; 77 - 153 + bool need_clock_update; 154 + bool need_reset; 155 + u32 mode_reg; 78 156 unsigned long bus_hz; 79 157 unsigned long mapbase; 80 158 struct clk *mck; 81 159 struct platform_device *pdev; 160 + 161 + struct atmel_mci_slot *slot[ATMEL_MCI_MAX_NR_SLOTS]; 82 162 }; 83 163 84 - #define atmci_is_completed(host, event) \ 85 - test_bit(event, &host->completed_events) 164 + /** 165 + * struct atmel_mci_slot - MMC slot state 166 + * @mmc: The mmc_host representing this slot. 167 + * @host: The MMC controller this slot is using. 168 + * @sdc_reg: Value of SDCR to be written before using this slot. 169 + * @mrq: mmc_request currently being processed or waiting to be 170 + * processed, or NULL when the slot is idle. 171 + * @queue_node: List node for placing this node in the @queue list of 172 + * &struct atmel_mci. 173 + * @clock: Clock rate configured by set_ios(). Protected by host->lock. 174 + * @flags: Random state bits associated with the slot. 175 + * @detect_pin: GPIO pin used for card detection, or negative if not 176 + * available. 177 + * @wp_pin: GPIO pin used for card write protect sending, or negative 178 + * if not available. 179 + * @detect_timer: Timer used for debouncing @detect_pin interrupts. 180 + */ 181 + struct atmel_mci_slot { 182 + struct mmc_host *mmc; 183 + struct atmel_mci *host; 184 + 185 + u32 sdc_reg; 186 + 187 + struct mmc_request *mrq; 188 + struct list_head queue_node; 189 + 190 + unsigned int clock; 191 + unsigned long flags; 192 + #define ATMCI_CARD_PRESENT 0 193 + #define ATMCI_CARD_NEED_INIT 1 194 + #define ATMCI_SHUTDOWN 2 195 + 196 + int detect_pin; 197 + int wp_pin; 198 + 199 + struct timer_list detect_timer; 200 + }; 201 + 86 202 #define atmci_test_and_clear_pending(host, event) \ 87 203 test_and_clear_bit(event, &host->pending_events) 88 - #define atmci_test_and_set_completed(host, event) \ 89 - test_and_set_bit(event, &host->completed_events) 90 204 #define atmci_set_completed(host, event) \ 91 205 set_bit(event, &host->completed_events) 92 206 #define atmci_set_pending(host, event) \ 93 207 set_bit(event, &host->pending_events) 94 - #define atmci_clear_pending(host, event) \ 95 - clear_bit(event, &host->pending_events) 96 208 97 209 /* 98 210 * The debugfs stuff below is mostly optimized away when ··· 214 98 */ 215 99 static int atmci_req_show(struct seq_file *s, void *v) 216 100 { 217 - struct atmel_mci *host = s->private; 218 - struct mmc_request *mrq = host->mrq; 101 + struct atmel_mci_slot *slot = s->private; 102 + struct mmc_request *mrq; 219 103 struct mmc_command *cmd; 220 104 struct mmc_command *stop; 221 105 struct mmc_data *data; 222 106 223 107 /* Make sure we get a consistent snapshot */ 224 - spin_lock_irq(&host->mmc->lock); 108 + spin_lock_bh(&slot->host->lock); 109 + mrq = slot->mrq; 225 110 226 111 if (mrq) { 227 112 cmd = mrq->cmd; ··· 247 130 stop->resp[2], stop->error); 248 131 } 249 132 250 - spin_unlock_irq(&host->mmc->lock); 133 + spin_unlock_bh(&slot->host->lock); 251 134 252 135 return 0; 253 136 } ··· 310 193 if (!buf) 311 194 return -ENOMEM; 312 195 313 - /* Grab a more or less consistent snapshot */ 314 - spin_lock_irq(&host->mmc->lock); 196 + /* 197 + * Grab a more or less consistent snapshot. Note that we're 198 + * not disabling interrupts, so IMR and SR may not be 199 + * consistent. 200 + */ 201 + spin_lock_bh(&host->lock); 315 202 clk_enable(host->mck); 316 203 memcpy_fromio(buf, host->regs, MCI_REGS_SIZE); 317 204 clk_disable(host->mck); 318 - spin_unlock_irq(&host->mmc->lock); 205 + spin_unlock_bh(&host->lock); 319 206 320 207 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n", 321 208 buf[MCI_MR / 4], ··· 357 236 .release = single_release, 358 237 }; 359 238 360 - static void atmci_init_debugfs(struct atmel_mci *host) 239 + static void atmci_init_debugfs(struct atmel_mci_slot *slot) 361 240 { 362 - struct mmc_host *mmc; 363 - struct dentry *root; 364 - struct dentry *node; 241 + struct mmc_host *mmc = slot->mmc; 242 + struct atmel_mci *host = slot->host; 243 + struct dentry *root; 244 + struct dentry *node; 365 245 366 - mmc = host->mmc; 367 246 root = mmc->debugfs_root; 368 247 if (!root) 369 248 return; ··· 375 254 if (!node) 376 255 goto err; 377 256 378 - node = debugfs_create_file("req", S_IRUSR, root, host, &atmci_req_fops); 257 + node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops); 258 + if (!node) 259 + goto err; 260 + 261 + node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 379 262 if (!node) 380 263 goto err; 381 264 ··· 396 271 return; 397 272 398 273 err: 399 - dev_err(&host->pdev->dev, 400 - "failed to initialize debugfs for controller\n"); 401 - } 402 - 403 - static void atmci_enable(struct atmel_mci *host) 404 - { 405 - clk_enable(host->mck); 406 - mci_writel(host, CR, MCI_CR_MCIEN); 407 - mci_writel(host, MR, host->mode_reg); 408 - mci_writel(host, SDCR, host->sdc_reg); 409 - } 410 - 411 - static void atmci_disable(struct atmel_mci *host) 412 - { 413 - mci_writel(host, CR, MCI_CR_SWRST); 414 - 415 - /* Stall until write is complete, then disable the bus clock */ 416 - mci_readl(host, SR); 417 - clk_disable(host->mck); 274 + dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 418 275 } 419 276 420 277 static inline unsigned int ns_to_clocks(struct atmel_mci *host, ··· 406 299 } 407 300 408 301 static void atmci_set_timeout(struct atmel_mci *host, 409 - struct mmc_data *data) 302 + struct atmel_mci_slot *slot, struct mmc_data *data) 410 303 { 411 304 static unsigned dtomul_to_shift[] = { 412 305 0, 4, 7, 8, 10, 12, 16, 20 ··· 429 322 dtocyc = 15; 430 323 } 431 324 432 - dev_vdbg(&host->mmc->class_dev, "setting timeout to %u cycles\n", 325 + dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", 433 326 dtocyc << dtomul_to_shift[dtomul]); 434 327 mci_writel(host, DTOR, (MCI_DTOMUL(dtomul) | MCI_DTOCYC(dtocyc))); 435 328 } ··· 482 375 } 483 376 484 377 static void atmci_start_command(struct atmel_mci *host, 485 - struct mmc_command *cmd, 486 - u32 cmd_flags) 378 + struct mmc_command *cmd, u32 cmd_flags) 487 379 { 488 - /* Must read host->cmd after testing event flags */ 489 - smp_rmb(); 490 380 WARN_ON(host->cmd); 491 381 host->cmd = cmd; 492 382 493 - dev_vdbg(&host->mmc->class_dev, 383 + dev_vdbg(&host->pdev->dev, 494 384 "start command: ARGR=0x%08x CMDR=0x%08x\n", 495 385 cmd->arg, cmd_flags); 496 386 ··· 495 391 mci_writel(host, CMDR, cmd_flags); 496 392 } 497 393 498 - static void send_stop_cmd(struct mmc_host *mmc, struct mmc_data *data) 394 + static void send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) 499 395 { 500 - struct atmel_mci *host = mmc_priv(mmc); 501 - 502 396 atmci_start_command(host, data->stop, host->stop_cmdr); 503 397 mci_writel(host, IER, MCI_CMDRDY); 504 398 } 505 399 506 - static void atmci_request_end(struct mmc_host *mmc, struct mmc_request *mrq) 400 + #ifdef CONFIG_MMC_ATMELMCI_DMA 401 + static void atmci_dma_cleanup(struct atmel_mci *host) 507 402 { 508 - struct atmel_mci *host = mmc_priv(mmc); 403 + struct mmc_data *data = host->data; 509 404 510 - WARN_ON(host->cmd || host->data); 511 - host->mrq = NULL; 512 - 513 - atmci_disable(host); 514 - 515 - mmc_request_done(mmc, mrq); 405 + dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, 406 + ((data->flags & MMC_DATA_WRITE) 407 + ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); 516 408 } 409 + 410 + static void atmci_stop_dma(struct atmel_mci *host) 411 + { 412 + struct dma_chan *chan = host->data_chan; 413 + 414 + if (chan) { 415 + chan->device->device_terminate_all(chan); 416 + atmci_dma_cleanup(host); 417 + } else { 418 + /* Data transfer was stopped by the interrupt handler */ 419 + atmci_set_pending(host, EVENT_XFER_COMPLETE); 420 + mci_writel(host, IER, MCI_NOTBUSY); 421 + } 422 + } 423 + 424 + /* This function is called by the DMA driver from tasklet context. */ 425 + static void atmci_dma_complete(void *arg) 426 + { 427 + struct atmel_mci *host = arg; 428 + struct mmc_data *data = host->data; 429 + 430 + dev_vdbg(&host->pdev->dev, "DMA complete\n"); 431 + 432 + atmci_dma_cleanup(host); 433 + 434 + /* 435 + * If the card was removed, data will be NULL. No point trying 436 + * to send the stop command or waiting for NBUSY in this case. 437 + */ 438 + if (data) { 439 + atmci_set_pending(host, EVENT_XFER_COMPLETE); 440 + tasklet_schedule(&host->tasklet); 441 + 442 + /* 443 + * Regardless of what the documentation says, we have 444 + * to wait for NOTBUSY even after block read 445 + * operations. 446 + * 447 + * When the DMA transfer is complete, the controller 448 + * may still be reading the CRC from the card, i.e. 449 + * the data transfer is still in progress and we 450 + * haven't seen all the potential error bits yet. 451 + * 452 + * The interrupt handler will schedule a different 453 + * tasklet to finish things up when the data transfer 454 + * is completely done. 455 + * 456 + * We may not complete the mmc request here anyway 457 + * because the mmc layer may call back and cause us to 458 + * violate the "don't submit new operations from the 459 + * completion callback" rule of the dma engine 460 + * framework. 461 + */ 462 + mci_writel(host, IER, MCI_NOTBUSY); 463 + } 464 + } 465 + 466 + static int 467 + atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) 468 + { 469 + struct dma_chan *chan; 470 + struct dma_async_tx_descriptor *desc; 471 + struct scatterlist *sg; 472 + unsigned int i; 473 + enum dma_data_direction direction; 474 + 475 + /* 476 + * We don't do DMA on "complex" transfers, i.e. with 477 + * non-word-aligned buffers or lengths. Also, we don't bother 478 + * with all the DMA setup overhead for short transfers. 479 + */ 480 + if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) 481 + return -EINVAL; 482 + if (data->blksz & 3) 483 + return -EINVAL; 484 + 485 + for_each_sg(data->sg, sg, data->sg_len, i) { 486 + if (sg->offset & 3 || sg->length & 3) 487 + return -EINVAL; 488 + } 489 + 490 + /* If we don't have a channel, we can't do DMA */ 491 + chan = host->dma.chan; 492 + if (chan) { 493 + dma_chan_get(chan); 494 + host->data_chan = chan; 495 + } 496 + 497 + if (!chan) 498 + return -ENODEV; 499 + 500 + if (data->flags & MMC_DATA_READ) 501 + direction = DMA_FROM_DEVICE; 502 + else 503 + direction = DMA_TO_DEVICE; 504 + 505 + desc = chan->device->device_prep_slave_sg(chan, 506 + data->sg, data->sg_len, direction, 507 + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 508 + if (!desc) 509 + return -ENOMEM; 510 + 511 + host->dma.data_desc = desc; 512 + desc->callback = atmci_dma_complete; 513 + desc->callback_param = host; 514 + desc->tx_submit(desc); 515 + 516 + /* Go! */ 517 + chan->device->device_issue_pending(chan); 518 + 519 + return 0; 520 + } 521 + 522 + #else /* CONFIG_MMC_ATMELMCI_DMA */ 523 + 524 + static int atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) 525 + { 526 + return -ENOSYS; 527 + } 528 + 529 + static void atmci_stop_dma(struct atmel_mci *host) 530 + { 531 + /* Data transfer was stopped by the interrupt handler */ 532 + atmci_set_pending(host, EVENT_XFER_COMPLETE); 533 + mci_writel(host, IER, MCI_NOTBUSY); 534 + } 535 + 536 + #endif /* CONFIG_MMC_ATMELMCI_DMA */ 517 537 518 538 /* 519 539 * Returns a mask of interrupt flags to be enabled after the whole 520 540 * request has been prepared. 521 541 */ 522 - static u32 atmci_submit_data(struct mmc_host *mmc, struct mmc_data *data) 542 + static u32 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data) 523 543 { 524 - struct atmel_mci *host = mmc_priv(mmc); 525 - u32 iflags; 544 + u32 iflags; 526 545 527 546 data->error = -EINPROGRESS; 528 547 ··· 653 426 host->sg = NULL; 654 427 host->data = data; 655 428 656 - dev_vdbg(&mmc->class_dev, "BLKR=0x%08x\n", 657 - MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz)); 658 - 659 429 iflags = ATMCI_DATA_ERROR_FLAGS; 660 - host->sg = data->sg; 661 - host->pio_offset = 0; 662 - if (data->flags & MMC_DATA_READ) 663 - iflags |= MCI_RXRDY; 664 - else 665 - iflags |= MCI_TXRDY; 430 + if (atmci_submit_data_dma(host, data)) { 431 + host->data_chan = NULL; 432 + 433 + /* 434 + * Errata: MMC data write operation with less than 12 435 + * bytes is impossible. 436 + * 437 + * Errata: MCI Transmit Data Register (TDR) FIFO 438 + * corruption when length is not multiple of 4. 439 + */ 440 + if (data->blocks * data->blksz < 12 441 + || (data->blocks * data->blksz) & 3) 442 + host->need_reset = true; 443 + 444 + host->sg = data->sg; 445 + host->pio_offset = 0; 446 + if (data->flags & MMC_DATA_READ) 447 + iflags |= MCI_RXRDY; 448 + else 449 + iflags |= MCI_TXRDY; 450 + } 666 451 667 452 return iflags; 668 453 } 669 454 670 - static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 455 + static void atmci_start_request(struct atmel_mci *host, 456 + struct atmel_mci_slot *slot) 671 457 { 672 - struct atmel_mci *host = mmc_priv(mmc); 673 - struct mmc_data *data; 458 + struct mmc_request *mrq; 674 459 struct mmc_command *cmd; 460 + struct mmc_data *data; 675 461 u32 iflags; 676 - u32 cmdflags = 0; 462 + u32 cmdflags; 463 + 464 + mrq = slot->mrq; 465 + host->cur_slot = slot; 466 + host->mrq = mrq; 467 + 468 + host->pending_events = 0; 469 + host->completed_events = 0; 470 + host->data_status = 0; 471 + 472 + if (host->need_reset) { 473 + mci_writel(host, CR, MCI_CR_SWRST); 474 + mci_writel(host, CR, MCI_CR_MCIEN); 475 + mci_writel(host, MR, host->mode_reg); 476 + host->need_reset = false; 477 + } 478 + mci_writel(host, SDCR, slot->sdc_reg); 677 479 678 480 iflags = mci_readl(host, IMR); 679 481 if (iflags) 680 - dev_warn(&mmc->class_dev, "WARNING: IMR=0x%08x\n", 681 - mci_readl(host, IMR)); 482 + dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", 483 + iflags); 682 484 683 - WARN_ON(host->mrq != NULL); 684 - 685 - /* 686 - * We may "know" the card is gone even though there's still an 687 - * electrical connection. If so, we really need to communicate 688 - * this to the MMC core since there won't be any more 689 - * interrupts as the card is completely removed. Otherwise, 690 - * the MMC core might believe the card is still there even 691 - * though the card was just removed very slowly. 692 - */ 693 - if (!host->present) { 694 - mrq->cmd->error = -ENOMEDIUM; 695 - mmc_request_done(mmc, mrq); 696 - return; 485 + if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { 486 + /* Send init sequence (74 clock cycles) */ 487 + mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT); 488 + while (!(mci_readl(host, SR) & MCI_CMDRDY)) 489 + cpu_relax(); 697 490 } 698 - 699 - host->mrq = mrq; 700 - host->pending_events = 0; 701 - host->completed_events = 0; 702 - 703 - atmci_enable(host); 704 - 705 - /* We don't support multiple blocks of weird lengths. */ 706 491 data = mrq->data; 707 492 if (data) { 708 - if (data->blocks > 1 && data->blksz & 3) 709 - goto fail; 710 - atmci_set_timeout(host, data); 493 + atmci_set_timeout(host, slot, data); 711 494 712 495 /* Must set block count/size before sending command */ 713 496 mci_writel(host, BLKR, MCI_BCNT(data->blocks) 714 497 | MCI_BLKLEN(data->blksz)); 498 + dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", 499 + MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz)); 715 500 } 716 501 717 502 iflags = MCI_CMDRDY; 718 503 cmd = mrq->cmd; 719 - cmdflags = atmci_prepare_command(mmc, cmd); 504 + cmdflags = atmci_prepare_command(slot->mmc, cmd); 720 505 atmci_start_command(host, cmd, cmdflags); 721 506 722 507 if (data) 723 - iflags |= atmci_submit_data(mmc, data); 508 + iflags |= atmci_submit_data(host, data); 724 509 725 510 if (mrq->stop) { 726 - host->stop_cmdr = atmci_prepare_command(mmc, mrq->stop); 511 + host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); 727 512 host->stop_cmdr |= MCI_CMDR_STOP_XFER; 728 513 if (!(data->flags & MMC_DATA_WRITE)) 729 514 host->stop_cmdr |= MCI_CMDR_TRDIR_READ; ··· 752 513 * prepared yet.) 753 514 */ 754 515 mci_writel(host, IER, iflags); 516 + } 755 517 756 - return; 518 + static void atmci_queue_request(struct atmel_mci *host, 519 + struct atmel_mci_slot *slot, struct mmc_request *mrq) 520 + { 521 + dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 522 + host->state); 757 523 758 - fail: 759 - atmci_disable(host); 760 - host->mrq = NULL; 761 - mrq->cmd->error = -EINVAL; 762 - mmc_request_done(mmc, mrq); 524 + spin_lock_bh(&host->lock); 525 + slot->mrq = mrq; 526 + if (host->state == STATE_IDLE) { 527 + host->state = STATE_SENDING_CMD; 528 + atmci_start_request(host, slot); 529 + } else { 530 + list_add_tail(&slot->queue_node, &host->queue); 531 + } 532 + spin_unlock_bh(&host->lock); 533 + } 534 + 535 + static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 536 + { 537 + struct atmel_mci_slot *slot = mmc_priv(mmc); 538 + struct atmel_mci *host = slot->host; 539 + struct mmc_data *data; 540 + 541 + WARN_ON(slot->mrq); 542 + 543 + /* 544 + * We may "know" the card is gone even though there's still an 545 + * electrical connection. If so, we really need to communicate 546 + * this to the MMC core since there won't be any more 547 + * interrupts as the card is completely removed. Otherwise, 548 + * the MMC core might believe the card is still there even 549 + * though the card was just removed very slowly. 550 + */ 551 + if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { 552 + mrq->cmd->error = -ENOMEDIUM; 553 + mmc_request_done(mmc, mrq); 554 + return; 555 + } 556 + 557 + /* We don't support multiple blocks of weird lengths. */ 558 + data = mrq->data; 559 + if (data && data->blocks > 1 && data->blksz & 3) { 560 + mrq->cmd->error = -EINVAL; 561 + mmc_request_done(mmc, mrq); 562 + } 563 + 564 + atmci_queue_request(host, slot, mrq); 763 565 } 764 566 765 567 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 766 568 { 767 - struct atmel_mci *host = mmc_priv(mmc); 569 + struct atmel_mci_slot *slot = mmc_priv(mmc); 570 + struct atmel_mci *host = slot->host; 571 + unsigned int i; 572 + 573 + slot->sdc_reg &= ~MCI_SDCBUS_MASK; 574 + switch (ios->bus_width) { 575 + case MMC_BUS_WIDTH_1: 576 + slot->sdc_reg |= MCI_SDCBUS_1BIT; 577 + break; 578 + case MMC_BUS_WIDTH_4: 579 + slot->sdc_reg = MCI_SDCBUS_4BIT; 580 + break; 581 + } 768 582 769 583 if (ios->clock) { 584 + unsigned int clock_min = ~0U; 770 585 u32 clkdiv; 771 586 772 - /* Set clock rate */ 773 - clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * ios->clock) - 1; 587 + spin_lock_bh(&host->lock); 588 + if (!host->mode_reg) { 589 + clk_enable(host->mck); 590 + mci_writel(host, CR, MCI_CR_SWRST); 591 + mci_writel(host, CR, MCI_CR_MCIEN); 592 + } 593 + 594 + /* 595 + * Use mirror of ios->clock to prevent race with mmc 596 + * core ios update when finding the minimum. 597 + */ 598 + slot->clock = ios->clock; 599 + for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 600 + if (host->slot[i] && host->slot[i]->clock 601 + && host->slot[i]->clock < clock_min) 602 + clock_min = host->slot[i]->clock; 603 + } 604 + 605 + /* Calculate clock divider */ 606 + clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; 774 607 if (clkdiv > 255) { 775 608 dev_warn(&mmc->class_dev, 776 609 "clock %u too slow; using %lu\n", 777 - ios->clock, host->bus_hz / (2 * 256)); 610 + clock_min, host->bus_hz / (2 * 256)); 778 611 clkdiv = 255; 779 612 } 780 613 614 + /* 615 + * WRPROOF and RDPROOF prevent overruns/underruns by 616 + * stopping the clock when the FIFO is full/empty. 617 + * This state is not expected to last for long. 618 + */ 781 619 host->mode_reg = MCI_MR_CLKDIV(clkdiv) | MCI_MR_WRPROOF 782 620 | MCI_MR_RDPROOF; 783 - } 784 621 785 - switch (ios->bus_width) { 786 - case MMC_BUS_WIDTH_1: 787 - host->sdc_reg = 0; 788 - break; 789 - case MMC_BUS_WIDTH_4: 790 - host->sdc_reg = MCI_SDCBUS_4BIT; 791 - break; 622 + if (list_empty(&host->queue)) 623 + mci_writel(host, MR, host->mode_reg); 624 + else 625 + host->need_clock_update = true; 626 + 627 + spin_unlock_bh(&host->lock); 628 + } else { 629 + bool any_slot_active = false; 630 + 631 + spin_lock_bh(&host->lock); 632 + slot->clock = 0; 633 + for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 634 + if (host->slot[i] && host->slot[i]->clock) { 635 + any_slot_active = true; 636 + break; 637 + } 638 + } 639 + if (!any_slot_active) { 640 + mci_writel(host, CR, MCI_CR_MCIDIS); 641 + if (host->mode_reg) { 642 + mci_readl(host, MR); 643 + clk_disable(host->mck); 644 + } 645 + host->mode_reg = 0; 646 + } 647 + spin_unlock_bh(&host->lock); 792 648 } 793 649 794 650 switch (ios->power_mode) { 795 - case MMC_POWER_ON: 796 - /* Send init sequence (74 clock cycles) */ 797 - atmci_enable(host); 798 - mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT); 799 - while (!(mci_readl(host, SR) & MCI_CMDRDY)) 800 - cpu_relax(); 801 - atmci_disable(host); 651 + case MMC_POWER_UP: 652 + set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); 802 653 break; 803 654 default: 804 655 /* 805 656 * TODO: None of the currently available AVR32-based 806 657 * boards allow MMC power to be turned off. Implement 807 658 * power control when this can be tested properly. 659 + * 660 + * We also need to hook this into the clock management 661 + * somehow so that newly inserted cards aren't 662 + * subjected to a fast clock before we have a chance 663 + * to figure out what the maximum rate is. Currently, 664 + * there's no way to avoid this, and there never will 665 + * be for boards that don't support power control. 808 666 */ 809 667 break; 810 668 } ··· 909 573 910 574 static int atmci_get_ro(struct mmc_host *mmc) 911 575 { 912 - int read_only = 0; 913 - struct atmel_mci *host = mmc_priv(mmc); 576 + int read_only = -ENOSYS; 577 + struct atmel_mci_slot *slot = mmc_priv(mmc); 914 578 915 - if (gpio_is_valid(host->wp_pin)) { 916 - read_only = gpio_get_value(host->wp_pin); 579 + if (gpio_is_valid(slot->wp_pin)) { 580 + read_only = gpio_get_value(slot->wp_pin); 917 581 dev_dbg(&mmc->class_dev, "card is %s\n", 918 582 read_only ? "read-only" : "read-write"); 919 - } else { 920 - dev_dbg(&mmc->class_dev, 921 - "no pin for checking read-only switch." 922 - " Assuming write-enable.\n"); 923 583 } 924 584 925 585 return read_only; 926 586 } 927 587 928 - static struct mmc_host_ops atmci_ops = { 588 + static int atmci_get_cd(struct mmc_host *mmc) 589 + { 590 + int present = -ENOSYS; 591 + struct atmel_mci_slot *slot = mmc_priv(mmc); 592 + 593 + if (gpio_is_valid(slot->detect_pin)) { 594 + present = !gpio_get_value(slot->detect_pin); 595 + dev_dbg(&mmc->class_dev, "card is %spresent\n", 596 + present ? "" : "not "); 597 + } 598 + 599 + return present; 600 + } 601 + 602 + static const struct mmc_host_ops atmci_ops = { 929 603 .request = atmci_request, 930 604 .set_ios = atmci_set_ios, 931 605 .get_ro = atmci_get_ro, 606 + .get_cd = atmci_get_cd, 932 607 }; 933 608 934 - static void atmci_command_complete(struct atmel_mci *host, 935 - struct mmc_command *cmd, u32 status) 609 + /* Called with host->lock held */ 610 + static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) 611 + __releases(&host->lock) 612 + __acquires(&host->lock) 936 613 { 614 + struct atmel_mci_slot *slot = NULL; 615 + struct mmc_host *prev_mmc = host->cur_slot->mmc; 616 + 617 + WARN_ON(host->cmd || host->data); 618 + 619 + /* 620 + * Update the MMC clock rate if necessary. This may be 621 + * necessary if set_ios() is called when a different slot is 622 + * busy transfering data. 623 + */ 624 + if (host->need_clock_update) 625 + mci_writel(host, MR, host->mode_reg); 626 + 627 + host->cur_slot->mrq = NULL; 628 + host->mrq = NULL; 629 + if (!list_empty(&host->queue)) { 630 + slot = list_entry(host->queue.next, 631 + struct atmel_mci_slot, queue_node); 632 + list_del(&slot->queue_node); 633 + dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", 634 + mmc_hostname(slot->mmc)); 635 + host->state = STATE_SENDING_CMD; 636 + atmci_start_request(host, slot); 637 + } else { 638 + dev_vdbg(&host->pdev->dev, "list empty\n"); 639 + host->state = STATE_IDLE; 640 + } 641 + 642 + spin_unlock(&host->lock); 643 + mmc_request_done(prev_mmc, mrq); 644 + spin_lock(&host->lock); 645 + } 646 + 647 + static void atmci_command_complete(struct atmel_mci *host, 648 + struct mmc_command *cmd) 649 + { 650 + u32 status = host->cmd_status; 651 + 937 652 /* Read the response from the card (up to 16 bytes) */ 938 653 cmd->resp[0] = mci_readl(host, RSPR); 939 654 cmd->resp[1] = mci_readl(host, RSPR); ··· 1001 614 cmd->error = 0; 1002 615 1003 616 if (cmd->error) { 1004 - dev_dbg(&host->mmc->class_dev, 617 + dev_dbg(&host->pdev->dev, 1005 618 "command error: status=0x%08x\n", status); 1006 619 1007 620 if (cmd->data) { 1008 621 host->data = NULL; 622 + atmci_stop_dma(host); 1009 623 mci_writel(host, IDR, MCI_NOTBUSY 1010 624 | MCI_TXRDY | MCI_RXRDY 1011 625 | ATMCI_DATA_ERROR_FLAGS); ··· 1016 628 1017 629 static void atmci_detect_change(unsigned long data) 1018 630 { 1019 - struct atmel_mci *host = (struct atmel_mci *)data; 1020 - struct mmc_request *mrq = host->mrq; 1021 - int present; 631 + struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data; 632 + bool present; 633 + bool present_old; 1022 634 1023 635 /* 1024 - * atmci_remove() sets detect_pin to -1 before freeing the 1025 - * interrupt. We must not re-enable the interrupt if it has 1026 - * been freed. 636 + * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before 637 + * freeing the interrupt. We must not re-enable the interrupt 638 + * if it has been freed, and if we're shutting down, it 639 + * doesn't really matter whether the card is present or not. 1027 640 */ 1028 641 smp_rmb(); 1029 - if (!gpio_is_valid(host->detect_pin)) 642 + if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) 1030 643 return; 1031 644 1032 - enable_irq(gpio_to_irq(host->detect_pin)); 1033 - present = !gpio_get_value(host->detect_pin); 645 + enable_irq(gpio_to_irq(slot->detect_pin)); 646 + present = !gpio_get_value(slot->detect_pin); 647 + present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); 1034 648 1035 - dev_vdbg(&host->pdev->dev, "detect change: %d (was %d)\n", 1036 - present, host->present); 649 + dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", 650 + present, present_old); 1037 651 1038 - if (present != host->present) { 1039 - dev_dbg(&host->mmc->class_dev, "card %s\n", 652 + if (present != present_old) { 653 + struct atmel_mci *host = slot->host; 654 + struct mmc_request *mrq; 655 + 656 + dev_dbg(&slot->mmc->class_dev, "card %s\n", 1040 657 present ? "inserted" : "removed"); 1041 - host->present = present; 1042 658 1043 - /* Reset controller if card is gone */ 1044 - if (!present) { 1045 - mci_writel(host, CR, MCI_CR_SWRST); 1046 - mci_writel(host, IDR, ~0UL); 1047 - mci_writel(host, CR, MCI_CR_MCIEN); 1048 - } 659 + spin_lock(&host->lock); 660 + 661 + if (!present) 662 + clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 663 + else 664 + set_bit(ATMCI_CARD_PRESENT, &slot->flags); 1049 665 1050 666 /* Clean up queue if present */ 667 + mrq = slot->mrq; 1051 668 if (mrq) { 1052 - /* 1053 - * Reset controller to terminate any ongoing 1054 - * commands or data transfers. 1055 - */ 1056 - mci_writel(host, CR, MCI_CR_SWRST); 669 + if (mrq == host->mrq) { 670 + /* 671 + * Reset controller to terminate any ongoing 672 + * commands or data transfers. 673 + */ 674 + mci_writel(host, CR, MCI_CR_SWRST); 675 + mci_writel(host, CR, MCI_CR_MCIEN); 676 + mci_writel(host, MR, host->mode_reg); 1057 677 1058 - if (!atmci_is_completed(host, EVENT_CMD_COMPLETE)) 1059 - mrq->cmd->error = -ENOMEDIUM; 1060 - 1061 - if (mrq->data && !atmci_is_completed(host, 1062 - EVENT_DATA_COMPLETE)) { 1063 678 host->data = NULL; 1064 - mrq->data->error = -ENOMEDIUM; 679 + host->cmd = NULL; 680 + 681 + switch (host->state) { 682 + case STATE_IDLE: 683 + break; 684 + case STATE_SENDING_CMD: 685 + mrq->cmd->error = -ENOMEDIUM; 686 + if (!mrq->data) 687 + break; 688 + /* fall through */ 689 + case STATE_SENDING_DATA: 690 + mrq->data->error = -ENOMEDIUM; 691 + atmci_stop_dma(host); 692 + break; 693 + case STATE_DATA_BUSY: 694 + case STATE_DATA_ERROR: 695 + if (mrq->data->error == -EINPROGRESS) 696 + mrq->data->error = -ENOMEDIUM; 697 + if (!mrq->stop) 698 + break; 699 + /* fall through */ 700 + case STATE_SENDING_STOP: 701 + mrq->stop->error = -ENOMEDIUM; 702 + break; 703 + } 704 + 705 + atmci_request_end(host, mrq); 706 + } else { 707 + list_del(&slot->queue_node); 708 + mrq->cmd->error = -ENOMEDIUM; 709 + if (mrq->data) 710 + mrq->data->error = -ENOMEDIUM; 711 + if (mrq->stop) 712 + mrq->stop->error = -ENOMEDIUM; 713 + 714 + spin_unlock(&host->lock); 715 + mmc_request_done(slot->mmc, mrq); 716 + spin_lock(&host->lock); 1065 717 } 1066 - if (mrq->stop && !atmci_is_completed(host, 1067 - EVENT_STOP_COMPLETE)) 1068 - mrq->stop->error = -ENOMEDIUM; 1069 - 1070 - host->cmd = NULL; 1071 - atmci_request_end(host->mmc, mrq); 1072 718 } 719 + spin_unlock(&host->lock); 1073 720 1074 - mmc_detect_change(host->mmc, 0); 721 + mmc_detect_change(slot->mmc, 0); 1075 722 } 1076 723 } 1077 724 1078 725 static void atmci_tasklet_func(unsigned long priv) 1079 726 { 1080 - struct mmc_host *mmc = (struct mmc_host *)priv; 1081 - struct atmel_mci *host = mmc_priv(mmc); 727 + struct atmel_mci *host = (struct atmel_mci *)priv; 1082 728 struct mmc_request *mrq = host->mrq; 1083 729 struct mmc_data *data = host->data; 730 + struct mmc_command *cmd = host->cmd; 731 + enum atmel_mci_state state = host->state; 732 + enum atmel_mci_state prev_state; 733 + u32 status; 1084 734 1085 - dev_vdbg(&mmc->class_dev, 1086 - "tasklet: pending/completed/mask %lx/%lx/%x\n", 1087 - host->pending_events, host->completed_events, 735 + spin_lock(&host->lock); 736 + 737 + state = host->state; 738 + 739 + dev_vdbg(&host->pdev->dev, 740 + "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", 741 + state, host->pending_events, host->completed_events, 1088 742 mci_readl(host, IMR)); 1089 743 1090 - if (atmci_test_and_clear_pending(host, EVENT_CMD_COMPLETE)) { 1091 - /* 1092 - * host->cmd must be set to NULL before the interrupt 1093 - * handler sees EVENT_CMD_COMPLETE 1094 - */ 1095 - host->cmd = NULL; 1096 - smp_wmb(); 1097 - atmci_set_completed(host, EVENT_CMD_COMPLETE); 1098 - atmci_command_complete(host, mrq->cmd, host->cmd_status); 744 + do { 745 + prev_state = state; 1099 746 1100 - if (!mrq->cmd->error && mrq->stop 1101 - && atmci_is_completed(host, EVENT_XFER_COMPLETE) 1102 - && !atmci_test_and_set_completed(host, 1103 - EVENT_STOP_SENT)) 1104 - send_stop_cmd(host->mmc, mrq->data); 1105 - } 1106 - if (atmci_test_and_clear_pending(host, EVENT_STOP_COMPLETE)) { 1107 - /* 1108 - * host->cmd must be set to NULL before the interrupt 1109 - * handler sees EVENT_STOP_COMPLETE 1110 - */ 1111 - host->cmd = NULL; 1112 - smp_wmb(); 1113 - atmci_set_completed(host, EVENT_STOP_COMPLETE); 1114 - atmci_command_complete(host, mrq->stop, host->stop_status); 1115 - } 1116 - if (atmci_test_and_clear_pending(host, EVENT_DATA_ERROR)) { 1117 - u32 status = host->data_status; 747 + switch (state) { 748 + case STATE_IDLE: 749 + break; 1118 750 1119 - dev_vdbg(&mmc->class_dev, "data error: status=%08x\n", status); 751 + case STATE_SENDING_CMD: 752 + if (!atmci_test_and_clear_pending(host, 753 + EVENT_CMD_COMPLETE)) 754 + break; 1120 755 1121 - atmci_set_completed(host, EVENT_DATA_ERROR); 1122 - atmci_set_completed(host, EVENT_DATA_COMPLETE); 756 + host->cmd = NULL; 757 + atmci_set_completed(host, EVENT_CMD_COMPLETE); 758 + atmci_command_complete(host, mrq->cmd); 759 + if (!mrq->data || cmd->error) { 760 + atmci_request_end(host, host->mrq); 761 + goto unlock; 762 + } 1123 763 1124 - if (status & MCI_DTOE) { 1125 - dev_dbg(&mmc->class_dev, 1126 - "data timeout error\n"); 1127 - data->error = -ETIMEDOUT; 1128 - } else if (status & MCI_DCRCE) { 1129 - dev_dbg(&mmc->class_dev, "data CRC error\n"); 1130 - data->error = -EILSEQ; 1131 - } else { 1132 - dev_dbg(&mmc->class_dev, 1133 - "data FIFO error (status=%08x)\n", 1134 - status); 1135 - data->error = -EIO; 764 + prev_state = state = STATE_SENDING_DATA; 765 + /* fall through */ 766 + 767 + case STATE_SENDING_DATA: 768 + if (atmci_test_and_clear_pending(host, 769 + EVENT_DATA_ERROR)) { 770 + atmci_stop_dma(host); 771 + if (data->stop) 772 + send_stop_cmd(host, data); 773 + state = STATE_DATA_ERROR; 774 + break; 775 + } 776 + 777 + if (!atmci_test_and_clear_pending(host, 778 + EVENT_XFER_COMPLETE)) 779 + break; 780 + 781 + atmci_set_completed(host, EVENT_XFER_COMPLETE); 782 + prev_state = state = STATE_DATA_BUSY; 783 + /* fall through */ 784 + 785 + case STATE_DATA_BUSY: 786 + if (!atmci_test_and_clear_pending(host, 787 + EVENT_DATA_COMPLETE)) 788 + break; 789 + 790 + host->data = NULL; 791 + atmci_set_completed(host, EVENT_DATA_COMPLETE); 792 + status = host->data_status; 793 + if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) { 794 + if (status & MCI_DTOE) { 795 + dev_dbg(&host->pdev->dev, 796 + "data timeout error\n"); 797 + data->error = -ETIMEDOUT; 798 + } else if (status & MCI_DCRCE) { 799 + dev_dbg(&host->pdev->dev, 800 + "data CRC error\n"); 801 + data->error = -EILSEQ; 802 + } else { 803 + dev_dbg(&host->pdev->dev, 804 + "data FIFO error (status=%08x)\n", 805 + status); 806 + data->error = -EIO; 807 + } 808 + } else { 809 + data->bytes_xfered = data->blocks * data->blksz; 810 + data->error = 0; 811 + } 812 + 813 + if (!data->stop) { 814 + atmci_request_end(host, host->mrq); 815 + goto unlock; 816 + } 817 + 818 + prev_state = state = STATE_SENDING_STOP; 819 + if (!data->error) 820 + send_stop_cmd(host, data); 821 + /* fall through */ 822 + 823 + case STATE_SENDING_STOP: 824 + if (!atmci_test_and_clear_pending(host, 825 + EVENT_CMD_COMPLETE)) 826 + break; 827 + 828 + host->cmd = NULL; 829 + atmci_command_complete(host, mrq->stop); 830 + atmci_request_end(host, host->mrq); 831 + goto unlock; 832 + 833 + case STATE_DATA_ERROR: 834 + if (!atmci_test_and_clear_pending(host, 835 + EVENT_XFER_COMPLETE)) 836 + break; 837 + 838 + state = STATE_DATA_BUSY; 839 + break; 1136 840 } 841 + } while (state != prev_state); 1137 842 1138 - if (host->present && data->stop 1139 - && atmci_is_completed(host, EVENT_CMD_COMPLETE) 1140 - && !atmci_test_and_set_completed( 1141 - host, EVENT_STOP_SENT)) 1142 - send_stop_cmd(host->mmc, data); 843 + host->state = state; 1143 844 1144 - host->data = NULL; 1145 - } 1146 - if (atmci_test_and_clear_pending(host, EVENT_DATA_COMPLETE)) { 1147 - atmci_set_completed(host, EVENT_DATA_COMPLETE); 1148 - 1149 - if (!atmci_is_completed(host, EVENT_DATA_ERROR)) { 1150 - data->bytes_xfered = data->blocks * data->blksz; 1151 - data->error = 0; 1152 - } 1153 - 1154 - host->data = NULL; 1155 - } 1156 - 1157 - if (host->mrq && !host->cmd && !host->data) 1158 - atmci_request_end(mmc, host->mrq); 845 + unlock: 846 + spin_unlock(&host->lock); 1159 847 } 1160 848 1161 849 static void atmci_read_data_pio(struct atmel_mci *host) ··· 1253 789 nbytes += 4; 1254 790 1255 791 if (offset == sg->length) { 792 + flush_dcache_page(sg_page(sg)); 1256 793 host->sg = sg = sg_next(sg); 1257 794 if (!sg) 1258 795 goto done; ··· 1282 817 mci_writel(host, IDR, (MCI_NOTBUSY | MCI_RXRDY 1283 818 | ATMCI_DATA_ERROR_FLAGS)); 1284 819 host->data_status = status; 820 + data->bytes_xfered += nbytes; 821 + smp_wmb(); 1285 822 atmci_set_pending(host, EVENT_DATA_ERROR); 1286 823 tasklet_schedule(&host->tasklet); 1287 - break; 824 + return; 1288 825 } 1289 826 } while (status & MCI_RXRDY); 1290 827 ··· 1299 832 mci_writel(host, IDR, MCI_RXRDY); 1300 833 mci_writel(host, IER, MCI_NOTBUSY); 1301 834 data->bytes_xfered += nbytes; 1302 - atmci_set_completed(host, EVENT_XFER_COMPLETE); 1303 - if (data->stop && atmci_is_completed(host, EVENT_CMD_COMPLETE) 1304 - && !atmci_test_and_set_completed(host, EVENT_STOP_SENT)) 1305 - send_stop_cmd(host->mmc, data); 835 + smp_wmb(); 836 + atmci_set_pending(host, EVENT_XFER_COMPLETE); 1306 837 } 1307 838 1308 839 static void atmci_write_data_pio(struct atmel_mci *host) ··· 1353 888 mci_writel(host, IDR, (MCI_NOTBUSY | MCI_TXRDY 1354 889 | ATMCI_DATA_ERROR_FLAGS)); 1355 890 host->data_status = status; 891 + data->bytes_xfered += nbytes; 892 + smp_wmb(); 1356 893 atmci_set_pending(host, EVENT_DATA_ERROR); 1357 894 tasklet_schedule(&host->tasklet); 1358 - break; 895 + return; 1359 896 } 1360 897 } while (status & MCI_TXRDY); 1361 898 ··· 1370 903 mci_writel(host, IDR, MCI_TXRDY); 1371 904 mci_writel(host, IER, MCI_NOTBUSY); 1372 905 data->bytes_xfered += nbytes; 1373 - atmci_set_completed(host, EVENT_XFER_COMPLETE); 1374 - if (data->stop && atmci_is_completed(host, EVENT_CMD_COMPLETE) 1375 - && !atmci_test_and_set_completed(host, EVENT_STOP_SENT)) 1376 - send_stop_cmd(host->mmc, data); 906 + smp_wmb(); 907 + atmci_set_pending(host, EVENT_XFER_COMPLETE); 1377 908 } 1378 909 1379 - static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status) 910 + static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status) 1380 911 { 1381 - struct atmel_mci *host = mmc_priv(mmc); 1382 - 1383 912 mci_writel(host, IDR, MCI_CMDRDY); 1384 913 1385 - if (atmci_is_completed(host, EVENT_STOP_SENT)) { 1386 - host->stop_status = status; 1387 - atmci_set_pending(host, EVENT_STOP_COMPLETE); 1388 - } else { 1389 - host->cmd_status = status; 1390 - atmci_set_pending(host, EVENT_CMD_COMPLETE); 1391 - } 1392 - 914 + host->cmd_status = status; 915 + smp_wmb(); 916 + atmci_set_pending(host, EVENT_CMD_COMPLETE); 1393 917 tasklet_schedule(&host->tasklet); 1394 918 } 1395 919 1396 920 static irqreturn_t atmci_interrupt(int irq, void *dev_id) 1397 921 { 1398 - struct mmc_host *mmc = dev_id; 1399 - struct atmel_mci *host = mmc_priv(mmc); 922 + struct atmel_mci *host = dev_id; 1400 923 u32 status, mask, pending; 1401 924 unsigned int pass_count = 0; 1402 - 1403 - spin_lock(&mmc->lock); 1404 925 1405 926 do { 1406 927 status = mci_readl(host, SR); ··· 1401 946 mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS 1402 947 | MCI_RXRDY | MCI_TXRDY); 1403 948 pending &= mci_readl(host, IMR); 949 + 1404 950 host->data_status = status; 951 + smp_wmb(); 1405 952 atmci_set_pending(host, EVENT_DATA_ERROR); 1406 953 tasklet_schedule(&host->tasklet); 1407 954 } 1408 955 if (pending & MCI_NOTBUSY) { 1409 - mci_writel(host, IDR, (MCI_NOTBUSY 1410 - | ATMCI_DATA_ERROR_FLAGS)); 956 + mci_writel(host, IDR, 957 + ATMCI_DATA_ERROR_FLAGS | MCI_NOTBUSY); 958 + if (!host->data_status) 959 + host->data_status = status; 960 + smp_wmb(); 1411 961 atmci_set_pending(host, EVENT_DATA_COMPLETE); 1412 962 tasklet_schedule(&host->tasklet); 1413 963 } ··· 1422 962 atmci_write_data_pio(host); 1423 963 1424 964 if (pending & MCI_CMDRDY) 1425 - atmci_cmd_interrupt(mmc, status); 965 + atmci_cmd_interrupt(host, status); 1426 966 } while (pass_count++ < 5); 1427 - 1428 - spin_unlock(&mmc->lock); 1429 967 1430 968 return pass_count ? IRQ_HANDLED : IRQ_NONE; 1431 969 } 1432 970 1433 971 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) 1434 972 { 1435 - struct mmc_host *mmc = dev_id; 1436 - struct atmel_mci *host = mmc_priv(mmc); 973 + struct atmel_mci_slot *slot = dev_id; 1437 974 1438 975 /* 1439 976 * Disable interrupts until the pin has stabilized and check ··· 1438 981 * middle of the timer routine when this interrupt triggers. 1439 982 */ 1440 983 disable_irq_nosync(irq); 1441 - mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(20)); 984 + mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); 1442 985 1443 986 return IRQ_HANDLED; 987 + } 988 + 989 + #ifdef CONFIG_MMC_ATMELMCI_DMA 990 + 991 + static inline struct atmel_mci * 992 + dma_client_to_atmel_mci(struct dma_client *client) 993 + { 994 + return container_of(client, struct atmel_mci, dma.client); 995 + } 996 + 997 + static enum dma_state_client atmci_dma_event(struct dma_client *client, 998 + struct dma_chan *chan, enum dma_state state) 999 + { 1000 + struct atmel_mci *host; 1001 + enum dma_state_client ret = DMA_NAK; 1002 + 1003 + host = dma_client_to_atmel_mci(client); 1004 + 1005 + switch (state) { 1006 + case DMA_RESOURCE_AVAILABLE: 1007 + spin_lock_bh(&host->lock); 1008 + if (!host->dma.chan) { 1009 + host->dma.chan = chan; 1010 + ret = DMA_ACK; 1011 + } 1012 + spin_unlock_bh(&host->lock); 1013 + 1014 + if (ret == DMA_ACK) 1015 + dev_info(&host->pdev->dev, 1016 + "Using %s for DMA transfers\n", 1017 + chan->dev.bus_id); 1018 + break; 1019 + 1020 + case DMA_RESOURCE_REMOVED: 1021 + spin_lock_bh(&host->lock); 1022 + if (host->dma.chan == chan) { 1023 + host->dma.chan = NULL; 1024 + ret = DMA_ACK; 1025 + } 1026 + spin_unlock_bh(&host->lock); 1027 + 1028 + if (ret == DMA_ACK) 1029 + dev_info(&host->pdev->dev, 1030 + "Lost %s, falling back to PIO\n", 1031 + chan->dev.bus_id); 1032 + break; 1033 + 1034 + default: 1035 + break; 1036 + } 1037 + 1038 + 1039 + return ret; 1040 + } 1041 + #endif /* CONFIG_MMC_ATMELMCI_DMA */ 1042 + 1043 + static int __init atmci_init_slot(struct atmel_mci *host, 1044 + struct mci_slot_pdata *slot_data, unsigned int id, 1045 + u32 sdc_reg) 1046 + { 1047 + struct mmc_host *mmc; 1048 + struct atmel_mci_slot *slot; 1049 + 1050 + mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); 1051 + if (!mmc) 1052 + return -ENOMEM; 1053 + 1054 + slot = mmc_priv(mmc); 1055 + slot->mmc = mmc; 1056 + slot->host = host; 1057 + slot->detect_pin = slot_data->detect_pin; 1058 + slot->wp_pin = slot_data->wp_pin; 1059 + slot->sdc_reg = sdc_reg; 1060 + 1061 + mmc->ops = &atmci_ops; 1062 + mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); 1063 + mmc->f_max = host->bus_hz / 2; 1064 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1065 + if (slot_data->bus_width >= 4) 1066 + mmc->caps |= MMC_CAP_4_BIT_DATA; 1067 + 1068 + mmc->max_hw_segs = 64; 1069 + mmc->max_phys_segs = 64; 1070 + mmc->max_req_size = 32768 * 512; 1071 + mmc->max_blk_size = 32768; 1072 + mmc->max_blk_count = 512; 1073 + 1074 + /* Assume card is present initially */ 1075 + set_bit(ATMCI_CARD_PRESENT, &slot->flags); 1076 + if (gpio_is_valid(slot->detect_pin)) { 1077 + if (gpio_request(slot->detect_pin, "mmc_detect")) { 1078 + dev_dbg(&mmc->class_dev, "no detect pin available\n"); 1079 + slot->detect_pin = -EBUSY; 1080 + } else if (gpio_get_value(slot->detect_pin)) { 1081 + clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 1082 + } 1083 + } 1084 + 1085 + if (!gpio_is_valid(slot->detect_pin)) 1086 + mmc->caps |= MMC_CAP_NEEDS_POLL; 1087 + 1088 + if (gpio_is_valid(slot->wp_pin)) { 1089 + if (gpio_request(slot->wp_pin, "mmc_wp")) { 1090 + dev_dbg(&mmc->class_dev, "no WP pin available\n"); 1091 + slot->wp_pin = -EBUSY; 1092 + } 1093 + } 1094 + 1095 + host->slot[id] = slot; 1096 + mmc_add_host(mmc); 1097 + 1098 + if (gpio_is_valid(slot->detect_pin)) { 1099 + int ret; 1100 + 1101 + setup_timer(&slot->detect_timer, atmci_detect_change, 1102 + (unsigned long)slot); 1103 + 1104 + ret = request_irq(gpio_to_irq(slot->detect_pin), 1105 + atmci_detect_interrupt, 1106 + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 1107 + "mmc-detect", slot); 1108 + if (ret) { 1109 + dev_dbg(&mmc->class_dev, 1110 + "could not request IRQ %d for detect pin\n", 1111 + gpio_to_irq(slot->detect_pin)); 1112 + gpio_free(slot->detect_pin); 1113 + slot->detect_pin = -EBUSY; 1114 + } 1115 + } 1116 + 1117 + atmci_init_debugfs(slot); 1118 + 1119 + return 0; 1120 + } 1121 + 1122 + static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot, 1123 + unsigned int id) 1124 + { 1125 + /* Debugfs stuff is cleaned up by mmc core */ 1126 + 1127 + set_bit(ATMCI_SHUTDOWN, &slot->flags); 1128 + smp_wmb(); 1129 + 1130 + mmc_remove_host(slot->mmc); 1131 + 1132 + if (gpio_is_valid(slot->detect_pin)) { 1133 + int pin = slot->detect_pin; 1134 + 1135 + free_irq(gpio_to_irq(pin), slot); 1136 + del_timer_sync(&slot->detect_timer); 1137 + gpio_free(pin); 1138 + } 1139 + if (gpio_is_valid(slot->wp_pin)) 1140 + gpio_free(slot->wp_pin); 1141 + 1142 + slot->host->slot[id] = NULL; 1143 + mmc_free_host(slot->mmc); 1444 1144 } 1445 1145 1446 1146 static int __init atmci_probe(struct platform_device *pdev) 1447 1147 { 1448 1148 struct mci_platform_data *pdata; 1449 - struct atmel_mci *host; 1450 - struct mmc_host *mmc; 1451 - struct resource *regs; 1452 - int irq; 1453 - int ret; 1149 + struct atmel_mci *host; 1150 + struct resource *regs; 1151 + unsigned int nr_slots; 1152 + int irq; 1153 + int ret; 1454 1154 1455 1155 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1456 1156 if (!regs) ··· 1619 1005 if (irq < 0) 1620 1006 return irq; 1621 1007 1622 - mmc = mmc_alloc_host(sizeof(struct atmel_mci), &pdev->dev); 1623 - if (!mmc) 1008 + host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL); 1009 + if (!host) 1624 1010 return -ENOMEM; 1625 1011 1626 - host = mmc_priv(mmc); 1627 1012 host->pdev = pdev; 1628 - host->mmc = mmc; 1629 - host->detect_pin = pdata->detect_pin; 1630 - host->wp_pin = pdata->wp_pin; 1013 + spin_lock_init(&host->lock); 1014 + INIT_LIST_HEAD(&host->queue); 1631 1015 1632 1016 host->mck = clk_get(&pdev->dev, "mci_clk"); 1633 1017 if (IS_ERR(host->mck)) { ··· 1645 1033 1646 1034 host->mapbase = regs->start; 1647 1035 1648 - mmc->ops = &atmci_ops; 1649 - mmc->f_min = (host->bus_hz + 511) / 512; 1650 - mmc->f_max = host->bus_hz / 2; 1651 - mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1652 - mmc->caps |= MMC_CAP_4_BIT_DATA; 1036 + tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host); 1653 1037 1654 - mmc->max_hw_segs = 64; 1655 - mmc->max_phys_segs = 64; 1656 - mmc->max_req_size = 32768 * 512; 1657 - mmc->max_blk_size = 32768; 1658 - mmc->max_blk_count = 512; 1659 - 1660 - tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)mmc); 1661 - 1662 - ret = request_irq(irq, atmci_interrupt, 0, pdev->dev.bus_id, mmc); 1038 + ret = request_irq(irq, atmci_interrupt, 0, pdev->dev.bus_id, host); 1663 1039 if (ret) 1664 1040 goto err_request_irq; 1665 1041 1666 - /* Assume card is present if we don't have a detect pin */ 1667 - host->present = 1; 1668 - if (gpio_is_valid(host->detect_pin)) { 1669 - if (gpio_request(host->detect_pin, "mmc_detect")) { 1670 - dev_dbg(&mmc->class_dev, "no detect pin available\n"); 1671 - host->detect_pin = -1; 1672 - } else { 1673 - host->present = !gpio_get_value(host->detect_pin); 1674 - } 1675 - } 1042 + #ifdef CONFIG_MMC_ATMELMCI_DMA 1043 + if (pdata->dma_slave) { 1044 + struct dma_slave *slave = pdata->dma_slave; 1676 1045 1677 - if (!gpio_is_valid(host->detect_pin)) 1678 - mmc->caps |= MMC_CAP_NEEDS_POLL; 1046 + slave->tx_reg = regs->start + MCI_TDR; 1047 + slave->rx_reg = regs->start + MCI_RDR; 1679 1048 1680 - if (gpio_is_valid(host->wp_pin)) { 1681 - if (gpio_request(host->wp_pin, "mmc_wp")) { 1682 - dev_dbg(&mmc->class_dev, "no WP pin available\n"); 1683 - host->wp_pin = -1; 1684 - } 1049 + /* Try to grab a DMA channel */ 1050 + host->dma.client.event_callback = atmci_dma_event; 1051 + dma_cap_set(DMA_SLAVE, host->dma.client.cap_mask); 1052 + host->dma.client.slave = slave; 1053 + 1054 + dma_async_client_register(&host->dma.client); 1055 + dma_async_client_chan_request(&host->dma.client); 1056 + } else { 1057 + dev_notice(&pdev->dev, "DMA not available, using PIO\n"); 1685 1058 } 1059 + #endif /* CONFIG_MMC_ATMELMCI_DMA */ 1686 1060 1687 1061 platform_set_drvdata(pdev, host); 1688 1062 1689 - mmc_add_host(mmc); 1690 - 1691 - if (gpio_is_valid(host->detect_pin)) { 1692 - setup_timer(&host->detect_timer, atmci_detect_change, 1693 - (unsigned long)host); 1694 - 1695 - ret = request_irq(gpio_to_irq(host->detect_pin), 1696 - atmci_detect_interrupt, 1697 - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 1698 - "mmc-detect", mmc); 1699 - if (ret) { 1700 - dev_dbg(&mmc->class_dev, 1701 - "could not request IRQ %d for detect pin\n", 1702 - gpio_to_irq(host->detect_pin)); 1703 - gpio_free(host->detect_pin); 1704 - host->detect_pin = -1; 1705 - } 1063 + /* We need at least one slot to succeed */ 1064 + nr_slots = 0; 1065 + ret = -ENODEV; 1066 + if (pdata->slot[0].bus_width) { 1067 + ret = atmci_init_slot(host, &pdata->slot[0], 1068 + MCI_SDCSEL_SLOT_A, 0); 1069 + if (!ret) 1070 + nr_slots++; 1071 + } 1072 + if (pdata->slot[1].bus_width) { 1073 + ret = atmci_init_slot(host, &pdata->slot[1], 1074 + MCI_SDCSEL_SLOT_B, 1); 1075 + if (!ret) 1076 + nr_slots++; 1706 1077 } 1707 1078 1708 - dev_info(&mmc->class_dev, 1709 - "Atmel MCI controller at 0x%08lx irq %d\n", 1710 - host->mapbase, irq); 1079 + if (!nr_slots) 1080 + goto err_init_slot; 1711 1081 1712 - atmci_init_debugfs(host); 1082 + dev_info(&pdev->dev, 1083 + "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", 1084 + host->mapbase, irq, nr_slots); 1713 1085 1714 1086 return 0; 1715 1087 1088 + err_init_slot: 1089 + #ifdef CONFIG_MMC_ATMELMCI_DMA 1090 + if (pdata->dma_slave) 1091 + dma_async_client_unregister(&host->dma.client); 1092 + #endif 1093 + free_irq(irq, host); 1716 1094 err_request_irq: 1717 1095 iounmap(host->regs); 1718 1096 err_ioremap: 1719 1097 clk_put(host->mck); 1720 1098 err_clk_get: 1721 - mmc_free_host(mmc); 1099 + kfree(host); 1722 1100 return ret; 1723 1101 } 1724 1102 1725 1103 static int __exit atmci_remove(struct platform_device *pdev) 1726 1104 { 1727 - struct atmel_mci *host = platform_get_drvdata(pdev); 1105 + struct atmel_mci *host = platform_get_drvdata(pdev); 1106 + unsigned int i; 1728 1107 1729 1108 platform_set_drvdata(pdev, NULL); 1730 1109 1731 - if (host) { 1732 - /* Debugfs stuff is cleaned up by mmc core */ 1733 - 1734 - if (gpio_is_valid(host->detect_pin)) { 1735 - int pin = host->detect_pin; 1736 - 1737 - /* Make sure the timer doesn't enable the interrupt */ 1738 - host->detect_pin = -1; 1739 - smp_wmb(); 1740 - 1741 - free_irq(gpio_to_irq(pin), host->mmc); 1742 - del_timer_sync(&host->detect_timer); 1743 - gpio_free(pin); 1744 - } 1745 - 1746 - mmc_remove_host(host->mmc); 1747 - 1748 - clk_enable(host->mck); 1749 - mci_writel(host, IDR, ~0UL); 1750 - mci_writel(host, CR, MCI_CR_MCIDIS); 1751 - mci_readl(host, SR); 1752 - clk_disable(host->mck); 1753 - 1754 - if (gpio_is_valid(host->wp_pin)) 1755 - gpio_free(host->wp_pin); 1756 - 1757 - free_irq(platform_get_irq(pdev, 0), host->mmc); 1758 - iounmap(host->regs); 1759 - 1760 - clk_put(host->mck); 1761 - 1762 - mmc_free_host(host->mmc); 1110 + for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 1111 + if (host->slot[i]) 1112 + atmci_cleanup_slot(host->slot[i], i); 1763 1113 } 1114 + 1115 + clk_enable(host->mck); 1116 + mci_writel(host, IDR, ~0UL); 1117 + mci_writel(host, CR, MCI_CR_MCIDIS); 1118 + mci_readl(host, SR); 1119 + clk_disable(host->mck); 1120 + 1121 + #ifdef CONFIG_MMC_ATMELMCI_DMA 1122 + if (host->dma.client.slave) 1123 + dma_async_client_unregister(&host->dma.client); 1124 + #endif 1125 + 1126 + free_irq(platform_get_irq(pdev, 0), host); 1127 + iounmap(host->regs); 1128 + 1129 + clk_put(host->mck); 1130 + kfree(host); 1131 + 1764 1132 return 0; 1765 1133 } 1766 1134
+21 -11
drivers/mmc/host/mmc_spi.c
··· 95 95 * reads which takes nowhere near that long. Older cards may be able to use 96 96 * shorter timeouts ... but why bother? 97 97 */ 98 - #define readblock_timeout ktime_set(0, 100 * 1000 * 1000) 99 - #define writeblock_timeout ktime_set(0, 250 * 1000 * 1000) 100 98 #define r1b_timeout ktime_set(3, 0) 101 99 102 100 ··· 218 220 return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0); 219 221 } 220 222 221 - static int mmc_spi_readtoken(struct mmc_spi_host *host) 223 + static int mmc_spi_readtoken(struct mmc_spi_host *host, ktime_t timeout) 222 224 { 223 - return mmc_spi_skip(host, readblock_timeout, 1, 0xff); 225 + return mmc_spi_skip(host, timeout, 1, 0xff); 224 226 } 225 227 226 228 ··· 603 605 * Return negative errno, else success. 604 606 */ 605 607 static int 606 - mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t) 608 + mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t, 609 + ktime_t timeout) 607 610 { 608 611 struct spi_device *spi = host->spi; 609 612 int status, i; ··· 672 673 if (scratch->status[i] != 0) 673 674 return 0; 674 675 } 675 - return mmc_spi_wait_unbusy(host, writeblock_timeout); 676 + return mmc_spi_wait_unbusy(host, timeout); 676 677 } 677 678 678 679 /* ··· 692 693 * STOP_TRANSMISSION command. 693 694 */ 694 695 static int 695 - mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t) 696 + mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t, 697 + ktime_t timeout) 696 698 { 697 699 struct spi_device *spi = host->spi; 698 700 int status; ··· 707 707 return status; 708 708 status = scratch->status[0]; 709 709 if (status == 0xff || status == 0) 710 - status = mmc_spi_readtoken(host); 710 + status = mmc_spi_readtoken(host, timeout); 711 711 712 712 if (status == SPI_TOKEN_SINGLE) { 713 713 if (host->dma_dev) { ··· 778 778 struct scatterlist *sg; 779 779 unsigned n_sg; 780 780 int multiple = (data->blocks > 1); 781 + u32 clock_rate; 782 + ktime_t timeout; 781 783 782 784 if (data->flags & MMC_DATA_READ) 783 785 direction = DMA_FROM_DEVICE; ··· 787 785 direction = DMA_TO_DEVICE; 788 786 mmc_spi_setup_data_message(host, multiple, direction); 789 787 t = &host->t; 788 + 789 + if (t->speed_hz) 790 + clock_rate = t->speed_hz; 791 + else 792 + clock_rate = spi->max_speed_hz; 793 + 794 + timeout = ktime_add_ns(ktime_set(0, 0), data->timeout_ns + 795 + data->timeout_clks * 1000000 / clock_rate); 790 796 791 797 /* Handle scatterlist segments one at a time, with synch for 792 798 * each 512-byte block ··· 842 832 t->len); 843 833 844 834 if (direction == DMA_TO_DEVICE) 845 - status = mmc_spi_writeblock(host, t); 835 + status = mmc_spi_writeblock(host, t, timeout); 846 836 else 847 - status = mmc_spi_readblock(host, t); 837 + status = mmc_spi_readblock(host, t, timeout); 848 838 if (status < 0) 849 839 break; 850 840 ··· 927 917 if (scratch->status[tmp] != 0) 928 918 return; 929 919 } 930 - tmp = mmc_spi_wait_unbusy(host, writeblock_timeout); 920 + tmp = mmc_spi_wait_unbusy(host, timeout); 931 921 if (tmp < 0 && !data->error) 932 922 data->error = tmp; 933 923 }
+2 -1
drivers/mmc/host/sdhci-pci.c
··· 144 144 SDHCI_QUIRK_32BIT_DMA_SIZE | 145 145 SDHCI_QUIRK_32BIT_ADMA_SIZE | 146 146 SDHCI_QUIRK_RESET_AFTER_REQUEST | 147 - SDHCI_QUIRK_BROKEN_SMALL_PIO; 147 + SDHCI_QUIRK_BROKEN_SMALL_PIO | 148 + SDHCI_QUIRK_FORCE_HIGHSPEED; 148 149 } 149 150 150 151 /*
+37 -9
drivers/mmc/host/sdhci.c
··· 177 177 { 178 178 unsigned long flags; 179 179 size_t blksize, len, chunk; 180 - u32 scratch; 180 + u32 uninitialized_var(scratch); 181 181 u8 *buf; 182 182 183 183 DBG("PIO reading\n"); ··· 1154 1154 1155 1155 spin_unlock_irqrestore(&host->lock, flags); 1156 1156 1157 - mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1157 + mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 1158 1158 } 1159 1159 1160 1160 static void sdhci_tasklet_finish(unsigned long param) ··· 1266 1266 SDHCI_INT_INDEX)) 1267 1267 host->cmd->error = -EILSEQ; 1268 1268 1269 - if (host->cmd->error) 1269 + if (host->cmd->error) { 1270 1270 tasklet_schedule(&host->finish_tasklet); 1271 - else if (intmask & SDHCI_INT_RESPONSE) 1271 + return; 1272 + } 1273 + 1274 + /* 1275 + * The host can send and interrupt when the busy state has 1276 + * ended, allowing us to wait without wasting CPU cycles. 1277 + * Unfortunately this is overloaded on the "data complete" 1278 + * interrupt, so we need to take some care when handling 1279 + * it. 1280 + * 1281 + * Note: The 1.0 specification is a bit ambiguous about this 1282 + * feature so there might be some problems with older 1283 + * controllers. 1284 + */ 1285 + if (host->cmd->flags & MMC_RSP_BUSY) { 1286 + if (host->cmd->data) 1287 + DBG("Cannot wait for busy signal when also " 1288 + "doing a data transfer"); 1289 + else 1290 + return; 1291 + } 1292 + 1293 + if (intmask & SDHCI_INT_RESPONSE) 1272 1294 sdhci_finish_command(host); 1273 1295 } 1274 1296 ··· 1300 1278 1301 1279 if (!host->data) { 1302 1280 /* 1303 - * A data end interrupt is sent together with the response 1304 - * for the stop command. 1281 + * The "data complete" interrupt is also used to 1282 + * indicate that a busy state has ended. See comment 1283 + * above in sdhci_cmd_irq(). 1305 1284 */ 1306 - if (intmask & SDHCI_INT_DATA_END) 1307 - return; 1285 + if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 1286 + if (intmask & SDHCI_INT_DATA_END) { 1287 + sdhci_finish_command(host); 1288 + return; 1289 + } 1290 + } 1308 1291 1309 1292 printk(KERN_ERR "%s: Got data interrupt 0x%08x even " 1310 1293 "though no data operation was in progress.\n", ··· 1631 1604 mmc->f_max = host->max_clk; 1632 1605 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 1633 1606 1634 - if (caps & SDHCI_CAN_DO_HISPD) 1607 + if ((caps & SDHCI_CAN_DO_HISPD) || 1608 + (host->quirks & SDHCI_QUIRK_FORCE_HIGHSPEED)) 1635 1609 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1636 1610 1637 1611 mmc->ocr_avail = 0;
+2
drivers/mmc/host/sdhci.h
··· 208 208 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 209 209 /* Controller has an issue with buffer bits for small transfers */ 210 210 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 211 + /* Controller supports high speed but doesn't have the caps bit set */ 212 + #define SDHCI_QUIRK_FORCE_HIGHSPEED (1<<14) 211 213 212 214 int irq; /* Device IRQ */ 213 215 void __iomem * ioaddr; /* Mapped address */
+1 -1
include/linux/mmc/host.h
··· 65 65 * -ENOSYS when not supported (equal to NULL callback) 66 66 * or a negative errno value when something bad happened 67 67 * 68 - * Return values for the get_ro callback should be: 68 + * Return values for the get_cd callback should be: 69 69 * 0 for a absent card 70 70 * 1 for a present card 71 71 * -ENOSYS when not supported (equal to NULL callback)