tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'icc-5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
Georgi writes:
interconnect changes for 5.13
These are the interconnect changes for the 5.13-rc1 merge window
with the highlights being drivers for two new platforms.
Driver changes:
- New driver for SM8350 platforms.
- New driver for SDM660 platforms.
Signed-off-by: Georgi Djakov <djakov@kernel.org>
* tag 'icc-5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
interconnect: qcom: sm8350: Add missing link between nodes
interconnect: qcom: sm8350: Use the correct ids
interconnect: qcom: sdm660: Fix kerneldoc warning
MAINTAINERS: icc: add interconnect tree
interconnect: qcom: Add SM8350 interconnect provider driver
dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings
interconnect: qcom: icc-rpm: record slave RPM id in error log
interconnect: qcom: Add SDM660 interconnect provider driver
dt-bindings: interconnect: Add bindings for Qualcomm SDM660 NoC
+2194
-2
+10
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+10
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
···
71
71
- qcom,sm8250-mmss-noc
72
72
- qcom,sm8250-npu-noc
73
73
- qcom,sm8250-system-noc
74
+
- qcom,sm8350-aggre1-noc
75
+
- qcom,sm8350-aggre2-noc
76
+
- qcom,sm8350-config-noc
77
+
- qcom,sm8350-dc-noc
78
+
- qcom,sm8350-gem-noc
79
+
- qcom,sm8350-lpass-ag-noc
80
+
- qcom,sm8350-mc-virt
81
+
- qcom,sm8350-mmss-noc
82
+
- qcom,sm8350-compute-noc
83
+
- qcom,sm8350-system-noc
74
84
75
85
'#interconnect-cells':
76
86
enum: [ 1, 2 ]
+147
Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml
+147
Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SDM660 Network-On-Chip interconnect
8
+
9
+
maintainers:
10
+
- AngeloGioacchino Del Regno <kholk11@gmail.com>
11
+
12
+
description: |
13
+
The Qualcomm SDM660 interconnect providers support adjusting the
14
+
bandwidth requirements between the various NoC fabrics.
15
+
16
+
properties:
17
+
reg:
18
+
maxItems: 1
19
+
20
+
compatible:
21
+
enum:
22
+
- qcom,sdm660-a2noc
23
+
- qcom,sdm660-bimc
24
+
- qcom,sdm660-cnoc
25
+
- qcom,sdm660-gnoc
26
+
- qcom,sdm660-mnoc
27
+
- qcom,sdm660-snoc
28
+
29
+
'#interconnect-cells':
30
+
const: 1
31
+
32
+
clocks:
33
+
minItems: 1
34
+
maxItems: 3
35
+
36
+
clock-names:
37
+
minItems: 1
38
+
maxItems: 3
39
+
40
+
required:
41
+
- compatible
42
+
- reg
43
+
- '#interconnect-cells'
44
+
- clock-names
45
+
- clocks
46
+
47
+
additionalProperties: false
48
+
49
+
allOf:
50
+
- if:
51
+
properties:
52
+
compatible:
53
+
contains:
54
+
enum:
55
+
- qcom,sdm660-mnoc
56
+
then:
57
+
properties:
58
+
clocks:
59
+
items:
60
+
- description: Bus Clock.
61
+
- description: Bus A Clock.
62
+
- description: CPU-NoC High-performance Bus Clock.
63
+
clock-names:
64
+
items:
65
+
- const: bus
66
+
- const: bus_a
67
+
- const: iface
68
+
69
+
- if:
70
+
properties:
71
+
compatible:
72
+
contains:
73
+
enum:
74
+
- qcom,sdm660-a2noc
75
+
- qcom,sdm660-bimc
76
+
- qcom,sdm660-cnoc
77
+
- qcom,sdm660-gnoc
78
+
- qcom,sdm660-snoc
79
+
then:
80
+
properties:
81
+
clocks:
82
+
items:
83
+
- description: Bus Clock.
84
+
- description: Bus A Clock.
85
+
clock-names:
86
+
items:
87
+
- const: bus
88
+
- const: bus_a
89
+
90
+
examples:
91
+
- |
92
+
#include <dt-bindings/clock/qcom,rpmcc.h>
93
+
#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
94
+
95
+
bimc: interconnect@1008000 {
96
+
compatible = "qcom,sdm660-bimc";
97
+
reg = <0x01008000 0x78000>;
98
+
#interconnect-cells = <1>;
99
+
clock-names = "bus", "bus_a";
100
+
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
101
+
<&rpmcc RPM_SMD_BIMC_A_CLK>;
102
+
};
103
+
104
+
cnoc: interconnect@1500000 {
105
+
compatible = "qcom,sdm660-cnoc";
106
+
reg = <0x01500000 0x10000>;
107
+
#interconnect-cells = <1>;
108
+
clock-names = "bus", "bus_a";
109
+
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
110
+
<&rpmcc RPM_SMD_CNOC_A_CLK>;
111
+
};
112
+
113
+
snoc: interconnect@1626000 {
114
+
compatible = "qcom,sdm660-snoc";
115
+
reg = <0x01626000 0x7090>;
116
+
#interconnect-cells = <1>;
117
+
clock-names = "bus", "bus_a";
118
+
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
119
+
<&rpmcc RPM_SMD_SNOC_A_CLK>;
120
+
};
121
+
122
+
a2noc: interconnect@1704000 {
123
+
compatible = "qcom,sdm660-a2noc";
124
+
reg = <0x01704000 0xc100>;
125
+
#interconnect-cells = <1>;
126
+
clock-names = "bus", "bus_a";
127
+
clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
128
+
<&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
129
+
};
130
+
131
+
mnoc: interconnect@1745000 {
132
+
compatible = "qcom,sdm660-mnoc";
133
+
reg = <0x01745000 0xa010>;
134
+
#interconnect-cells = <1>;
135
+
clock-names = "bus", "bus_a", "iface";
136
+
clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
137
+
<&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
138
+
<&mmcc AHB_CLK_SRC>;
139
+
};
140
+
141
+
gnoc: interconnect@17900000 {
142
+
compatible = "qcom,sdm660-gnoc";
143
+
reg = <0x17900000 0xe000>;
144
+
#interconnect-cells = <1>;
145
+
clock-names = "bus", "bus_a";
146
+
clocks = <&xo_board>, <&xo_board>;
147
+
};
+1
MAINTAINERS
+1
MAINTAINERS
···
9297
9297
M: Georgi Djakov <djakov@kernel.org>
9298
9298
L: linux-pm@vger.kernel.org
9299
9299
S: Maintained
9300
+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc.git
9300
9301
F: Documentation/devicetree/bindings/interconnect/
9301
9302
F: Documentation/driver-api/interconnect.rst
9302
9303
F: drivers/interconnect/
+18
drivers/interconnect/qcom/Kconfig
+18
drivers/interconnect/qcom/Kconfig
···
74
74
This is a driver for the Qualcomm Network-on-Chip on sc7180-based
75
75
platforms.
76
76
77
+
config INTERCONNECT_QCOM_SDM660
78
+
tristate "Qualcomm SDM660 interconnect driver"
79
+
depends on INTERCONNECT_QCOM
80
+
depends on QCOM_SMD_RPM
81
+
select INTERCONNECT_QCOM_SMD_RPM
82
+
help
83
+
This is a driver for the Qualcomm Network-on-Chip on sdm660-based
84
+
platforms.
85
+
77
86
config INTERCONNECT_QCOM_SDM845
78
87
tristate "Qualcomm SDM845 interconnect driver"
79
88
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
···
117
108
select INTERCONNECT_QCOM_BCM_VOTER
118
109
help
119
110
This is a driver for the Qualcomm Network-on-Chip on sm8250-based
111
+
platforms.
112
+
113
+
config INTERCONNECT_QCOM_SM8350
114
+
tristate "Qualcomm SM8350 interconnect driver"
115
+
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
116
+
select INTERCONNECT_QCOM_RPMH
117
+
select INTERCONNECT_QCOM_BCM_VOTER
118
+
help
119
+
This is a driver for the Qualcomm Network-on-Chip on SM8350-based
120
120
platforms.
121
121
122
122
config INTERCONNECT_QCOM_SMD_RPM
+4
drivers/interconnect/qcom/Makefile
+4
drivers/interconnect/qcom/Makefile
···
8
8
qnoc-qcs404-objs := qcs404.o
9
9
icc-rpmh-obj := icc-rpmh.o
10
10
qnoc-sc7180-objs := sc7180.o
11
+
qnoc-sdm660-objs := sdm660.o
11
12
qnoc-sdm845-objs := sdm845.o
12
13
qnoc-sdx55-objs := sdx55.o
13
14
qnoc-sm8150-objs := sm8150.o
14
15
qnoc-sm8250-objs := sm8250.o
16
+
qnoc-sm8350-objs := sm8350.o
15
17
icc-smd-rpm-objs := smd-rpm.o icc-rpm.o
16
18
17
19
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
···
24
22
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
25
23
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
26
24
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
25
+
obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o
27
26
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
28
27
obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
29
28
obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
30
29
obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
30
+
obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o
31
31
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
+2
-2
drivers/interconnect/qcom/icc-rpm.c
+2
-2
drivers/interconnect/qcom/icc-rpm.c
+923
drivers/interconnect/qcom/sdm660.c
+923
drivers/interconnect/qcom/sdm660.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Qualcomm SDM630/SDM636/SDM660 Network-on-Chip (NoC) QoS driver
4
+
* Copyright (C) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
5
+
*/
6
+
7
+
#include <dt-bindings/interconnect/qcom,sdm660.h>
8
+
#include <linux/clk.h>
9
+
#include <linux/device.h>
10
+
#include <linux/interconnect-provider.h>
11
+
#include <linux/io.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of_device.h>
14
+
#include <linux/of_platform.h>
15
+
#include <linux/platform_device.h>
16
+
#include <linux/regmap.h>
17
+
#include <linux/slab.h>
18
+
19
+
#include "smd-rpm.h"
20
+
21
+
#define RPM_BUS_MASTER_REQ 0x73616d62
22
+
#define RPM_BUS_SLAVE_REQ 0x766c7362
23
+
24
+
/* BIMC QoS */
25
+
#define M_BKE_REG_BASE(n) (0x300 + (0x4000 * n))
26
+
#define M_BKE_EN_ADDR(n) (M_BKE_REG_BASE(n))
27
+
#define M_BKE_HEALTH_CFG_ADDR(i, n) (M_BKE_REG_BASE(n) + 0x40 + (0x4 * i))
28
+
29
+
#define M_BKE_HEALTH_CFG_LIMITCMDS_MASK 0x80000000
30
+
#define M_BKE_HEALTH_CFG_AREQPRIO_MASK 0x300
31
+
#define M_BKE_HEALTH_CFG_PRIOLVL_MASK 0x3
32
+
#define M_BKE_HEALTH_CFG_AREQPRIO_SHIFT 0x8
33
+
#define M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT 0x1f
34
+
35
+
#define M_BKE_EN_EN_BMASK 0x1
36
+
37
+
/* Valid for both NoC and BIMC */
38
+
#define NOC_QOS_MODE_FIXED 0x0
39
+
#define NOC_QOS_MODE_LIMITER 0x1
40
+
#define NOC_QOS_MODE_BYPASS 0x2
41
+
42
+
/* NoC QoS */
43
+
#define NOC_PERM_MODE_FIXED 1
44
+
#define NOC_PERM_MODE_BYPASS (1 << NOC_QOS_MODE_BYPASS)
45
+
46
+
#define NOC_QOS_PRIORITYn_ADDR(n) (0x8 + (n * 0x1000))
47
+
#define NOC_QOS_PRIORITY_MASK 0xf
48
+
#define NOC_QOS_PRIORITY_P1_SHIFT 0x2
49
+
#define NOC_QOS_PRIORITY_P0_SHIFT 0x3
50
+
51
+
#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000))
52
+
#define NOC_QOS_MODEn_MASK 0x3
53
+
54
+
enum {
55
+
SDM660_MASTER_IPA = 1,
56
+
SDM660_MASTER_CNOC_A2NOC,
57
+
SDM660_MASTER_SDCC_1,
58
+
SDM660_MASTER_SDCC_2,
59
+
SDM660_MASTER_BLSP_1,
60
+
SDM660_MASTER_BLSP_2,
61
+
SDM660_MASTER_UFS,
62
+
SDM660_MASTER_USB_HS,
63
+
SDM660_MASTER_USB3,
64
+
SDM660_MASTER_CRYPTO_C0,
65
+
SDM660_MASTER_GNOC_BIMC,
66
+
SDM660_MASTER_OXILI,
67
+
SDM660_MASTER_MNOC_BIMC,
68
+
SDM660_MASTER_SNOC_BIMC,
69
+
SDM660_MASTER_PIMEM,
70
+
SDM660_MASTER_SNOC_CNOC,
71
+
SDM660_MASTER_QDSS_DAP,
72
+
SDM660_MASTER_APPS_PROC,
73
+
SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
74
+
SDM660_MASTER_CNOC_MNOC_CFG,
75
+
SDM660_MASTER_CPP,
76
+
SDM660_MASTER_JPEG,
77
+
SDM660_MASTER_MDP_P0,
78
+
SDM660_MASTER_MDP_P1,
79
+
SDM660_MASTER_VENUS,
80
+
SDM660_MASTER_VFE,
81
+
SDM660_MASTER_QDSS_ETR,
82
+
SDM660_MASTER_QDSS_BAM,
83
+
SDM660_MASTER_SNOC_CFG,
84
+
SDM660_MASTER_BIMC_SNOC,
85
+
SDM660_MASTER_A2NOC_SNOC,
86
+
SDM660_MASTER_GNOC_SNOC,
87
+
88
+
SDM660_SLAVE_A2NOC_SNOC,
89
+
SDM660_SLAVE_EBI,
90
+
SDM660_SLAVE_HMSS_L3,
91
+
SDM660_SLAVE_BIMC_SNOC,
92
+
SDM660_SLAVE_CNOC_A2NOC,
93
+
SDM660_SLAVE_MPM,
94
+
SDM660_SLAVE_PMIC_ARB,
95
+
SDM660_SLAVE_TLMM_NORTH,
96
+
SDM660_SLAVE_TCSR,
97
+
SDM660_SLAVE_PIMEM_CFG,
98
+
SDM660_SLAVE_IMEM_CFG,
99
+
SDM660_SLAVE_MESSAGE_RAM,
100
+
SDM660_SLAVE_GLM,
101
+
SDM660_SLAVE_BIMC_CFG,
102
+
SDM660_SLAVE_PRNG,
103
+
SDM660_SLAVE_SPDM,
104
+
SDM660_SLAVE_QDSS_CFG,
105
+
SDM660_SLAVE_CNOC_MNOC_CFG,
106
+
SDM660_SLAVE_SNOC_CFG,
107
+
SDM660_SLAVE_QM_CFG,
108
+
SDM660_SLAVE_CLK_CTL,
109
+
SDM660_SLAVE_MSS_CFG,
110
+
SDM660_SLAVE_TLMM_SOUTH,
111
+
SDM660_SLAVE_UFS_CFG,
112
+
SDM660_SLAVE_A2NOC_CFG,
113
+
SDM660_SLAVE_A2NOC_SMMU_CFG,
114
+
SDM660_SLAVE_GPUSS_CFG,
115
+
SDM660_SLAVE_AHB2PHY,
116
+
SDM660_SLAVE_BLSP_1,
117
+
SDM660_SLAVE_SDCC_1,
118
+
SDM660_SLAVE_SDCC_2,
119
+
SDM660_SLAVE_TLMM_CENTER,
120
+
SDM660_SLAVE_BLSP_2,
121
+
SDM660_SLAVE_PDM,
122
+
SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
123
+
SDM660_SLAVE_USB_HS,
124
+
SDM660_SLAVE_USB3_0,
125
+
SDM660_SLAVE_SRVC_CNOC,
126
+
SDM660_SLAVE_GNOC_BIMC,
127
+
SDM660_SLAVE_GNOC_SNOC,
128
+
SDM660_SLAVE_CAMERA_CFG,
129
+
SDM660_SLAVE_CAMERA_THROTTLE_CFG,
130
+
SDM660_SLAVE_MISC_CFG,
131
+
SDM660_SLAVE_VENUS_THROTTLE_CFG,
132
+
SDM660_SLAVE_VENUS_CFG,
133
+
SDM660_SLAVE_MMSS_CLK_XPU_CFG,
134
+
SDM660_SLAVE_MMSS_CLK_CFG,
135
+
SDM660_SLAVE_MNOC_MPU_CFG,
136
+
SDM660_SLAVE_DISPLAY_CFG,
137
+
SDM660_SLAVE_CSI_PHY_CFG,
138
+
SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
139
+
SDM660_SLAVE_SMMU_CFG,
140
+
SDM660_SLAVE_MNOC_BIMC,
141
+
SDM660_SLAVE_SRVC_MNOC,
142
+
SDM660_SLAVE_HMSS,
143
+
SDM660_SLAVE_LPASS,
144
+
SDM660_SLAVE_WLAN,
145
+
SDM660_SLAVE_CDSP,
146
+
SDM660_SLAVE_IPA,
147
+
SDM660_SLAVE_SNOC_BIMC,
148
+
SDM660_SLAVE_SNOC_CNOC,
149
+
SDM660_SLAVE_IMEM,
150
+
SDM660_SLAVE_PIMEM,
151
+
SDM660_SLAVE_QDSS_STM,
152
+
SDM660_SLAVE_SRVC_SNOC,
153
+
154
+
SDM660_A2NOC,
155
+
SDM660_BIMC,
156
+
SDM660_CNOC,
157
+
SDM660_GNOC,
158
+
SDM660_MNOC,
159
+
SDM660_SNOC,
160
+
};
161
+
162
+
#define to_qcom_provider(_provider) \
163
+
container_of(_provider, struct qcom_icc_provider, provider)
164
+
165
+
static const struct clk_bulk_data bus_clocks[] = {
166
+
{ .id = "bus" },
167
+
{ .id = "bus_a" },
168
+
};
169
+
170
+
static const struct clk_bulk_data bus_mm_clocks[] = {
171
+
{ .id = "bus" },
172
+
{ .id = "bus_a" },
173
+
{ .id = "iface" },
174
+
};
175
+
176
+
/**
177
+
* struct qcom_icc_provider - Qualcomm specific interconnect provider
178
+
* @provider: generic interconnect provider
179
+
* @bus_clks: the clk_bulk_data table of bus clocks
180
+
* @num_clks: the total number of clk_bulk_data entries
181
+
* @is_bimc_node: indicates whether to use bimc specific setting
182
+
* @regmap: regmap for QoS registers read/write access
183
+
* @mmio: NoC base iospace
184
+
*/
185
+
struct qcom_icc_provider {
186
+
struct icc_provider provider;
187
+
struct clk_bulk_data *bus_clks;
188
+
int num_clks;
189
+
bool is_bimc_node;
190
+
struct regmap *regmap;
191
+
void __iomem *mmio;
192
+
};
193
+
194
+
#define SDM660_MAX_LINKS 34
195
+
196
+
/**
197
+
* struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters
198
+
* @areq_prio: node requests priority
199
+
* @prio_level: priority level for bus communication
200
+
* @limit_commands: activate/deactivate limiter mode during runtime
201
+
* @ap_owned: indicates if the node is owned by the AP or by the RPM
202
+
* @qos_mode: default qos mode for this node
203
+
* @qos_port: qos port number for finding qos registers of this node
204
+
*/
205
+
struct qcom_icc_qos {
206
+
u32 areq_prio;
207
+
u32 prio_level;
208
+
bool limit_commands;
209
+
bool ap_owned;
210
+
int qos_mode;
211
+
int qos_port;
212
+
};
213
+
214
+
/**
215
+
* struct qcom_icc_node - Qualcomm specific interconnect nodes
216
+
* @name: the node name used in debugfs
217
+
* @id: a unique node identifier
218
+
* @links: an array of nodes where we can go next while traversing
219
+
* @num_links: the total number of @links
220
+
* @buswidth: width of the interconnect between a node and the bus (bytes)
221
+
* @mas_rpm_id: RPM id for devices that are bus masters
222
+
* @slv_rpm_id: RPM id for devices that are bus slaves
223
+
* @qos: NoC QoS setting parameters
224
+
* @rate: current bus clock rate in Hz
225
+
*/
226
+
struct qcom_icc_node {
227
+
unsigned char *name;
228
+
u16 id;
229
+
u16 links[SDM660_MAX_LINKS];
230
+
u16 num_links;
231
+
u16 buswidth;
232
+
int mas_rpm_id;
233
+
int slv_rpm_id;
234
+
struct qcom_icc_qos qos;
235
+
u64 rate;
236
+
};
237
+
238
+
struct qcom_icc_desc {
239
+
struct qcom_icc_node **nodes;
240
+
size_t num_nodes;
241
+
const struct regmap_config *regmap_cfg;
242
+
};
243
+
244
+
#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
245
+
_ap_owned, _qos_mode, _qos_prio, _qos_port, ...) \
246
+
static struct qcom_icc_node _name = { \
247
+
.name = #_name, \
248
+
.id = _id, \
249
+
.buswidth = _buswidth, \
250
+
.mas_rpm_id = _mas_rpm_id, \
251
+
.slv_rpm_id = _slv_rpm_id, \
252
+
.qos.ap_owned = _ap_owned, \
253
+
.qos.qos_mode = _qos_mode, \
254
+
.qos.areq_prio = _qos_prio, \
255
+
.qos.prio_level = _qos_prio, \
256
+
.qos.qos_port = _qos_port, \
257
+
.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
258
+
.links = { __VA_ARGS__ }, \
259
+
}
260
+
261
+
DEFINE_QNODE(mas_ipa, SDM660_MASTER_IPA, 8, 59, -1, true, NOC_QOS_MODE_FIXED, 1, 3, SDM660_SLAVE_A2NOC_SNOC);
262
+
DEFINE_QNODE(mas_cnoc_a2noc, SDM660_MASTER_CNOC_A2NOC, 8, 146, -1, true, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
263
+
DEFINE_QNODE(mas_sdcc_1, SDM660_MASTER_SDCC_1, 8, 33, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
264
+
DEFINE_QNODE(mas_sdcc_2, SDM660_MASTER_SDCC_2, 8, 35, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
265
+
DEFINE_QNODE(mas_blsp_1, SDM660_MASTER_BLSP_1, 4, 41, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
266
+
DEFINE_QNODE(mas_blsp_2, SDM660_MASTER_BLSP_2, 4, 39, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
267
+
DEFINE_QNODE(mas_ufs, SDM660_MASTER_UFS, 8, 68, -1, true, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_A2NOC_SNOC);
268
+
DEFINE_QNODE(mas_usb_hs, SDM660_MASTER_USB_HS, 8, 42, -1, true, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_A2NOC_SNOC);
269
+
DEFINE_QNODE(mas_usb3, SDM660_MASTER_USB3, 8, 32, -1, true, NOC_QOS_MODE_FIXED, 1, 2, SDM660_SLAVE_A2NOC_SNOC);
270
+
DEFINE_QNODE(mas_crypto, SDM660_MASTER_CRYPTO_C0, 8, 23, -1, true, NOC_QOS_MODE_FIXED, 1, 11, SDM660_SLAVE_A2NOC_SNOC);
271
+
DEFINE_QNODE(mas_gnoc_bimc, SDM660_MASTER_GNOC_BIMC, 4, 144, -1, true, NOC_QOS_MODE_FIXED, 0, 0, SDM660_SLAVE_EBI);
272
+
DEFINE_QNODE(mas_oxili, SDM660_MASTER_OXILI, 4, 6, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC);
273
+
DEFINE_QNODE(mas_mnoc_bimc, SDM660_MASTER_MNOC_BIMC, 4, 2, -1, true, NOC_QOS_MODE_BYPASS, 0, 2, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC);
274
+
DEFINE_QNODE(mas_snoc_bimc, SDM660_MASTER_SNOC_BIMC, 4, 3, -1, false, -1, 0, -1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI);
275
+
DEFINE_QNODE(mas_pimem, SDM660_MASTER_PIMEM, 4, 113, -1, true, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI);
276
+
DEFINE_QNODE(mas_snoc_cnoc, SDM660_MASTER_SNOC_CNOC, 8, 52, -1, true, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG);
277
+
DEFINE_QNODE(mas_qdss_dap, SDM660_MASTER_QDSS_DAP, 8, 49, -1, true, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_CNOC_A2NOC, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG);
278
+
DEFINE_QNODE(mas_apss_proc, SDM660_MASTER_APPS_PROC, 16, 0, -1, true, -1, 0, -1, SDM660_SLAVE_GNOC_SNOC, SDM660_SLAVE_GNOC_BIMC);
279
+
DEFINE_QNODE(mas_cnoc_mnoc_mmss_cfg, SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 8, 4, -1, true, -1, 0, -1, SDM660_SLAVE_VENUS_THROTTLE_CFG, SDM660_SLAVE_VENUS_CFG, SDM660_SLAVE_CAMERA_THROTTLE_CFG, SDM660_SLAVE_SMMU_CFG, SDM660_SLAVE_CAMERA_CFG, SDM660_SLAVE_CSI_PHY_CFG, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, SDM660_SLAVE_DISPLAY_CFG, SDM660_SLAVE_MMSS_CLK_CFG, SDM660_SLAVE_MNOC_MPU_CFG, SDM660_SLAVE_MISC_CFG, SDM660_SLAVE_MMSS_CLK_XPU_CFG);
280
+
DEFINE_QNODE(mas_cnoc_mnoc_cfg, SDM660_MASTER_CNOC_MNOC_CFG, 4, 5, -1, true, -1, 0, -1, SDM660_SLAVE_SRVC_MNOC);
281
+
DEFINE_QNODE(mas_cpp, SDM660_MASTER_CPP, 16, 115, -1, true, NOC_QOS_MODE_BYPASS, 0, 4, SDM660_SLAVE_MNOC_BIMC);
282
+
DEFINE_QNODE(mas_jpeg, SDM660_MASTER_JPEG, 16, 7, -1, true, NOC_QOS_MODE_BYPASS, 0, 6, SDM660_SLAVE_MNOC_BIMC);
283
+
DEFINE_QNODE(mas_mdp_p0, SDM660_MASTER_MDP_P0, 16, 8, -1, true, NOC_QOS_MODE_BYPASS, 0, 0, SDM660_SLAVE_MNOC_BIMC); /* vrail-comp???? */
284
+
DEFINE_QNODE(mas_mdp_p1, SDM660_MASTER_MDP_P1, 16, 61, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC); /* vrail-comp??? */
285
+
DEFINE_QNODE(mas_venus, SDM660_MASTER_VENUS, 16, 9, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC);
286
+
DEFINE_QNODE(mas_vfe, SDM660_MASTER_VFE, 16, 11, -1, true, NOC_QOS_MODE_BYPASS, 0, 5, SDM660_SLAVE_MNOC_BIMC);
287
+
DEFINE_QNODE(mas_qdss_etr, SDM660_MASTER_QDSS_ETR, 8, 31, -1, true, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC);
288
+
DEFINE_QNODE(mas_qdss_bam, SDM660_MASTER_QDSS_BAM, 4, 19, -1, true, NOC_QOS_MODE_FIXED, 1, 0, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC);
289
+
DEFINE_QNODE(mas_snoc_cfg, SDM660_MASTER_SNOC_CFG, 4, 20, -1, false, -1, 0, -1, SDM660_SLAVE_SRVC_SNOC);
290
+
DEFINE_QNODE(mas_bimc_snoc, SDM660_MASTER_BIMC_SNOC, 8, 21, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM);
291
+
DEFINE_QNODE(mas_gnoc_snoc, SDM660_MASTER_GNOC_SNOC, 8, 150, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM);
292
+
DEFINE_QNODE(mas_a2noc_snoc, SDM660_MASTER_A2NOC_SNOC, 16, 112, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_SNOC_BIMC, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM);
293
+
DEFINE_QNODE(slv_a2noc_snoc, SDM660_SLAVE_A2NOC_SNOC, 16, -1, 143, false, -1, 0, -1, SDM660_MASTER_A2NOC_SNOC);
294
+
DEFINE_QNODE(slv_ebi, SDM660_SLAVE_EBI, 4, -1, 0, false, -1, 0, -1, 0);
295
+
DEFINE_QNODE(slv_hmss_l3, SDM660_SLAVE_HMSS_L3, 4, -1, 160, false, -1, 0, -1, 0);
296
+
DEFINE_QNODE(slv_bimc_snoc, SDM660_SLAVE_BIMC_SNOC, 4, -1, 2, false, -1, 0, -1, SDM660_MASTER_BIMC_SNOC);
297
+
DEFINE_QNODE(slv_cnoc_a2noc, SDM660_SLAVE_CNOC_A2NOC, 8, -1, 208, true, -1, 0, -1, SDM660_MASTER_CNOC_A2NOC);
298
+
DEFINE_QNODE(slv_mpm, SDM660_SLAVE_MPM, 4, -1, 62, true, -1, 0, -1, 0);
299
+
DEFINE_QNODE(slv_pmic_arb, SDM660_SLAVE_PMIC_ARB, 4, -1, 59, true, -1, 0, -1, 0);
300
+
DEFINE_QNODE(slv_tlmm_north, SDM660_SLAVE_TLMM_NORTH, 8, -1, 214, true, -1, 0, -1, 0);
301
+
DEFINE_QNODE(slv_tcsr, SDM660_SLAVE_TCSR, 4, -1, 50, true, -1, 0, -1, 0);
302
+
DEFINE_QNODE(slv_pimem_cfg, SDM660_SLAVE_PIMEM_CFG, 4, -1, 167, true, -1, 0, -1, 0);
303
+
DEFINE_QNODE(slv_imem_cfg, SDM660_SLAVE_IMEM_CFG, 4, -1, 54, true, -1, 0, -1, 0);
304
+
DEFINE_QNODE(slv_message_ram, SDM660_SLAVE_MESSAGE_RAM, 4, -1, 55, true, -1, 0, -1, 0);
305
+
DEFINE_QNODE(slv_glm, SDM660_SLAVE_GLM, 4, -1, 209, true, -1, 0, -1, 0);
306
+
DEFINE_QNODE(slv_bimc_cfg, SDM660_SLAVE_BIMC_CFG, 4, -1, 56, true, -1, 0, -1, 0);
307
+
DEFINE_QNODE(slv_prng, SDM660_SLAVE_PRNG, 4, -1, 44, true, -1, 0, -1, 0);
308
+
DEFINE_QNODE(slv_spdm, SDM660_SLAVE_SPDM, 4, -1, 60, true, -1, 0, -1, 0);
309
+
DEFINE_QNODE(slv_qdss_cfg, SDM660_SLAVE_QDSS_CFG, 4, -1, 63, true, -1, 0, -1, 0);
310
+
DEFINE_QNODE(slv_cnoc_mnoc_cfg, SDM660_SLAVE_BLSP_1, 4, -1, 66, true, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_CFG);
311
+
DEFINE_QNODE(slv_snoc_cfg, SDM660_SLAVE_SNOC_CFG, 4, -1, 70, true, -1, 0, -1, 0);
312
+
DEFINE_QNODE(slv_qm_cfg, SDM660_SLAVE_QM_CFG, 4, -1, 212, true, -1, 0, -1, 0);
313
+
DEFINE_QNODE(slv_clk_ctl, SDM660_SLAVE_CLK_CTL, 4, -1, 47, true, -1, 0, -1, 0);
314
+
DEFINE_QNODE(slv_mss_cfg, SDM660_SLAVE_MSS_CFG, 4, -1, 48, true, -1, 0, -1, 0);
315
+
DEFINE_QNODE(slv_tlmm_south, SDM660_SLAVE_TLMM_SOUTH, 4, -1, 217, true, -1, 0, -1, 0);
316
+
DEFINE_QNODE(slv_ufs_cfg, SDM660_SLAVE_UFS_CFG, 4, -1, 92, true, -1, 0, -1, 0);
317
+
DEFINE_QNODE(slv_a2noc_cfg, SDM660_SLAVE_A2NOC_CFG, 4, -1, 150, true, -1, 0, -1, 0);
318
+
DEFINE_QNODE(slv_a2noc_smmu_cfg, SDM660_SLAVE_A2NOC_SMMU_CFG, 8, -1, 152, true, -1, 0, -1, 0);
319
+
DEFINE_QNODE(slv_gpuss_cfg, SDM660_SLAVE_GPUSS_CFG, 8, -1, 11, true, -1, 0, -1, 0);
320
+
DEFINE_QNODE(slv_ahb2phy, SDM660_SLAVE_AHB2PHY, 4, -1, 163, true, -1, 0, -1, 0);
321
+
DEFINE_QNODE(slv_blsp_1, SDM660_SLAVE_BLSP_1, 4, -1, 39, true, -1, 0, -1, 0);
322
+
DEFINE_QNODE(slv_sdcc_1, SDM660_SLAVE_SDCC_1, 4, -1, 31, true, -1, 0, -1, 0);
323
+
DEFINE_QNODE(slv_sdcc_2, SDM660_SLAVE_SDCC_2, 4, -1, 33, true, -1, 0, -1, 0);
324
+
DEFINE_QNODE(slv_tlmm_center, SDM660_SLAVE_TLMM_CENTER, 4, -1, 218, true, -1, 0, -1, 0);
325
+
DEFINE_QNODE(slv_blsp_2, SDM660_SLAVE_BLSP_2, 4, -1, 37, true, -1, 0, -1, 0);
326
+
DEFINE_QNODE(slv_pdm, SDM660_SLAVE_PDM, 4, -1, 41, true, -1, 0, -1, 0);
327
+
DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 8, -1, 58, true, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_MMSS_CFG);
328
+
DEFINE_QNODE(slv_usb_hs, SDM660_SLAVE_USB_HS, 4, -1, 40, true, -1, 0, -1, 0);
329
+
DEFINE_QNODE(slv_usb3_0, SDM660_SLAVE_USB3_0, 4, -1, 22, true, -1, 0, -1, 0);
330
+
DEFINE_QNODE(slv_srvc_cnoc, SDM660_SLAVE_SRVC_CNOC, 4, -1, 76, true, -1, 0, -1, 0);
331
+
DEFINE_QNODE(slv_gnoc_bimc, SDM660_SLAVE_GNOC_BIMC, 16, -1, 210, true, -1, 0, -1, SDM660_MASTER_GNOC_BIMC);
332
+
DEFINE_QNODE(slv_gnoc_snoc, SDM660_SLAVE_GNOC_SNOC, 8, -1, 211, true, -1, 0, -1, SDM660_MASTER_GNOC_SNOC);
333
+
DEFINE_QNODE(slv_camera_cfg, SDM660_SLAVE_CAMERA_CFG, 4, -1, 3, true, -1, 0, -1, 0);
334
+
DEFINE_QNODE(slv_camera_throttle_cfg, SDM660_SLAVE_CAMERA_THROTTLE_CFG, 4, -1, 154, true, -1, 0, -1, 0);
335
+
DEFINE_QNODE(slv_misc_cfg, SDM660_SLAVE_MISC_CFG, 4, -1, 8, true, -1, 0, -1, 0);
336
+
DEFINE_QNODE(slv_venus_throttle_cfg, SDM660_SLAVE_VENUS_THROTTLE_CFG, 4, -1, 178, true, -1, 0, -1, 0);
337
+
DEFINE_QNODE(slv_venus_cfg, SDM660_SLAVE_VENUS_CFG, 4, -1, 10, true, -1, 0, -1, 0);
338
+
DEFINE_QNODE(slv_mmss_clk_xpu_cfg, SDM660_SLAVE_MMSS_CLK_XPU_CFG, 4, -1, 13, true, -1, 0, -1, 0);
339
+
DEFINE_QNODE(slv_mmss_clk_cfg, SDM660_SLAVE_MMSS_CLK_CFG, 4, -1, 12, true, -1, 0, -1, 0);
340
+
DEFINE_QNODE(slv_mnoc_mpu_cfg, SDM660_SLAVE_MNOC_MPU_CFG, 4, -1, 14, true, -1, 0, -1, 0);
341
+
DEFINE_QNODE(slv_display_cfg, SDM660_SLAVE_DISPLAY_CFG, 4, -1, 4, true, -1, 0, -1, 0);
342
+
DEFINE_QNODE(slv_csi_phy_cfg, SDM660_SLAVE_CSI_PHY_CFG, 4, -1, 224, true, -1, 0, -1, 0);
343
+
DEFINE_QNODE(slv_display_throttle_cfg, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 4, -1, 156, true, -1, 0, -1, 0);
344
+
DEFINE_QNODE(slv_smmu_cfg, SDM660_SLAVE_SMMU_CFG, 8, -1, 205, true, -1, 0, -1, 0);
345
+
DEFINE_QNODE(slv_mnoc_bimc, SDM660_SLAVE_MNOC_BIMC, 16, -1, 16, true, -1, 0, -1, SDM660_MASTER_MNOC_BIMC);
346
+
DEFINE_QNODE(slv_srvc_mnoc, SDM660_SLAVE_SRVC_MNOC, 8, -1, 17, true, -1, 0, -1, 0);
347
+
DEFINE_QNODE(slv_hmss, SDM660_SLAVE_HMSS, 8, -1, 20, true, -1, 0, -1, 0);
348
+
DEFINE_QNODE(slv_lpass, SDM660_SLAVE_LPASS, 4, -1, 21, true, -1, 0, -1, 0);
349
+
DEFINE_QNODE(slv_wlan, SDM660_SLAVE_WLAN, 4, -1, 206, false, -1, 0, -1, 0);
350
+
DEFINE_QNODE(slv_cdsp, SDM660_SLAVE_CDSP, 4, -1, 221, true, -1, 0, -1, 0);
351
+
DEFINE_QNODE(slv_ipa, SDM660_SLAVE_IPA, 4, -1, 183, true, -1, 0, -1, 0);
352
+
DEFINE_QNODE(slv_snoc_bimc, SDM660_SLAVE_SNOC_BIMC, 16, -1, 24, false, -1, 0, -1, SDM660_MASTER_SNOC_BIMC);
353
+
DEFINE_QNODE(slv_snoc_cnoc, SDM660_SLAVE_SNOC_CNOC, 8, -1, 25, false, -1, 0, -1, SDM660_MASTER_SNOC_CNOC);
354
+
DEFINE_QNODE(slv_imem, SDM660_SLAVE_IMEM, 8, -1, 26, false, -1, 0, -1, 0);
355
+
DEFINE_QNODE(slv_pimem, SDM660_SLAVE_PIMEM, 8, -1, 166, false, -1, 0, -1, 0);
356
+
DEFINE_QNODE(slv_qdss_stm, SDM660_SLAVE_QDSS_STM, 4, -1, 30, false, -1, 0, -1, 0);
357
+
DEFINE_QNODE(slv_srvc_snoc, SDM660_SLAVE_SRVC_SNOC, 16, -1, 29, false, -1, 0, -1, 0);
358
+
359
+
static struct qcom_icc_node *sdm660_a2noc_nodes[] = {
360
+
[MASTER_IPA] = &mas_ipa,
361
+
[MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc,
362
+
[MASTER_SDCC_1] = &mas_sdcc_1,
363
+
[MASTER_SDCC_2] = &mas_sdcc_2,
364
+
[MASTER_BLSP_1] = &mas_blsp_1,
365
+
[MASTER_BLSP_2] = &mas_blsp_2,
366
+
[MASTER_UFS] = &mas_ufs,
367
+
[MASTER_USB_HS] = &mas_usb_hs,
368
+
[MASTER_USB3] = &mas_usb3,
369
+
[MASTER_CRYPTO_C0] = &mas_crypto,
370
+
[SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
371
+
};
372
+
373
+
static const struct regmap_config sdm660_a2noc_regmap_config = {
374
+
.reg_bits = 32,
375
+
.reg_stride = 4,
376
+
.val_bits = 32,
377
+
.max_register = 0x20000,
378
+
.fast_io = true,
379
+
};
380
+
381
+
static struct qcom_icc_desc sdm660_a2noc = {
382
+
.nodes = sdm660_a2noc_nodes,
383
+
.num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
384
+
.regmap_cfg = &sdm660_a2noc_regmap_config,
385
+
};
386
+
387
+
static struct qcom_icc_node *sdm660_bimc_nodes[] = {
388
+
[MASTER_GNOC_BIMC] = &mas_gnoc_bimc,
389
+
[MASTER_OXILI] = &mas_oxili,
390
+
[MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
391
+
[MASTER_SNOC_BIMC] = &mas_snoc_bimc,
392
+
[MASTER_PIMEM] = &mas_pimem,
393
+
[SLAVE_EBI] = &slv_ebi,
394
+
[SLAVE_HMSS_L3] = &slv_hmss_l3,
395
+
[SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
396
+
};
397
+
398
+
static const struct regmap_config sdm660_bimc_regmap_config = {
399
+
.reg_bits = 32,
400
+
.reg_stride = 4,
401
+
.val_bits = 32,
402
+
.max_register = 0x80000,
403
+
.fast_io = true,
404
+
};
405
+
406
+
static struct qcom_icc_desc sdm660_bimc = {
407
+
.nodes = sdm660_bimc_nodes,
408
+
.num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
409
+
.regmap_cfg = &sdm660_bimc_regmap_config,
410
+
};
411
+
412
+
static struct qcom_icc_node *sdm660_cnoc_nodes[] = {
413
+
[MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
414
+
[MASTER_QDSS_DAP] = &mas_qdss_dap,
415
+
[SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc,
416
+
[SLAVE_MPM] = &slv_mpm,
417
+
[SLAVE_PMIC_ARB] = &slv_pmic_arb,
418
+
[SLAVE_TLMM_NORTH] = &slv_tlmm_north,
419
+
[SLAVE_TCSR] = &slv_tcsr,
420
+
[SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
421
+
[SLAVE_IMEM_CFG] = &slv_imem_cfg,
422
+
[SLAVE_MESSAGE_RAM] = &slv_message_ram,
423
+
[SLAVE_GLM] = &slv_glm,
424
+
[SLAVE_BIMC_CFG] = &slv_bimc_cfg,
425
+
[SLAVE_PRNG] = &slv_prng,
426
+
[SLAVE_SPDM] = &slv_spdm,
427
+
[SLAVE_QDSS_CFG] = &slv_qdss_cfg,
428
+
[SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
429
+
[SLAVE_SNOC_CFG] = &slv_snoc_cfg,
430
+
[SLAVE_QM_CFG] = &slv_qm_cfg,
431
+
[SLAVE_CLK_CTL] = &slv_clk_ctl,
432
+
[SLAVE_MSS_CFG] = &slv_mss_cfg,
433
+
[SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
434
+
[SLAVE_UFS_CFG] = &slv_ufs_cfg,
435
+
[SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
436
+
[SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
437
+
[SLAVE_GPUSS_CFG] = &slv_gpuss_cfg,
438
+
[SLAVE_AHB2PHY] = &slv_ahb2phy,
439
+
[SLAVE_BLSP_1] = &slv_blsp_1,
440
+
[SLAVE_SDCC_1] = &slv_sdcc_1,
441
+
[SLAVE_SDCC_2] = &slv_sdcc_2,
442
+
[SLAVE_TLMM_CENTER] = &slv_tlmm_center,
443
+
[SLAVE_BLSP_2] = &slv_blsp_2,
444
+
[SLAVE_PDM] = &slv_pdm,
445
+
[SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
446
+
[SLAVE_USB_HS] = &slv_usb_hs,
447
+
[SLAVE_USB3_0] = &slv_usb3_0,
448
+
[SLAVE_SRVC_CNOC] = &slv_srvc_cnoc,
449
+
};
450
+
451
+
static const struct regmap_config sdm660_cnoc_regmap_config = {
452
+
.reg_bits = 32,
453
+
.reg_stride = 4,
454
+
.val_bits = 32,
455
+
.max_register = 0x10000,
456
+
.fast_io = true,
457
+
};
458
+
459
+
static struct qcom_icc_desc sdm660_cnoc = {
460
+
.nodes = sdm660_cnoc_nodes,
461
+
.num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
462
+
.regmap_cfg = &sdm660_cnoc_regmap_config,
463
+
};
464
+
465
+
static struct qcom_icc_node *sdm660_gnoc_nodes[] = {
466
+
[MASTER_APSS_PROC] = &mas_apss_proc,
467
+
[SLAVE_GNOC_BIMC] = &slv_gnoc_bimc,
468
+
[SLAVE_GNOC_SNOC] = &slv_gnoc_snoc,
469
+
};
470
+
471
+
static const struct regmap_config sdm660_gnoc_regmap_config = {
472
+
.reg_bits = 32,
473
+
.reg_stride = 4,
474
+
.val_bits = 32,
475
+
.max_register = 0xe000,
476
+
.fast_io = true,
477
+
};
478
+
479
+
static struct qcom_icc_desc sdm660_gnoc = {
480
+
.nodes = sdm660_gnoc_nodes,
481
+
.num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
482
+
.regmap_cfg = &sdm660_gnoc_regmap_config,
483
+
};
484
+
485
+
static struct qcom_icc_node *sdm660_mnoc_nodes[] = {
486
+
[MASTER_CPP] = &mas_cpp,
487
+
[MASTER_JPEG] = &mas_jpeg,
488
+
[MASTER_MDP_P0] = &mas_mdp_p0,
489
+
[MASTER_MDP_P1] = &mas_mdp_p1,
490
+
[MASTER_VENUS] = &mas_venus,
491
+
[MASTER_VFE] = &mas_vfe,
492
+
[MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
493
+
[MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
494
+
[SLAVE_CAMERA_CFG] = &slv_camera_cfg,
495
+
[SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
496
+
[SLAVE_MISC_CFG] = &slv_misc_cfg,
497
+
[SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
498
+
[SLAVE_VENUS_CFG] = &slv_venus_cfg,
499
+
[SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
500
+
[SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
501
+
[SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
502
+
[SLAVE_DISPLAY_CFG] = &slv_display_cfg,
503
+
[SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg,
504
+
[SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
505
+
[SLAVE_SMMU_CFG] = &slv_smmu_cfg,
506
+
[SLAVE_SRVC_MNOC] = &slv_srvc_mnoc,
507
+
[SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
508
+
};
509
+
510
+
static const struct regmap_config sdm660_mnoc_regmap_config = {
511
+
.reg_bits = 32,
512
+
.reg_stride = 4,
513
+
.val_bits = 32,
514
+
.max_register = 0x10000,
515
+
.fast_io = true,
516
+
};
517
+
518
+
static struct qcom_icc_desc sdm660_mnoc = {
519
+
.nodes = sdm660_mnoc_nodes,
520
+
.num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
521
+
.regmap_cfg = &sdm660_mnoc_regmap_config,
522
+
};
523
+
524
+
static struct qcom_icc_node *sdm660_snoc_nodes[] = {
525
+
[MASTER_QDSS_ETR] = &mas_qdss_etr,
526
+
[MASTER_QDSS_BAM] = &mas_qdss_bam,
527
+
[MASTER_SNOC_CFG] = &mas_snoc_cfg,
528
+
[MASTER_BIMC_SNOC] = &mas_bimc_snoc,
529
+
[MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
530
+
[MASTER_GNOC_SNOC] = &mas_gnoc_snoc,
531
+
[SLAVE_HMSS] = &slv_hmss,
532
+
[SLAVE_LPASS] = &slv_lpass,
533
+
[SLAVE_WLAN] = &slv_wlan,
534
+
[SLAVE_CDSP] = &slv_cdsp,
535
+
[SLAVE_IPA] = &slv_ipa,
536
+
[SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
537
+
[SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
538
+
[SLAVE_IMEM] = &slv_imem,
539
+
[SLAVE_PIMEM] = &slv_pimem,
540
+
[SLAVE_QDSS_STM] = &slv_qdss_stm,
541
+
[SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
542
+
};
543
+
544
+
static const struct regmap_config sdm660_snoc_regmap_config = {
545
+
.reg_bits = 32,
546
+
.reg_stride = 4,
547
+
.val_bits = 32,
548
+
.max_register = 0x20000,
549
+
.fast_io = true,
550
+
};
551
+
552
+
static struct qcom_icc_desc sdm660_snoc = {
553
+
.nodes = sdm660_snoc_nodes,
554
+
.num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
555
+
.regmap_cfg = &sdm660_snoc_regmap_config,
556
+
};
557
+
558
+
static int qcom_icc_bimc_set_qos_health(struct regmap *rmap,
559
+
struct qcom_icc_qos *qos,
560
+
int regnum)
561
+
{
562
+
u32 val;
563
+
u32 mask;
564
+
565
+
val = qos->prio_level;
566
+
mask = M_BKE_HEALTH_CFG_PRIOLVL_MASK;
567
+
568
+
val |= qos->areq_prio << M_BKE_HEALTH_CFG_AREQPRIO_SHIFT;
569
+
mask |= M_BKE_HEALTH_CFG_AREQPRIO_MASK;
570
+
571
+
/* LIMITCMDS is not present on M_BKE_HEALTH_3 */
572
+
if (regnum != 3) {
573
+
val |= qos->limit_commands << M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT;
574
+
mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK;
575
+
}
576
+
577
+
return regmap_update_bits(rmap,
578
+
M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port),
579
+
mask, val);
580
+
}
581
+
582
+
static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw,
583
+
bool bypass_mode)
584
+
{
585
+
struct qcom_icc_provider *qp;
586
+
struct qcom_icc_node *qn;
587
+
struct icc_provider *provider;
588
+
u32 mode = NOC_QOS_MODE_BYPASS;
589
+
u32 val = 0;
590
+
int i, rc = 0;
591
+
592
+
qn = src->data;
593
+
provider = src->provider;
594
+
qp = to_qcom_provider(provider);
595
+
596
+
if (qn->qos.qos_mode != -1)
597
+
mode = qn->qos.qos_mode;
598
+
599
+
/* QoS Priority: The QoS Health parameters are getting considered
600
+
* only if we are NOT in Bypass Mode.
601
+
*/
602
+
if (mode != NOC_QOS_MODE_BYPASS) {
603
+
for (i = 3; i >= 0; i--) {
604
+
rc = qcom_icc_bimc_set_qos_health(qp->regmap,
605
+
&qn->qos, i);
606
+
if (rc)
607
+
return rc;
608
+
}
609
+
610
+
/* Set BKE_EN to 1 when Fixed, Regulator or Limiter Mode */
611
+
val = 1;
612
+
}
613
+
614
+
return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port),
615
+
M_BKE_EN_EN_BMASK, val);
616
+
}
617
+
618
+
static int qcom_icc_noc_set_qos_priority(struct regmap *rmap,
619
+
struct qcom_icc_qos *qos)
620
+
{
621
+
u32 val;
622
+
int rc;
623
+
624
+
/* Must be updated one at a time, P1 first, P0 last */
625
+
val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT;
626
+
rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
627
+
NOC_QOS_PRIORITY_MASK, val);
628
+
if (rc)
629
+
return rc;
630
+
631
+
val = qos->prio_level << NOC_QOS_PRIORITY_P0_SHIFT;
632
+
return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
633
+
NOC_QOS_PRIORITY_MASK, val);
634
+
}
635
+
636
+
static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw)
637
+
{
638
+
struct qcom_icc_provider *qp;
639
+
struct qcom_icc_node *qn;
640
+
struct icc_provider *provider;
641
+
u32 mode = NOC_QOS_MODE_BYPASS;
642
+
int rc = 0;
643
+
644
+
qn = src->data;
645
+
provider = src->provider;
646
+
qp = to_qcom_provider(provider);
647
+
648
+
if (qn->qos.qos_port < 0) {
649
+
dev_dbg(src->provider->dev,
650
+
"NoC QoS: Skipping %s: vote aggregated on parent.\n",
651
+
qn->name);
652
+
return 0;
653
+
}
654
+
655
+
if (qn->qos.qos_mode != -1)
656
+
mode = qn->qos.qos_mode;
657
+
658
+
if (mode == NOC_QOS_MODE_FIXED) {
659
+
dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n",
660
+
qn->name);
661
+
rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos);
662
+
if (rc)
663
+
return rc;
664
+
} else if (mode == NOC_QOS_MODE_BYPASS) {
665
+
dev_dbg(src->provider->dev, "NoC QoS: %s: Set Bypass mode\n",
666
+
qn->name);
667
+
}
668
+
669
+
return regmap_update_bits(qp->regmap,
670
+
NOC_QOS_MODEn_ADDR(qn->qos.qos_port),
671
+
NOC_QOS_MODEn_MASK, mode);
672
+
}
673
+
674
+
static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw)
675
+
{
676
+
struct qcom_icc_provider *qp = to_qcom_provider(node->provider);
677
+
struct qcom_icc_node *qn = node->data;
678
+
679
+
dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name);
680
+
681
+
if (qp->is_bimc_node)
682
+
return qcom_icc_set_bimc_qos(node, sum_bw,
683
+
(qn->qos.qos_mode == NOC_QOS_MODE_BYPASS));
684
+
685
+
return qcom_icc_set_noc_qos(node, sum_bw);
686
+
}
687
+
688
+
static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw)
689
+
{
690
+
int ret = 0;
691
+
692
+
if (mas_rpm_id != -1) {
693
+
ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
694
+
RPM_BUS_MASTER_REQ,
695
+
mas_rpm_id,
696
+
sum_bw);
697
+
if (ret) {
698
+
pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
699
+
mas_rpm_id, ret);
700
+
return ret;
701
+
}
702
+
}
703
+
704
+
if (slv_rpm_id != -1) {
705
+
ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
706
+
RPM_BUS_SLAVE_REQ,
707
+
slv_rpm_id,
708
+
sum_bw);
709
+
if (ret) {
710
+
pr_err("qcom_icc_rpm_smd_send slv %d error %d\n",
711
+
slv_rpm_id, ret);
712
+
return ret;
713
+
}
714
+
}
715
+
716
+
return ret;
717
+
}
718
+
719
+
static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
720
+
{
721
+
struct qcom_icc_provider *qp;
722
+
struct qcom_icc_node *qn;
723
+
struct icc_provider *provider;
724
+
struct icc_node *n;
725
+
u64 sum_bw;
726
+
u64 max_peak_bw;
727
+
u64 rate;
728
+
u32 agg_avg = 0;
729
+
u32 agg_peak = 0;
730
+
int ret, i;
731
+
732
+
qn = src->data;
733
+
provider = src->provider;
734
+
qp = to_qcom_provider(provider);
735
+
736
+
list_for_each_entry(n, &provider->nodes, node_list)
737
+
provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
738
+
&agg_avg, &agg_peak);
739
+
740
+
sum_bw = icc_units_to_bps(agg_avg);
741
+
max_peak_bw = icc_units_to_bps(agg_peak);
742
+
743
+
if (!qn->qos.ap_owned) {
744
+
/* send bandwidth request message to the RPM processor */
745
+
ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw);
746
+
if (ret)
747
+
return ret;
748
+
} else if (qn->qos.qos_mode != -1) {
749
+
/* set bandwidth directly from the AP */
750
+
ret = qcom_icc_qos_set(src, sum_bw);
751
+
if (ret)
752
+
return ret;
753
+
}
754
+
755
+
rate = max(sum_bw, max_peak_bw);
756
+
757
+
do_div(rate, qn->buswidth);
758
+
759
+
if (qn->rate == rate)
760
+
return 0;
761
+
762
+
for (i = 0; i < qp->num_clks; i++) {
763
+
ret = clk_set_rate(qp->bus_clks[i].clk, rate);
764
+
if (ret) {
765
+
pr_err("%s clk_set_rate error: %d\n",
766
+
qp->bus_clks[i].id, ret);
767
+
return ret;
768
+
}
769
+
}
770
+
771
+
qn->rate = rate;
772
+
773
+
return 0;
774
+
}
775
+
776
+
static int qnoc_probe(struct platform_device *pdev)
777
+
{
778
+
struct device *dev = &pdev->dev;
779
+
const struct qcom_icc_desc *desc;
780
+
struct icc_onecell_data *data;
781
+
struct icc_provider *provider;
782
+
struct qcom_icc_node **qnodes;
783
+
struct qcom_icc_provider *qp;
784
+
struct icc_node *node;
785
+
struct resource *res;
786
+
size_t num_nodes, i;
787
+
int ret;
788
+
789
+
/* wait for the RPM proxy */
790
+
if (!qcom_icc_rpm_smd_available())
791
+
return -EPROBE_DEFER;
792
+
793
+
desc = of_device_get_match_data(dev);
794
+
if (!desc)
795
+
return -EINVAL;
796
+
797
+
qnodes = desc->nodes;
798
+
num_nodes = desc->num_nodes;
799
+
800
+
qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
801
+
if (!qp)
802
+
return -ENOMEM;
803
+
804
+
data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
805
+
GFP_KERNEL);
806
+
if (!data)
807
+
return -ENOMEM;
808
+
809
+
if (of_device_is_compatible(dev->of_node, "qcom,sdm660-mnoc")) {
810
+
qp->bus_clks = devm_kmemdup(dev, bus_mm_clocks,
811
+
sizeof(bus_mm_clocks), GFP_KERNEL);
812
+
qp->num_clks = ARRAY_SIZE(bus_mm_clocks);
813
+
} else {
814
+
if (of_device_is_compatible(dev->of_node, "qcom,sdm660-bimc"))
815
+
qp->is_bimc_node = true;
816
+
817
+
qp->bus_clks = devm_kmemdup(dev, bus_clocks, sizeof(bus_clocks),
818
+
GFP_KERNEL);
819
+
qp->num_clks = ARRAY_SIZE(bus_clocks);
820
+
}
821
+
if (!qp->bus_clks)
822
+
return -ENOMEM;
823
+
824
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
825
+
if (!res)
826
+
return -ENODEV;
827
+
828
+
qp->mmio = devm_ioremap_resource(dev, res);
829
+
if (IS_ERR(qp->mmio)) {
830
+
dev_err(dev, "Cannot ioremap interconnect bus resource\n");
831
+
return PTR_ERR(qp->mmio);
832
+
}
833
+
834
+
qp->regmap = devm_regmap_init_mmio(dev, qp->mmio, desc->regmap_cfg);
835
+
if (IS_ERR(qp->regmap)) {
836
+
dev_err(dev, "Cannot regmap interconnect bus resource\n");
837
+
return PTR_ERR(qp->regmap);
838
+
}
839
+
840
+
ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
841
+
if (ret)
842
+
return ret;
843
+
844
+
ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
845
+
if (ret)
846
+
return ret;
847
+
848
+
provider = &qp->provider;
849
+
INIT_LIST_HEAD(&provider->nodes);
850
+
provider->dev = dev;
851
+
provider->set = qcom_icc_set;
852
+
provider->aggregate = icc_std_aggregate;
853
+
provider->xlate = of_icc_xlate_onecell;
854
+
provider->data = data;
855
+
856
+
ret = icc_provider_add(provider);
857
+
if (ret) {
858
+
dev_err(dev, "error adding interconnect provider: %d\n", ret);
859
+
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
860
+
return ret;
861
+
}
862
+
863
+
for (i = 0; i < num_nodes; i++) {
864
+
size_t j;
865
+
866
+
node = icc_node_create(qnodes[i]->id);
867
+
if (IS_ERR(node)) {
868
+
ret = PTR_ERR(node);
869
+
goto err;
870
+
}
871
+
872
+
node->name = qnodes[i]->name;
873
+
node->data = qnodes[i];
874
+
icc_node_add(node, provider);
875
+
876
+
for (j = 0; j < qnodes[i]->num_links; j++)
877
+
icc_link_create(node, qnodes[i]->links[j]);
878
+
879
+
data->nodes[i] = node;
880
+
}
881
+
data->num_nodes = num_nodes;
882
+
platform_set_drvdata(pdev, qp);
883
+
884
+
return 0;
885
+
err:
886
+
icc_nodes_remove(provider);
887
+
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
888
+
icc_provider_del(provider);
889
+
890
+
return ret;
891
+
}
892
+
893
+
static int qnoc_remove(struct platform_device *pdev)
894
+
{
895
+
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
896
+
897
+
icc_nodes_remove(&qp->provider);
898
+
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
899
+
return icc_provider_del(&qp->provider);
900
+
}
901
+
902
+
static const struct of_device_id sdm660_noc_of_match[] = {
903
+
{ .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc },
904
+
{ .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc },
905
+
{ .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc },
906
+
{ .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc },
907
+
{ .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc },
908
+
{ .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc },
909
+
{ },
910
+
};
911
+
MODULE_DEVICE_TABLE(of, sdm660_noc_of_match);
912
+
913
+
static struct platform_driver sdm660_noc_driver = {
914
+
.probe = qnoc_probe,
915
+
.remove = qnoc_remove,
916
+
.driver = {
917
+
.name = "qnoc-sdm660",
918
+
.of_match_table = sdm660_noc_of_match,
919
+
},
920
+
};
921
+
module_platform_driver(sdm660_noc_driver);
922
+
MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver");
923
+
MODULE_LICENSE("GPL v2");
+633
drivers/interconnect/qcom/sm8350.c
+633
drivers/interconnect/qcom/sm8350.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2021, Linaro Limited
5
+
*
6
+
*/
7
+
8
+
#include <linux/interconnect-provider.h>
9
+
#include <linux/module.h>
10
+
#include <linux/of_device.h>
11
+
#include <dt-bindings/interconnect/qcom,sm8350.h>
12
+
13
+
#include "bcm-voter.h"
14
+
#include "icc-rpmh.h"
15
+
#include "sm8350.h"
16
+
17
+
DEFINE_QNODE(qhm_qspi, SM8350_MASTER_QSPI_0, 1, 4, SM8350_SLAVE_A1NOC_SNOC);
18
+
DEFINE_QNODE(qhm_qup0, SM8350_MASTER_QUP_0, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
19
+
DEFINE_QNODE(qhm_qup1, SM8350_MASTER_QUP_1, 1, 4, SM8350_SLAVE_A1NOC_SNOC);
20
+
DEFINE_QNODE(qhm_qup2, SM8350_MASTER_QUP_2, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
21
+
DEFINE_QNODE(qnm_a1noc_cfg, SM8350_MASTER_A1NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A1NOC);
22
+
DEFINE_QNODE(xm_sdc4, SM8350_MASTER_SDCC_4, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
23
+
DEFINE_QNODE(xm_ufs_mem, SM8350_MASTER_UFS_MEM, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
24
+
DEFINE_QNODE(xm_usb3_0, SM8350_MASTER_USB3_0, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
25
+
DEFINE_QNODE(xm_usb3_1, SM8350_MASTER_USB3_1, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
26
+
DEFINE_QNODE(qhm_qdss_bam, SM8350_MASTER_QDSS_BAM, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
27
+
DEFINE_QNODE(qnm_a2noc_cfg, SM8350_MASTER_A2NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A2NOC);
28
+
DEFINE_QNODE(qxm_crypto, SM8350_MASTER_CRYPTO, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
29
+
DEFINE_QNODE(qxm_ipa, SM8350_MASTER_IPA, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
30
+
DEFINE_QNODE(xm_pcie3_0, SM8350_MASTER_PCIE_0, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC);
31
+
DEFINE_QNODE(xm_pcie3_1, SM8350_MASTER_PCIE_1, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC);
32
+
DEFINE_QNODE(xm_qdss_etr, SM8350_MASTER_QDSS_ETR, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
33
+
DEFINE_QNODE(xm_sdc2, SM8350_MASTER_SDCC_2, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
34
+
DEFINE_QNODE(xm_ufs_card, SM8350_MASTER_UFS_CARD, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
35
+
DEFINE_QNODE(qnm_gemnoc_cnoc, SM8350_MASTER_GEM_NOC_CNOC, 1, 16, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU);
36
+
DEFINE_QNODE(qnm_gemnoc_pcie, SM8350_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8350_SLAVE_PCIE_0, SM8350_SLAVE_PCIE_1);
37
+
DEFINE_QNODE(xm_qdss_dap, SM8350_MASTER_QDSS_DAP, 1, 8, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU);
38
+
DEFINE_QNODE(qnm_cnoc_dc_noc, SM8350_MASTER_CNOC_DC_NOC, 1, 4, SM8350_SLAVE_LLCC_CFG, SM8350_SLAVE_GEM_NOC_CFG);
39
+
DEFINE_QNODE(alm_gpu_tcu, SM8350_MASTER_GPU_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
40
+
DEFINE_QNODE(alm_sys_tcu, SM8350_MASTER_SYS_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
41
+
DEFINE_QNODE(chm_apps, SM8350_MASTER_APPSS_PROC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC);
42
+
DEFINE_QNODE(qnm_cmpnoc, SM8350_MASTER_COMPUTE_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
43
+
DEFINE_QNODE(qnm_gemnoc_cfg, SM8350_MASTER_GEM_NOC_CFG, 1, 4, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, SM8350_SLAVE_MCDMA_MS_MPU_CFG, SM8350_SLAVE_SERVICE_GEM_NOC_1, SM8350_SLAVE_SERVICE_GEM_NOC_2, SM8350_SLAVE_SERVICE_GEM_NOC);
44
+
DEFINE_QNODE(qnm_gpu, SM8350_MASTER_GFX3D, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
45
+
DEFINE_QNODE(qnm_mnoc_hf, SM8350_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8350_SLAVE_LLCC);
46
+
DEFINE_QNODE(qnm_mnoc_sf, SM8350_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
47
+
DEFINE_QNODE(qnm_pcie, SM8350_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
48
+
DEFINE_QNODE(qnm_snoc_gc, SM8350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8350_SLAVE_LLCC);
49
+
DEFINE_QNODE(qnm_snoc_sf, SM8350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC);
50
+
DEFINE_QNODE(qhm_config_noc, SM8350_MASTER_CNOC_LPASS_AG_NOC, 1, 4, SM8350_SLAVE_LPASS_CORE_CFG, SM8350_SLAVE_LPASS_LPI_CFG, SM8350_SLAVE_LPASS_MPU_CFG, SM8350_SLAVE_LPASS_TOP_CFG, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, SM8350_SLAVE_SERVICE_LPASS_AG_NOC);
51
+
DEFINE_QNODE(llcc_mc, SM8350_MASTER_LLCC, 4, 4, SM8350_SLAVE_EBI1);
52
+
DEFINE_QNODE(qnm_camnoc_hf, SM8350_MASTER_CAMNOC_HF, 2, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
53
+
DEFINE_QNODE(qnm_camnoc_icp, SM8350_MASTER_CAMNOC_ICP, 1, 8, SM8350_SLAVE_MNOC_SF_MEM_NOC);
54
+
DEFINE_QNODE(qnm_camnoc_sf, SM8350_MASTER_CAMNOC_SF, 2, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
55
+
DEFINE_QNODE(qnm_mnoc_cfg, SM8350_MASTER_CNOC_MNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_MNOC);
56
+
DEFINE_QNODE(qnm_video0, SM8350_MASTER_VIDEO_P0, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
57
+
DEFINE_QNODE(qnm_video1, SM8350_MASTER_VIDEO_P1, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
58
+
DEFINE_QNODE(qnm_video_cvp, SM8350_MASTER_VIDEO_PROC, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
59
+
DEFINE_QNODE(qxm_mdp0, SM8350_MASTER_MDP0, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
60
+
DEFINE_QNODE(qxm_mdp1, SM8350_MASTER_MDP1, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
61
+
DEFINE_QNODE(qxm_rot, SM8350_MASTER_ROTATOR, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
62
+
DEFINE_QNODE(qhm_nsp_noc_config, SM8350_MASTER_CDSP_NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_NSP_NOC);
63
+
DEFINE_QNODE(qxm_nsp, SM8350_MASTER_CDSP_PROC, 2, 32, SM8350_SLAVE_CDSP_MEM_NOC);
64
+
DEFINE_QNODE(qnm_aggre1_noc, SM8350_MASTER_A1NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF);
65
+
DEFINE_QNODE(qnm_aggre2_noc, SM8350_MASTER_A2NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF);
66
+
DEFINE_QNODE(qnm_snoc_cfg, SM8350_MASTER_SNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_SNOC);
67
+
DEFINE_QNODE(qxm_pimem, SM8350_MASTER_PIMEM, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC);
68
+
DEFINE_QNODE(xm_gic, SM8350_MASTER_GIC, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC);
69
+
DEFINE_QNODE(qnm_mnoc_hf_disp, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP);
70
+
DEFINE_QNODE(qnm_mnoc_sf_disp, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP);
71
+
DEFINE_QNODE(llcc_mc_disp, SM8350_MASTER_LLCC_DISP, 4, 4, SM8350_SLAVE_EBI1_DISP);
72
+
DEFINE_QNODE(qxm_mdp0_disp, SM8350_MASTER_MDP0_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP);
73
+
DEFINE_QNODE(qxm_mdp1_disp, SM8350_MASTER_MDP1_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP);
74
+
DEFINE_QNODE(qxm_rot_disp, SM8350_MASTER_ROTATOR_DISP, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP);
75
+
DEFINE_QNODE(qns_a1noc_snoc, SM8350_SLAVE_A1NOC_SNOC, 1, 16, SM8350_MASTER_A1NOC_SNOC);
76
+
DEFINE_QNODE(srvc_aggre1_noc, SM8350_SLAVE_SERVICE_A1NOC, 1, 4);
77
+
DEFINE_QNODE(qns_a2noc_snoc, SM8350_SLAVE_A2NOC_SNOC, 1, 16, SM8350_MASTER_A2NOC_SNOC);
78
+
DEFINE_QNODE(qns_pcie_mem_noc, SM8350_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_MASTER_ANOC_PCIE_GEM_NOC);
79
+
DEFINE_QNODE(srvc_aggre2_noc, SM8350_SLAVE_SERVICE_A2NOC, 1, 4);
80
+
DEFINE_QNODE(qhs_ahb2phy0, SM8350_SLAVE_AHB2PHY_SOUTH, 1, 4);
81
+
DEFINE_QNODE(qhs_ahb2phy1, SM8350_SLAVE_AHB2PHY_NORTH, 1, 4);
82
+
DEFINE_QNODE(qhs_aoss, SM8350_SLAVE_AOSS, 1, 4);
83
+
DEFINE_QNODE(qhs_apss, SM8350_SLAVE_APPSS, 1, 8);
84
+
DEFINE_QNODE(qhs_camera_cfg, SM8350_SLAVE_CAMERA_CFG, 1, 4);
85
+
DEFINE_QNODE(qhs_clk_ctl, SM8350_SLAVE_CLK_CTL, 1, 4);
86
+
DEFINE_QNODE(qhs_compute_cfg, SM8350_SLAVE_CDSP_CFG, 1, 4);
87
+
DEFINE_QNODE(qhs_cpr_cx, SM8350_SLAVE_RBCPR_CX_CFG, 1, 4);
88
+
DEFINE_QNODE(qhs_cpr_mmcx, SM8350_SLAVE_RBCPR_MMCX_CFG, 1, 4);
89
+
DEFINE_QNODE(qhs_cpr_mx, SM8350_SLAVE_RBCPR_MX_CFG, 1, 4);
90
+
DEFINE_QNODE(qhs_crypto0_cfg, SM8350_SLAVE_CRYPTO_0_CFG, 1, 4);
91
+
DEFINE_QNODE(qhs_cx_rdpm, SM8350_SLAVE_CX_RDPM, 1, 4);
92
+
DEFINE_QNODE(qhs_dcc_cfg, SM8350_SLAVE_DCC_CFG, 1, 4);
93
+
DEFINE_QNODE(qhs_display_cfg, SM8350_SLAVE_DISPLAY_CFG, 1, 4);
94
+
DEFINE_QNODE(qhs_gpuss_cfg, SM8350_SLAVE_GFX3D_CFG, 1, 8);
95
+
DEFINE_QNODE(qhs_hwkm, SM8350_SLAVE_HWKM, 1, 4);
96
+
DEFINE_QNODE(qhs_imem_cfg, SM8350_SLAVE_IMEM_CFG, 1, 4);
97
+
DEFINE_QNODE(qhs_ipa, SM8350_SLAVE_IPA_CFG, 1, 4);
98
+
DEFINE_QNODE(qhs_ipc_router, SM8350_SLAVE_IPC_ROUTER_CFG, 1, 4);
99
+
DEFINE_QNODE(qhs_lpass_cfg, SM8350_SLAVE_LPASS, 1, 4, SM8350_MASTER_CNOC_LPASS_AG_NOC);
100
+
DEFINE_QNODE(qhs_mss_cfg, SM8350_SLAVE_CNOC_MSS, 1, 4);
101
+
DEFINE_QNODE(qhs_mx_rdpm, SM8350_SLAVE_MX_RDPM, 1, 4);
102
+
DEFINE_QNODE(qhs_pcie0_cfg, SM8350_SLAVE_PCIE_0_CFG, 1, 4);
103
+
DEFINE_QNODE(qhs_pcie1_cfg, SM8350_SLAVE_PCIE_1_CFG, 1, 4);
104
+
DEFINE_QNODE(qhs_pdm, SM8350_SLAVE_PDM, 1, 4);
105
+
DEFINE_QNODE(qhs_pimem_cfg, SM8350_SLAVE_PIMEM_CFG, 1, 4);
106
+
DEFINE_QNODE(qhs_pka_wrapper_cfg, SM8350_SLAVE_PKA_WRAPPER_CFG, 1, 4);
107
+
DEFINE_QNODE(qhs_pmu_wrapper_cfg, SM8350_SLAVE_PMU_WRAPPER_CFG, 1, 4);
108
+
DEFINE_QNODE(qhs_qdss_cfg, SM8350_SLAVE_QDSS_CFG, 1, 4);
109
+
DEFINE_QNODE(qhs_qspi, SM8350_SLAVE_QSPI_0, 1, 4);
110
+
DEFINE_QNODE(qhs_qup0, SM8350_SLAVE_QUP_0, 1, 4);
111
+
DEFINE_QNODE(qhs_qup1, SM8350_SLAVE_QUP_1, 1, 4);
112
+
DEFINE_QNODE(qhs_qup2, SM8350_SLAVE_QUP_2, 1, 4);
113
+
DEFINE_QNODE(qhs_sdc2, SM8350_SLAVE_SDCC_2, 1, 4);
114
+
DEFINE_QNODE(qhs_sdc4, SM8350_SLAVE_SDCC_4, 1, 4);
115
+
DEFINE_QNODE(qhs_security, SM8350_SLAVE_SECURITY, 1, 4);
116
+
DEFINE_QNODE(qhs_spss_cfg, SM8350_SLAVE_SPSS_CFG, 1, 4);
117
+
DEFINE_QNODE(qhs_tcsr, SM8350_SLAVE_TCSR, 1, 4);
118
+
DEFINE_QNODE(qhs_tlmm, SM8350_SLAVE_TLMM, 1, 4);
119
+
DEFINE_QNODE(qhs_ufs_card_cfg, SM8350_SLAVE_UFS_CARD_CFG, 1, 4);
120
+
DEFINE_QNODE(qhs_ufs_mem_cfg, SM8350_SLAVE_UFS_MEM_CFG, 1, 4);
121
+
DEFINE_QNODE(qhs_usb3_0, SM8350_SLAVE_USB3_0, 1, 4);
122
+
DEFINE_QNODE(qhs_usb3_1, SM8350_SLAVE_USB3_1, 1, 4);
123
+
DEFINE_QNODE(qhs_venus_cfg, SM8350_SLAVE_VENUS_CFG, 1, 4);
124
+
DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8350_SLAVE_VSENSE_CTRL_CFG, 1, 4);
125
+
DEFINE_QNODE(qns_a1_noc_cfg, SM8350_SLAVE_A1NOC_CFG, 1, 4);
126
+
DEFINE_QNODE(qns_a2_noc_cfg, SM8350_SLAVE_A2NOC_CFG, 1, 4);
127
+
DEFINE_QNODE(qns_ddrss_cfg, SM8350_SLAVE_DDRSS_CFG, 1, 4);
128
+
DEFINE_QNODE(qns_mnoc_cfg, SM8350_SLAVE_CNOC_MNOC_CFG, 1, 4);
129
+
DEFINE_QNODE(qns_snoc_cfg, SM8350_SLAVE_SNOC_CFG, 1, 4);
130
+
DEFINE_QNODE(qxs_boot_imem, SM8350_SLAVE_BOOT_IMEM, 1, 8);
131
+
DEFINE_QNODE(qxs_imem, SM8350_SLAVE_IMEM, 1, 8);
132
+
DEFINE_QNODE(qxs_pimem, SM8350_SLAVE_PIMEM, 1, 8);
133
+
DEFINE_QNODE(srvc_cnoc, SM8350_SLAVE_SERVICE_CNOC, 1, 4);
134
+
DEFINE_QNODE(xs_pcie_0, SM8350_SLAVE_PCIE_0, 1, 8);
135
+
DEFINE_QNODE(xs_pcie_1, SM8350_SLAVE_PCIE_1, 1, 8);
136
+
DEFINE_QNODE(xs_qdss_stm, SM8350_SLAVE_QDSS_STM, 1, 4);
137
+
DEFINE_QNODE(xs_sys_tcu_cfg, SM8350_SLAVE_TCU, 1, 8);
138
+
DEFINE_QNODE(qhs_llcc, SM8350_SLAVE_LLCC_CFG, 1, 4);
139
+
DEFINE_QNODE(qns_gemnoc, SM8350_SLAVE_GEM_NOC_CFG, 1, 4);
140
+
DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
141
+
DEFINE_QNODE(qhs_modem_ms_mpu_cfg, SM8350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4);
142
+
DEFINE_QNODE(qns_gem_noc_cnoc, SM8350_SLAVE_GEM_NOC_CNOC, 1, 16, SM8350_MASTER_GEM_NOC_CNOC);
143
+
DEFINE_QNODE(qns_llcc, SM8350_SLAVE_LLCC, 4, 16, SM8350_MASTER_LLCC);
144
+
DEFINE_QNODE(qns_pcie, SM8350_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8);
145
+
DEFINE_QNODE(srvc_even_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
146
+
DEFINE_QNODE(srvc_odd_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
147
+
DEFINE_QNODE(srvc_sys_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC, 1, 4);
148
+
DEFINE_QNODE(qhs_lpass_core, SM8350_SLAVE_LPASS_CORE_CFG, 1, 4);
149
+
DEFINE_QNODE(qhs_lpass_lpi, SM8350_SLAVE_LPASS_LPI_CFG, 1, 4);
150
+
DEFINE_QNODE(qhs_lpass_mpu, SM8350_SLAVE_LPASS_MPU_CFG, 1, 4);
151
+
DEFINE_QNODE(qhs_lpass_top, SM8350_SLAVE_LPASS_TOP_CFG, 1, 4);
152
+
DEFINE_QNODE(srvc_niu_aml_noc, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, 1, 4);
153
+
DEFINE_QNODE(srvc_niu_lpass_agnoc, SM8350_SLAVE_SERVICE_LPASS_AG_NOC, 1, 4);
154
+
DEFINE_QNODE(ebi, SM8350_SLAVE_EBI1, 4, 4);
155
+
DEFINE_QNODE(qns_mem_noc_hf, SM8350_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC);
156
+
DEFINE_QNODE(qns_mem_noc_sf, SM8350_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC);
157
+
DEFINE_QNODE(srvc_mnoc, SM8350_SLAVE_SERVICE_MNOC, 1, 4);
158
+
DEFINE_QNODE(qns_nsp_gemnoc, SM8350_SLAVE_CDSP_MEM_NOC, 2, 32, SM8350_MASTER_COMPUTE_NOC);
159
+
DEFINE_QNODE(service_nsp_noc, SM8350_SLAVE_SERVICE_NSP_NOC, 1, 4);
160
+
DEFINE_QNODE(qns_gemnoc_gc, SM8350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8350_MASTER_SNOC_GC_MEM_NOC);
161
+
DEFINE_QNODE(qns_gemnoc_sf, SM8350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8350_MASTER_SNOC_SF_MEM_NOC);
162
+
DEFINE_QNODE(srvc_snoc, SM8350_SLAVE_SERVICE_SNOC, 1, 4);
163
+
DEFINE_QNODE(qns_llcc_disp, SM8350_SLAVE_LLCC_DISP, 4, 16, SM8350_MASTER_LLCC_DISP);
164
+
DEFINE_QNODE(ebi_disp, SM8350_SLAVE_EBI1_DISP, 4, 4);
165
+
DEFINE_QNODE(qns_mem_noc_hf_disp, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP);
166
+
DEFINE_QNODE(qns_mem_noc_sf_disp, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP);
167
+
168
+
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
169
+
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
170
+
DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie);
171
+
DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_apss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_cfg, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_hwkm, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_mss_cfg, &qhs_mx_rdpm, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_security, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, &qns_a2_noc_cfg, &qns_ddrss_cfg, &qns_mnoc_cfg, &qns_snoc_cfg, &srvc_cnoc);
172
+
DEFINE_QBCM(bcm_cn2, "CN2", false, &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4);
173
+
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_nsp_gemnoc);
174
+
DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_nsp);
175
+
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
176
+
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
177
+
DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
178
+
DEFINE_QBCM(bcm_mm4, "MM4", false, &qns_mem_noc_sf);
179
+
DEFINE_QBCM(bcm_mm5, "MM5", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp, &qxm_rot);
180
+
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
181
+
DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
182
+
DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
183
+
DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
184
+
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
185
+
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
186
+
DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
187
+
DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
188
+
DEFINE_QBCM(bcm_sn5, "SN5", false, &xm_pcie3_0);
189
+
DEFINE_QBCM(bcm_sn6, "SN6", false, &xm_pcie3_1);
190
+
DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
191
+
DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
192
+
DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
193
+
DEFINE_QBCM(bcm_acv_disp, "ACV", false, &ebi_disp);
194
+
DEFINE_QBCM(bcm_mc0_disp, "MC0", false, &ebi_disp);
195
+
DEFINE_QBCM(bcm_mm0_disp, "MM0", false, &qns_mem_noc_hf_disp);
196
+
DEFINE_QBCM(bcm_mm1_disp, "MM1", false, &qxm_mdp0_disp, &qxm_mdp1_disp);
197
+
DEFINE_QBCM(bcm_mm4_disp, "MM4", false, &qns_mem_noc_sf_disp);
198
+
DEFINE_QBCM(bcm_mm5_disp, "MM5", false, &qxm_rot_disp);
199
+
DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp);
200
+
201
+
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
202
+
};
203
+
204
+
static struct qcom_icc_node *aggre1_noc_nodes[] = {
205
+
[MASTER_QSPI_0] = &qhm_qspi,
206
+
[MASTER_QUP_1] = &qhm_qup1,
207
+
[MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
208
+
[MASTER_SDCC_4] = &xm_sdc4,
209
+
[MASTER_UFS_MEM] = &xm_ufs_mem,
210
+
[MASTER_USB3_0] = &xm_usb3_0,
211
+
[MASTER_USB3_1] = &xm_usb3_1,
212
+
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
213
+
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
214
+
};
215
+
216
+
static struct qcom_icc_desc sm8350_aggre1_noc = {
217
+
.nodes = aggre1_noc_nodes,
218
+
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
219
+
.bcms = aggre1_noc_bcms,
220
+
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
221
+
};
222
+
223
+
static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
224
+
&bcm_ce0,
225
+
&bcm_sn5,
226
+
&bcm_sn6,
227
+
&bcm_sn14,
228
+
};
229
+
230
+
static struct qcom_icc_node *aggre2_noc_nodes[] = {
231
+
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
232
+
[MASTER_QUP_0] = &qhm_qup0,
233
+
[MASTER_QUP_2] = &qhm_qup2,
234
+
[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
235
+
[MASTER_CRYPTO] = &qxm_crypto,
236
+
[MASTER_IPA] = &qxm_ipa,
237
+
[MASTER_PCIE_0] = &xm_pcie3_0,
238
+
[MASTER_PCIE_1] = &xm_pcie3_1,
239
+
[MASTER_QDSS_ETR] = &xm_qdss_etr,
240
+
[MASTER_SDCC_2] = &xm_sdc2,
241
+
[MASTER_UFS_CARD] = &xm_ufs_card,
242
+
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
243
+
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
244
+
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
245
+
};
246
+
247
+
static struct qcom_icc_desc sm8350_aggre2_noc = {
248
+
.nodes = aggre2_noc_nodes,
249
+
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
250
+
.bcms = aggre2_noc_bcms,
251
+
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
252
+
};
253
+
254
+
static struct qcom_icc_bcm *config_noc_bcms[] = {
255
+
&bcm_cn0,
256
+
&bcm_cn1,
257
+
&bcm_cn2,
258
+
&bcm_sn3,
259
+
&bcm_sn4,
260
+
};
261
+
262
+
static struct qcom_icc_node *config_noc_nodes[] = {
263
+
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
264
+
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
265
+
[MASTER_QDSS_DAP] = &xm_qdss_dap,
266
+
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
267
+
[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
268
+
[SLAVE_AOSS] = &qhs_aoss,
269
+
[SLAVE_APPSS] = &qhs_apss,
270
+
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
271
+
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
272
+
[SLAVE_CDSP_CFG] = &qhs_compute_cfg,
273
+
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
274
+
[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
275
+
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
276
+
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
277
+
[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
278
+
[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
279
+
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
280
+
[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
281
+
[SLAVE_HWKM] = &qhs_hwkm,
282
+
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
283
+
[SLAVE_IPA_CFG] = &qhs_ipa,
284
+
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
285
+
[SLAVE_LPASS] = &qhs_lpass_cfg,
286
+
[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
287
+
[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
288
+
[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
289
+
[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
290
+
[SLAVE_PDM] = &qhs_pdm,
291
+
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
292
+
[SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
293
+
[SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
294
+
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
295
+
[SLAVE_QSPI_0] = &qhs_qspi,
296
+
[SLAVE_QUP_0] = &qhs_qup0,
297
+
[SLAVE_QUP_1] = &qhs_qup1,
298
+
[SLAVE_QUP_2] = &qhs_qup2,
299
+
[SLAVE_SDCC_2] = &qhs_sdc2,
300
+
[SLAVE_SDCC_4] = &qhs_sdc4,
301
+
[SLAVE_SECURITY] = &qhs_security,
302
+
[SLAVE_SPSS_CFG] = &qhs_spss_cfg,
303
+
[SLAVE_TCSR] = &qhs_tcsr,
304
+
[SLAVE_TLMM] = &qhs_tlmm,
305
+
[SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
306
+
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
307
+
[SLAVE_USB3_0] = &qhs_usb3_0,
308
+
[SLAVE_USB3_1] = &qhs_usb3_1,
309
+
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
310
+
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
311
+
[SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
312
+
[SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
313
+
[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
314
+
[SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
315
+
[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
316
+
[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
317
+
[SLAVE_IMEM] = &qxs_imem,
318
+
[SLAVE_PIMEM] = &qxs_pimem,
319
+
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
320
+
[SLAVE_PCIE_0] = &xs_pcie_0,
321
+
[SLAVE_PCIE_1] = &xs_pcie_1,
322
+
[SLAVE_QDSS_STM] = &xs_qdss_stm,
323
+
[SLAVE_TCU] = &xs_sys_tcu_cfg,
324
+
};
325
+
326
+
static struct qcom_icc_desc sm8350_config_noc = {
327
+
.nodes = config_noc_nodes,
328
+
.num_nodes = ARRAY_SIZE(config_noc_nodes),
329
+
.bcms = config_noc_bcms,
330
+
.num_bcms = ARRAY_SIZE(config_noc_bcms),
331
+
};
332
+
333
+
static struct qcom_icc_bcm *dc_noc_bcms[] = {
334
+
};
335
+
336
+
static struct qcom_icc_node *dc_noc_nodes[] = {
337
+
[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
338
+
[SLAVE_LLCC_CFG] = &qhs_llcc,
339
+
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
340
+
};
341
+
342
+
static struct qcom_icc_desc sm8350_dc_noc = {
343
+
.nodes = dc_noc_nodes,
344
+
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
345
+
.bcms = dc_noc_bcms,
346
+
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
347
+
};
348
+
349
+
static struct qcom_icc_bcm *gem_noc_bcms[] = {
350
+
&bcm_sh0,
351
+
&bcm_sh2,
352
+
&bcm_sh3,
353
+
&bcm_sh4,
354
+
&bcm_sh0_disp,
355
+
};
356
+
357
+
static struct qcom_icc_node *gem_noc_nodes[] = {
358
+
[MASTER_GPU_TCU] = &alm_gpu_tcu,
359
+
[MASTER_SYS_TCU] = &alm_sys_tcu,
360
+
[MASTER_APPSS_PROC] = &chm_apps,
361
+
[MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
362
+
[MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
363
+
[MASTER_GFX3D] = &qnm_gpu,
364
+
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
365
+
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
366
+
[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
367
+
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
368
+
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
369
+
[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
370
+
[SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
371
+
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
372
+
[SLAVE_LLCC] = &qns_llcc,
373
+
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
374
+
[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
375
+
[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
376
+
[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
377
+
[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
378
+
[MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp,
379
+
[SLAVE_LLCC_DISP] = &qns_llcc_disp,
380
+
};
381
+
382
+
static struct qcom_icc_desc sm8350_gem_noc = {
383
+
.nodes = gem_noc_nodes,
384
+
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
385
+
.bcms = gem_noc_bcms,
386
+
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
387
+
};
388
+
389
+
static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
390
+
};
391
+
392
+
static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
393
+
[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
394
+
[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
395
+
[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
396
+
[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
397
+
[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
398
+
[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
399
+
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
400
+
};
401
+
402
+
static struct qcom_icc_desc sm8350_lpass_ag_noc = {
403
+
.nodes = lpass_ag_noc_nodes,
404
+
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
405
+
.bcms = lpass_ag_noc_bcms,
406
+
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
407
+
};
408
+
409
+
static struct qcom_icc_bcm *mc_virt_bcms[] = {
410
+
&bcm_acv,
411
+
&bcm_mc0,
412
+
&bcm_acv_disp,
413
+
&bcm_mc0_disp,
414
+
};
415
+
416
+
static struct qcom_icc_node *mc_virt_nodes[] = {
417
+
[MASTER_LLCC] = &llcc_mc,
418
+
[SLAVE_EBI1] = &ebi,
419
+
[MASTER_LLCC_DISP] = &llcc_mc_disp,
420
+
[SLAVE_EBI1_DISP] = &ebi_disp,
421
+
};
422
+
423
+
static struct qcom_icc_desc sm8350_mc_virt = {
424
+
.nodes = mc_virt_nodes,
425
+
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
426
+
.bcms = mc_virt_bcms,
427
+
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
428
+
};
429
+
430
+
static struct qcom_icc_bcm *mmss_noc_bcms[] = {
431
+
&bcm_mm0,
432
+
&bcm_mm1,
433
+
&bcm_mm4,
434
+
&bcm_mm5,
435
+
&bcm_mm0_disp,
436
+
&bcm_mm1_disp,
437
+
&bcm_mm4_disp,
438
+
&bcm_mm5_disp,
439
+
};
440
+
441
+
static struct qcom_icc_node *mmss_noc_nodes[] = {
442
+
[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
443
+
[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
444
+
[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
445
+
[MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
446
+
[MASTER_VIDEO_P0] = &qnm_video0,
447
+
[MASTER_VIDEO_P1] = &qnm_video1,
448
+
[MASTER_VIDEO_PROC] = &qnm_video_cvp,
449
+
[MASTER_MDP0] = &qxm_mdp0,
450
+
[MASTER_MDP1] = &qxm_mdp1,
451
+
[MASTER_ROTATOR] = &qxm_rot,
452
+
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
453
+
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
454
+
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
455
+
[MASTER_MDP0_DISP] = &qxm_mdp0_disp,
456
+
[MASTER_MDP1_DISP] = &qxm_mdp1_disp,
457
+
[MASTER_ROTATOR_DISP] = &qxm_rot_disp,
458
+
[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
459
+
[SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp,
460
+
};
461
+
462
+
static struct qcom_icc_desc sm8350_mmss_noc = {
463
+
.nodes = mmss_noc_nodes,
464
+
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
465
+
.bcms = mmss_noc_bcms,
466
+
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
467
+
};
468
+
469
+
static struct qcom_icc_bcm *nsp_noc_bcms[] = {
470
+
&bcm_co0,
471
+
&bcm_co3,
472
+
};
473
+
474
+
static struct qcom_icc_node *nsp_noc_nodes[] = {
475
+
[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
476
+
[MASTER_CDSP_PROC] = &qxm_nsp,
477
+
[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
478
+
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
479
+
};
480
+
481
+
static struct qcom_icc_desc sm8350_compute_noc = {
482
+
.nodes = nsp_noc_nodes,
483
+
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
484
+
.bcms = nsp_noc_bcms,
485
+
.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
486
+
};
487
+
488
+
static struct qcom_icc_bcm *system_noc_bcms[] = {
489
+
&bcm_sn0,
490
+
&bcm_sn2,
491
+
&bcm_sn7,
492
+
&bcm_sn8,
493
+
};
494
+
495
+
static struct qcom_icc_node *system_noc_nodes[] = {
496
+
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
497
+
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
498
+
[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
499
+
[MASTER_PIMEM] = &qxm_pimem,
500
+
[MASTER_GIC] = &xm_gic,
501
+
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
502
+
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
503
+
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
504
+
};
505
+
506
+
static struct qcom_icc_desc sm8350_system_noc = {
507
+
.nodes = system_noc_nodes,
508
+
.num_nodes = ARRAY_SIZE(system_noc_nodes),
509
+
.bcms = system_noc_bcms,
510
+
.num_bcms = ARRAY_SIZE(system_noc_bcms),
511
+
};
512
+
513
+
static int qnoc_probe(struct platform_device *pdev)
514
+
{
515
+
const struct qcom_icc_desc *desc;
516
+
struct icc_onecell_data *data;
517
+
struct icc_provider *provider;
518
+
struct qcom_icc_node **qnodes;
519
+
struct qcom_icc_provider *qp;
520
+
struct icc_node *node;
521
+
size_t num_nodes, i;
522
+
int ret;
523
+
524
+
desc = of_device_get_match_data(&pdev->dev);
525
+
if (!desc)
526
+
return -EINVAL;
527
+
528
+
qnodes = desc->nodes;
529
+
num_nodes = desc->num_nodes;
530
+
531
+
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
532
+
if (!qp)
533
+
return -ENOMEM;
534
+
535
+
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
536
+
if (!data)
537
+
return -ENOMEM;
538
+
539
+
provider = &qp->provider;
540
+
provider->dev = &pdev->dev;
541
+
provider->set = qcom_icc_set;
542
+
provider->pre_aggregate = qcom_icc_pre_aggregate;
543
+
provider->aggregate = qcom_icc_aggregate;
544
+
provider->xlate = of_icc_xlate_onecell;
545
+
INIT_LIST_HEAD(&provider->nodes);
546
+
provider->data = data;
547
+
548
+
qp->dev = &pdev->dev;
549
+
qp->bcms = desc->bcms;
550
+
qp->num_bcms = desc->num_bcms;
551
+
552
+
qp->voter = of_bcm_voter_get(qp->dev, NULL);
553
+
if (IS_ERR(qp->voter))
554
+
return PTR_ERR(qp->voter);
555
+
556
+
ret = icc_provider_add(provider);
557
+
if (ret) {
558
+
dev_err(&pdev->dev, "error adding interconnect provider\n");
559
+
return ret;
560
+
}
561
+
562
+
for (i = 0; i < qp->num_bcms; i++)
563
+
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
564
+
565
+
for (i = 0; i < num_nodes; i++) {
566
+
size_t j;
567
+
568
+
if (!qnodes[i])
569
+
continue;
570
+
571
+
node = icc_node_create(qnodes[i]->id);
572
+
if (IS_ERR(node)) {
573
+
ret = PTR_ERR(node);
574
+
goto err;
575
+
}
576
+
577
+
node->name = qnodes[i]->name;
578
+
node->data = qnodes[i];
579
+
icc_node_add(node, provider);
580
+
581
+
for (j = 0; j < qnodes[i]->num_links; j++)
582
+
icc_link_create(node, qnodes[i]->links[j]);
583
+
584
+
data->nodes[i] = node;
585
+
}
586
+
data->num_nodes = num_nodes;
587
+
588
+
platform_set_drvdata(pdev, qp);
589
+
590
+
return ret;
591
+
592
+
err:
593
+
icc_nodes_remove(provider);
594
+
icc_provider_del(provider);
595
+
return ret;
596
+
}
597
+
598
+
static int qnoc_remove(struct platform_device *pdev)
599
+
{
600
+
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
601
+
602
+
icc_nodes_remove(&qp->provider);
603
+
return icc_provider_del(&qp->provider);
604
+
}
605
+
606
+
static const struct of_device_id qnoc_of_match[] = {
607
+
{ .compatible = "qcom,sm8350-aggre1-noc", .data = &sm8350_aggre1_noc},
608
+
{ .compatible = "qcom,sm8350-aggre2-noc", .data = &sm8350_aggre2_noc},
609
+
{ .compatible = "qcom,sm8350-config-noc", .data = &sm8350_config_noc},
610
+
{ .compatible = "qcom,sm8350-dc-noc", .data = &sm8350_dc_noc},
611
+
{ .compatible = "qcom,sm8350-gem-noc", .data = &sm8350_gem_noc},
612
+
{ .compatible = "qcom,sm8350-lpass-ag-noc", .data = &sm8350_lpass_ag_noc},
613
+
{ .compatible = "qcom,sm8350-mc-virt", .data = &sm8350_mc_virt},
614
+
{ .compatible = "qcom,sm8350-mmss-noc", .data = &sm8350_mmss_noc},
615
+
{ .compatible = "qcom,sm8350-compute-noc", .data = &sm8350_compute_noc},
616
+
{ .compatible = "qcom,sm8350-system-noc", .data = &sm8350_system_noc},
617
+
{ }
618
+
};
619
+
MODULE_DEVICE_TABLE(of, qnoc_of_match);
620
+
621
+
static struct platform_driver qnoc_driver = {
622
+
.probe = qnoc_probe,
623
+
.remove = qnoc_remove,
624
+
.driver = {
625
+
.name = "qnoc-sm8350",
626
+
.of_match_table = qnoc_of_match,
627
+
.sync_state = icc_sync_state,
628
+
},
629
+
};
630
+
module_platform_driver(qnoc_driver);
631
+
632
+
MODULE_DESCRIPTION("SM8350 NoC driver");
633
+
MODULE_LICENSE("GPL v2");
+168
drivers/interconnect/qcom/sm8350.h
+168
drivers/interconnect/qcom/sm8350.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Qualcomm SM8350 interconnect IDs
4
+
*
5
+
* Copyright (c) 2021, Linaro Limited
6
+
*/
7
+
8
+
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8350_H
9
+
#define __DRIVERS_INTERCONNECT_QCOM_SM8350_H
10
+
11
+
#define SM8350_MASTER_GPU_TCU 0
12
+
#define SM8350_MASTER_SYS_TCU 1
13
+
#define SM8350_MASTER_APPSS_PROC 2
14
+
#define SM8350_MASTER_LLCC 3
15
+
#define SM8350_MASTER_CNOC_LPASS_AG_NOC 4
16
+
#define SM8350_MASTER_CDSP_NOC_CFG 5
17
+
#define SM8350_MASTER_QDSS_BAM 6
18
+
#define SM8350_MASTER_QSPI_0 7
19
+
#define SM8350_MASTER_QUP_0 8
20
+
#define SM8350_MASTER_QUP_1 9
21
+
#define SM8350_MASTER_QUP_2 10
22
+
#define SM8350_MASTER_A1NOC_CFG 11
23
+
#define SM8350_MASTER_A2NOC_CFG 12
24
+
#define SM8350_MASTER_A1NOC_SNOC 13
25
+
#define SM8350_MASTER_A2NOC_SNOC 14
26
+
#define SM8350_MASTER_CAMNOC_HF 15
27
+
#define SM8350_MASTER_CAMNOC_ICP 16
28
+
#define SM8350_MASTER_CAMNOC_SF 17
29
+
#define SM8350_MASTER_COMPUTE_NOC 18
30
+
#define SM8350_MASTER_CNOC_DC_NOC 19
31
+
#define SM8350_MASTER_GEM_NOC_CFG 20
32
+
#define SM8350_MASTER_GEM_NOC_CNOC 21
33
+
#define SM8350_MASTER_GEM_NOC_PCIE_SNOC 22
34
+
#define SM8350_MASTER_GFX3D 23
35
+
#define SM8350_MASTER_CNOC_MNOC_CFG 24
36
+
#define SM8350_MASTER_MNOC_HF_MEM_NOC 25
37
+
#define SM8350_MASTER_MNOC_SF_MEM_NOC 26
38
+
#define SM8350_MASTER_ANOC_PCIE_GEM_NOC 27
39
+
#define SM8350_MASTER_SNOC_CFG 28
40
+
#define SM8350_MASTER_SNOC_GC_MEM_NOC 29
41
+
#define SM8350_MASTER_SNOC_SF_MEM_NOC 30
42
+
#define SM8350_MASTER_VIDEO_P0 31
43
+
#define SM8350_MASTER_VIDEO_P1 32
44
+
#define SM8350_MASTER_VIDEO_PROC 33
45
+
#define SM8350_MASTER_QUP_CORE_0 34
46
+
#define SM8350_MASTER_QUP_CORE_1 35
47
+
#define SM8350_MASTER_QUP_CORE_2 36
48
+
#define SM8350_MASTER_CRYPTO 37
49
+
#define SM8350_MASTER_IPA 38
50
+
#define SM8350_MASTER_MDP0 39
51
+
#define SM8350_MASTER_MDP1 40
52
+
#define SM8350_MASTER_CDSP_PROC 41
53
+
#define SM8350_MASTER_PIMEM 42
54
+
#define SM8350_MASTER_ROTATOR 43
55
+
#define SM8350_MASTER_GIC 44
56
+
#define SM8350_MASTER_PCIE_0 45
57
+
#define SM8350_MASTER_PCIE_1 46
58
+
#define SM8350_MASTER_QDSS_DAP 47
59
+
#define SM8350_MASTER_QDSS_ETR 48
60
+
#define SM8350_MASTER_SDCC_2 49
61
+
#define SM8350_MASTER_SDCC_4 50
62
+
#define SM8350_MASTER_UFS_CARD 51
63
+
#define SM8350_MASTER_UFS_MEM 52
64
+
#define SM8350_MASTER_USB3_0 53
65
+
#define SM8350_MASTER_USB3_1 54
66
+
#define SM8350_SLAVE_EBI1 55
67
+
#define SM8350_SLAVE_AHB2PHY_SOUTH 56
68
+
#define SM8350_SLAVE_AHB2PHY_NORTH 57
69
+
#define SM8350_SLAVE_AOSS 58
70
+
#define SM8350_SLAVE_APPSS 59
71
+
#define SM8350_SLAVE_CAMERA_CFG 60
72
+
#define SM8350_SLAVE_CLK_CTL 61
73
+
#define SM8350_SLAVE_CDSP_CFG 62
74
+
#define SM8350_SLAVE_RBCPR_CX_CFG 63
75
+
#define SM8350_SLAVE_RBCPR_MMCX_CFG 64
76
+
#define SM8350_SLAVE_RBCPR_MX_CFG 65
77
+
#define SM8350_SLAVE_CRYPTO_0_CFG 66
78
+
#define SM8350_SLAVE_CX_RDPM 67
79
+
#define SM8350_SLAVE_DCC_CFG 68
80
+
#define SM8350_SLAVE_DISPLAY_CFG 69
81
+
#define SM8350_SLAVE_GFX3D_CFG 70
82
+
#define SM8350_SLAVE_HWKM 71
83
+
#define SM8350_SLAVE_IMEM_CFG 72
84
+
#define SM8350_SLAVE_IPA_CFG 73
85
+
#define SM8350_SLAVE_IPC_ROUTER_CFG 74
86
+
#define SM8350_SLAVE_LLCC_CFG 75
87
+
#define SM8350_SLAVE_LPASS 76
88
+
#define SM8350_SLAVE_LPASS_CORE_CFG 77
89
+
#define SM8350_SLAVE_LPASS_LPI_CFG 78
90
+
#define SM8350_SLAVE_LPASS_MPU_CFG 79
91
+
#define SM8350_SLAVE_LPASS_TOP_CFG 80
92
+
#define SM8350_SLAVE_MSS_PROC_MS_MPU_CFG 81
93
+
#define SM8350_SLAVE_MCDMA_MS_MPU_CFG 82
94
+
#define SM8350_SLAVE_CNOC_MSS 83
95
+
#define SM8350_SLAVE_MX_RDPM 84
96
+
#define SM8350_SLAVE_PCIE_0_CFG 85
97
+
#define SM8350_SLAVE_PCIE_1_CFG 86
98
+
#define SM8350_SLAVE_PDM 87
99
+
#define SM8350_SLAVE_PIMEM_CFG 88
100
+
#define SM8350_SLAVE_PKA_WRAPPER_CFG 89
101
+
#define SM8350_SLAVE_PMU_WRAPPER_CFG 90
102
+
#define SM8350_SLAVE_QDSS_CFG 91
103
+
#define SM8350_SLAVE_QSPI_0 92
104
+
#define SM8350_SLAVE_QUP_0 93
105
+
#define SM8350_SLAVE_QUP_1 94
106
+
#define SM8350_SLAVE_QUP_2 95
107
+
#define SM8350_SLAVE_SDCC_2 96
108
+
#define SM8350_SLAVE_SDCC_4 97
109
+
#define SM8350_SLAVE_SECURITY 98
110
+
#define SM8350_SLAVE_SPSS_CFG 99
111
+
#define SM8350_SLAVE_TCSR 100
112
+
#define SM8350_SLAVE_TLMM 101
113
+
#define SM8350_SLAVE_UFS_CARD_CFG 102
114
+
#define SM8350_SLAVE_UFS_MEM_CFG 103
115
+
#define SM8350_SLAVE_USB3_0 104
116
+
#define SM8350_SLAVE_USB3_1 105
117
+
#define SM8350_SLAVE_VENUS_CFG 106
118
+
#define SM8350_SLAVE_VSENSE_CTRL_CFG 107
119
+
#define SM8350_SLAVE_A1NOC_CFG 108
120
+
#define SM8350_SLAVE_A1NOC_SNOC 109
121
+
#define SM8350_SLAVE_A2NOC_CFG 110
122
+
#define SM8350_SLAVE_A2NOC_SNOC 111
123
+
#define SM8350_SLAVE_DDRSS_CFG 112
124
+
#define SM8350_SLAVE_GEM_NOC_CNOC 113
125
+
#define SM8350_SLAVE_GEM_NOC_CFG 114
126
+
#define SM8350_SLAVE_SNOC_GEM_NOC_GC 115
127
+
#define SM8350_SLAVE_SNOC_GEM_NOC_SF 116
128
+
#define SM8350_SLAVE_LLCC 117
129
+
#define SM8350_SLAVE_MNOC_HF_MEM_NOC 118
130
+
#define SM8350_SLAVE_MNOC_SF_MEM_NOC 119
131
+
#define SM8350_SLAVE_CNOC_MNOC_CFG 120
132
+
#define SM8350_SLAVE_CDSP_MEM_NOC 121
133
+
#define SM8350_SLAVE_MEM_NOC_PCIE_SNOC 122
134
+
#define SM8350_SLAVE_ANOC_PCIE_GEM_NOC 123
135
+
#define SM8350_SLAVE_SNOC_CFG 124
136
+
#define SM8350_SLAVE_QUP_CORE_0 125
137
+
#define SM8350_SLAVE_QUP_CORE_1 126
138
+
#define SM8350_SLAVE_QUP_CORE_2 127
139
+
#define SM8350_SLAVE_BOOT_IMEM 128
140
+
#define SM8350_SLAVE_IMEM 129
141
+
#define SM8350_SLAVE_PIMEM 130
142
+
#define SM8350_SLAVE_SERVICE_NSP_NOC 131
143
+
#define SM8350_SLAVE_SERVICE_A1NOC 132
144
+
#define SM8350_SLAVE_SERVICE_A2NOC 133
145
+
#define SM8350_SLAVE_SERVICE_CNOC 134
146
+
#define SM8350_SLAVE_SERVICE_GEM_NOC_1 135
147
+
#define SM8350_SLAVE_SERVICE_MNOC 136
148
+
#define SM8350_SLAVE_SERVICES_LPASS_AML_NOC 137
149
+
#define SM8350_SLAVE_SERVICE_LPASS_AG_NOC 138
150
+
#define SM8350_SLAVE_SERVICE_GEM_NOC_2 139
151
+
#define SM8350_SLAVE_SERVICE_SNOC 140
152
+
#define SM8350_SLAVE_SERVICE_GEM_NOC 141
153
+
#define SM8350_SLAVE_PCIE_0 142
154
+
#define SM8350_SLAVE_PCIE_1 143
155
+
#define SM8350_SLAVE_QDSS_STM 144
156
+
#define SM8350_SLAVE_TCU 145
157
+
#define SM8350_MASTER_LLCC_DISP 146
158
+
#define SM8350_MASTER_MNOC_HF_MEM_NOC_DISP 147
159
+
#define SM8350_MASTER_MNOC_SF_MEM_NOC_DISP 148
160
+
#define SM8350_MASTER_MDP0_DISP 149
161
+
#define SM8350_MASTER_MDP1_DISP 150
162
+
#define SM8350_MASTER_ROTATOR_DISP 151
163
+
#define SM8350_SLAVE_EBI1_DISP 152
164
+
#define SM8350_SLAVE_LLCC_DISP 153
165
+
#define SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP 154
166
+
#define SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP 155
167
+
168
+
#endif
+116
include/dt-bindings/interconnect/qcom,sdm660.h
+116
include/dt-bindings/interconnect/qcom,sdm660.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/* SDM660 interconnect IDs */
3
+
4
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM660_H
5
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM660_H
6
+
7
+
/* A2NOC */
8
+
#define MASTER_IPA 0
9
+
#define MASTER_CNOC_A2NOC 1
10
+
#define MASTER_SDCC_1 2
11
+
#define MASTER_SDCC_2 3
12
+
#define MASTER_BLSP_1 4
13
+
#define MASTER_BLSP_2 5
14
+
#define MASTER_UFS 6
15
+
#define MASTER_USB_HS 7
16
+
#define MASTER_USB3 8
17
+
#define MASTER_CRYPTO_C0 9
18
+
#define SLAVE_A2NOC_SNOC 10
19
+
20
+
/* BIMC */
21
+
#define MASTER_GNOC_BIMC 0
22
+
#define MASTER_OXILI 1
23
+
#define MASTER_MNOC_BIMC 2
24
+
#define MASTER_SNOC_BIMC 3
25
+
#define MASTER_PIMEM 4
26
+
#define SLAVE_EBI 5
27
+
#define SLAVE_HMSS_L3 6
28
+
#define SLAVE_BIMC_SNOC 7
29
+
30
+
/* CNOC */
31
+
#define MASTER_SNOC_CNOC 0
32
+
#define MASTER_QDSS_DAP 1
33
+
#define SLAVE_CNOC_A2NOC 2
34
+
#define SLAVE_MPM 3
35
+
#define SLAVE_PMIC_ARB 4
36
+
#define SLAVE_TLMM_NORTH 5
37
+
#define SLAVE_TCSR 6
38
+
#define SLAVE_PIMEM_CFG 7
39
+
#define SLAVE_IMEM_CFG 8
40
+
#define SLAVE_MESSAGE_RAM 9
41
+
#define SLAVE_GLM 10
42
+
#define SLAVE_BIMC_CFG 11
43
+
#define SLAVE_PRNG 12
44
+
#define SLAVE_SPDM 13
45
+
#define SLAVE_QDSS_CFG 14
46
+
#define SLAVE_CNOC_MNOC_CFG 15
47
+
#define SLAVE_SNOC_CFG 16
48
+
#define SLAVE_QM_CFG 17
49
+
#define SLAVE_CLK_CTL 18
50
+
#define SLAVE_MSS_CFG 19
51
+
#define SLAVE_TLMM_SOUTH 20
52
+
#define SLAVE_UFS_CFG 21
53
+
#define SLAVE_A2NOC_CFG 22
54
+
#define SLAVE_A2NOC_SMMU_CFG 23
55
+
#define SLAVE_GPUSS_CFG 24
56
+
#define SLAVE_AHB2PHY 25
57
+
#define SLAVE_BLSP_1 26
58
+
#define SLAVE_SDCC_1 27
59
+
#define SLAVE_SDCC_2 28
60
+
#define SLAVE_TLMM_CENTER 29
61
+
#define SLAVE_BLSP_2 30
62
+
#define SLAVE_PDM 31
63
+
#define SLAVE_CNOC_MNOC_MMSS_CFG 32
64
+
#define SLAVE_USB_HS 33
65
+
#define SLAVE_USB3_0 34
66
+
#define SLAVE_SRVC_CNOC 35
67
+
68
+
/* GNOC */
69
+
#define MASTER_APSS_PROC 0
70
+
#define SLAVE_GNOC_BIMC 1
71
+
#define SLAVE_GNOC_SNOC 2
72
+
73
+
/* MNOC */
74
+
#define MASTER_CPP 0
75
+
#define MASTER_JPEG 1
76
+
#define MASTER_MDP_P0 2
77
+
#define MASTER_MDP_P1 3
78
+
#define MASTER_VENUS 4
79
+
#define MASTER_VFE 5
80
+
#define SLAVE_MNOC_BIMC 6
81
+
#define MASTER_CNOC_MNOC_MMSS_CFG 7
82
+
#define MASTER_CNOC_MNOC_CFG 8
83
+
#define SLAVE_CAMERA_CFG 9
84
+
#define SLAVE_CAMERA_THROTTLE_CFG 10
85
+
#define SLAVE_MISC_CFG 11
86
+
#define SLAVE_VENUS_THROTTLE_CFG 12
87
+
#define SLAVE_VENUS_CFG 13
88
+
#define SLAVE_MMSS_CLK_XPU_CFG 14
89
+
#define SLAVE_MMSS_CLK_CFG 15
90
+
#define SLAVE_MNOC_MPU_CFG 16
91
+
#define SLAVE_DISPLAY_CFG 17
92
+
#define SLAVE_CSI_PHY_CFG 18
93
+
#define SLAVE_DISPLAY_THROTTLE_CFG 19
94
+
#define SLAVE_SMMU_CFG 20
95
+
#define SLAVE_SRVC_MNOC 21
96
+
97
+
/* SNOC */
98
+
#define MASTER_QDSS_ETR 0
99
+
#define MASTER_QDSS_BAM 1
100
+
#define MASTER_SNOC_CFG 2
101
+
#define MASTER_BIMC_SNOC 3
102
+
#define MASTER_A2NOC_SNOC 4
103
+
#define MASTER_GNOC_SNOC 5
104
+
#define SLAVE_HMSS 6
105
+
#define SLAVE_LPASS 7
106
+
#define SLAVE_WLAN 8
107
+
#define SLAVE_CDSP 9
108
+
#define SLAVE_IPA 10
109
+
#define SLAVE_SNOC_BIMC 11
110
+
#define SLAVE_SNOC_CNOC 12
111
+
#define SLAVE_IMEM 13
112
+
#define SLAVE_PIMEM 14
113
+
#define SLAVE_QDSS_STM 15
114
+
#define SLAVE_SRVC_SNOC 16
115
+
116
+
#endif
+172
include/dt-bindings/interconnect/qcom,sm8350.h
+172
include/dt-bindings/interconnect/qcom,sm8350.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Qualcomm SM8350 interconnect IDs
4
+
*
5
+
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6
+
* Copyright (c) 2021, Linaro Limited
7
+
*/
8
+
9
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H
10
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H
11
+
12
+
#define MASTER_QSPI_0 0
13
+
#define MASTER_QUP_1 1
14
+
#define MASTER_A1NOC_CFG 2
15
+
#define MASTER_SDCC_4 3
16
+
#define MASTER_UFS_MEM 4
17
+
#define MASTER_USB3_0 5
18
+
#define MASTER_USB3_1 6
19
+
#define SLAVE_A1NOC_SNOC 7
20
+
#define SLAVE_SERVICE_A1NOC 8
21
+
22
+
#define MASTER_QDSS_BAM 0
23
+
#define MASTER_QUP_0 1
24
+
#define MASTER_QUP_2 2
25
+
#define MASTER_A2NOC_CFG 3
26
+
#define MASTER_CRYPTO 4
27
+
#define MASTER_IPA 5
28
+
#define MASTER_PCIE_0 6
29
+
#define MASTER_PCIE_1 7
30
+
#define MASTER_QDSS_ETR 8
31
+
#define MASTER_SDCC_2 9
32
+
#define MASTER_UFS_CARD 10
33
+
#define SLAVE_A2NOC_SNOC 11
34
+
#define SLAVE_ANOC_PCIE_GEM_NOC 12
35
+
#define SLAVE_SERVICE_A2NOC 13
36
+
37
+
#define MASTER_GEM_NOC_CNOC 0
38
+
#define MASTER_GEM_NOC_PCIE_SNOC 1
39
+
#define MASTER_QDSS_DAP 2
40
+
#define SLAVE_AHB2PHY_SOUTH 3
41
+
#define SLAVE_AHB2PHY_NORTH 4
42
+
#define SLAVE_AOSS 5
43
+
#define SLAVE_APPSS 6
44
+
#define SLAVE_CAMERA_CFG 7
45
+
#define SLAVE_CLK_CTL 8
46
+
#define SLAVE_CDSP_CFG 9
47
+
#define SLAVE_RBCPR_CX_CFG 10
48
+
#define SLAVE_RBCPR_MMCX_CFG 11
49
+
#define SLAVE_RBCPR_MX_CFG 12
50
+
#define SLAVE_CRYPTO_0_CFG 13
51
+
#define SLAVE_CX_RDPM 14
52
+
#define SLAVE_DCC_CFG 15
53
+
#define SLAVE_DISPLAY_CFG 16
54
+
#define SLAVE_GFX3D_CFG 17
55
+
#define SLAVE_HWKM 18
56
+
#define SLAVE_IMEM_CFG 19
57
+
#define SLAVE_IPA_CFG 20
58
+
#define SLAVE_IPC_ROUTER_CFG 21
59
+
#define SLAVE_LPASS 22
60
+
#define SLAVE_CNOC_MSS 23
61
+
#define SLAVE_MX_RDPM 24
62
+
#define SLAVE_PCIE_0_CFG 25
63
+
#define SLAVE_PCIE_1_CFG 26
64
+
#define SLAVE_PDM 27
65
+
#define SLAVE_PIMEM_CFG 28
66
+
#define SLAVE_PKA_WRAPPER_CFG 29
67
+
#define SLAVE_PMU_WRAPPER_CFG 30
68
+
#define SLAVE_QDSS_CFG 31
69
+
#define SLAVE_QSPI_0 32
70
+
#define SLAVE_QUP_0 33
71
+
#define SLAVE_QUP_1 34
72
+
#define SLAVE_QUP_2 35
73
+
#define SLAVE_SDCC_2 36
74
+
#define SLAVE_SDCC_4 37
75
+
#define SLAVE_SECURITY 38
76
+
#define SLAVE_SPSS_CFG 39
77
+
#define SLAVE_TCSR 40
78
+
#define SLAVE_TLMM 41
79
+
#define SLAVE_UFS_CARD_CFG 42
80
+
#define SLAVE_UFS_MEM_CFG 43
81
+
#define SLAVE_USB3_0 44
82
+
#define SLAVE_USB3_1 45
83
+
#define SLAVE_VENUS_CFG 46
84
+
#define SLAVE_VSENSE_CTRL_CFG 47
85
+
#define SLAVE_A1NOC_CFG 48
86
+
#define SLAVE_A2NOC_CFG 49
87
+
#define SLAVE_DDRSS_CFG 50
88
+
#define SLAVE_CNOC_MNOC_CFG 51
89
+
#define SLAVE_SNOC_CFG 52
90
+
#define SLAVE_BOOT_IMEM 53
91
+
#define SLAVE_IMEM 54
92
+
#define SLAVE_PIMEM 55
93
+
#define SLAVE_SERVICE_CNOC 56
94
+
#define SLAVE_PCIE_0 57
95
+
#define SLAVE_PCIE_1 58
96
+
#define SLAVE_QDSS_STM 59
97
+
#define SLAVE_TCU 60
98
+
99
+
#define MASTER_CNOC_DC_NOC 0
100
+
#define SLAVE_LLCC_CFG 1
101
+
#define SLAVE_GEM_NOC_CFG 2
102
+
103
+
#define MASTER_GPU_TCU 0
104
+
#define MASTER_SYS_TCU 1
105
+
#define MASTER_APPSS_PROC 2
106
+
#define MASTER_COMPUTE_NOC 3
107
+
#define MASTER_GEM_NOC_CFG 4
108
+
#define MASTER_GFX3D 5
109
+
#define MASTER_MNOC_HF_MEM_NOC 6
110
+
#define MASTER_MNOC_SF_MEM_NOC 7
111
+
#define MASTER_ANOC_PCIE_GEM_NOC 8
112
+
#define MASTER_SNOC_GC_MEM_NOC 9
113
+
#define MASTER_SNOC_SF_MEM_NOC 10
114
+
#define SLAVE_MSS_PROC_MS_MPU_CFG 11
115
+
#define SLAVE_MCDMA_MS_MPU_CFG 12
116
+
#define SLAVE_GEM_NOC_CNOC 13
117
+
#define SLAVE_LLCC 14
118
+
#define SLAVE_MEM_NOC_PCIE_SNOC 15
119
+
#define SLAVE_SERVICE_GEM_NOC_1 16
120
+
#define SLAVE_SERVICE_GEM_NOC_2 17
121
+
#define SLAVE_SERVICE_GEM_NOC 18
122
+
#define MASTER_MNOC_HF_MEM_NOC_DISP 19
123
+
#define MASTER_MNOC_SF_MEM_NOC_DISP 20
124
+
#define SLAVE_LLCC_DISP 21
125
+
126
+
#define MASTER_CNOC_LPASS_AG_NOC 0
127
+
#define SLAVE_LPASS_CORE_CFG 1
128
+
#define SLAVE_LPASS_LPI_CFG 2
129
+
#define SLAVE_LPASS_MPU_CFG 3
130
+
#define SLAVE_LPASS_TOP_CFG 4
131
+
#define SLAVE_SERVICES_LPASS_AML_NOC 5
132
+
#define SLAVE_SERVICE_LPASS_AG_NOC 6
133
+
134
+
#define MASTER_LLCC 0
135
+
#define SLAVE_EBI1 1
136
+
#define MASTER_LLCC_DISP 2
137
+
#define SLAVE_EBI1_DISP 3
138
+
139
+
#define MASTER_CAMNOC_HF 0
140
+
#define MASTER_CAMNOC_ICP 1
141
+
#define MASTER_CAMNOC_SF 2
142
+
#define MASTER_CNOC_MNOC_CFG 3
143
+
#define MASTER_VIDEO_P0 4
144
+
#define MASTER_VIDEO_P1 5
145
+
#define MASTER_VIDEO_PROC 6
146
+
#define MASTER_MDP0 7
147
+
#define MASTER_MDP1 8
148
+
#define MASTER_ROTATOR 9
149
+
#define SLAVE_MNOC_HF_MEM_NOC 10
150
+
#define SLAVE_MNOC_SF_MEM_NOC 11
151
+
#define SLAVE_SERVICE_MNOC 12
152
+
#define MASTER_MDP0_DISP 13
153
+
#define MASTER_MDP1_DISP 14
154
+
#define MASTER_ROTATOR_DISP 15
155
+
#define SLAVE_MNOC_HF_MEM_NOC_DISP 16
156
+
#define SLAVE_MNOC_SF_MEM_NOC_DISP 17
157
+
158
+
#define MASTER_CDSP_NOC_CFG 0
159
+
#define MASTER_CDSP_PROC 1
160
+
#define SLAVE_CDSP_MEM_NOC 2
161
+
#define SLAVE_SERVICE_NSP_NOC 3
162
+
163
+
#define MASTER_A1NOC_SNOC 0
164
+
#define MASTER_A2NOC_SNOC 1
165
+
#define MASTER_SNOC_CFG 2
166
+
#define MASTER_PIMEM 3
167
+
#define MASTER_GIC 4
168
+
#define SLAVE_SNOC_GEM_NOC_GC 5
169
+
#define SLAVE_SNOC_GEM_NOC_SF 6
170
+
#define SLAVE_SERVICE_SNOC 7
171
+
172
+
#endif