tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: hix5hd2: add I2C clocks
hix5hd2 add I2C clocks (I2C0~i2C5)
Signed-off-by: Wei Yan <sledge.yanwei@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+37
+25
drivers/clk/hisilicon/clk-hix5hd2.c
+25
drivers/clk/hisilicon/clk-hix5hd2.c
···
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CLK_SET_RATE_PARENT, 0x178, 0, 0, },
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{ HIX5HD2_WDG0_RST, "rst_wdg0", "clk_wdg0",
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CLK_SET_RATE_PARENT, 0x178, 4, CLK_GATE_SET_TO_DISABLE, },
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+
/* I2C */
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{HIX5HD2_I2C0_CLK, "clk_i2c0", "100m",
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CLK_SET_RATE_PARENT, 0x06c, 4, 0, },
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{HIX5HD2_I2C0_RST, "rst_i2c0", "clk_i2c0",
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CLK_SET_RATE_PARENT, 0x06c, 5, CLK_GATE_SET_TO_DISABLE, },
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{HIX5HD2_I2C1_CLK, "clk_i2c1", "100m",
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CLK_SET_RATE_PARENT, 0x06c, 8, 0, },
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{HIX5HD2_I2C1_RST, "rst_i2c1", "clk_i2c1",
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CLK_SET_RATE_PARENT, 0x06c, 9, CLK_GATE_SET_TO_DISABLE, },
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{HIX5HD2_I2C2_CLK, "clk_i2c2", "100m",
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CLK_SET_RATE_PARENT, 0x06c, 12, 0, },
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{HIX5HD2_I2C2_RST, "rst_i2c2", "clk_i2c2",
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CLK_SET_RATE_PARENT, 0x06c, 13, CLK_GATE_SET_TO_DISABLE, },
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{HIX5HD2_I2C3_CLK, "clk_i2c3", "100m",
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CLK_SET_RATE_PARENT, 0x06c, 16, 0, },
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{HIX5HD2_I2C3_RST, "rst_i2c3", "clk_i2c3",
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CLK_SET_RATE_PARENT, 0x06c, 17, CLK_GATE_SET_TO_DISABLE, },
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{HIX5HD2_I2C4_CLK, "clk_i2c4", "100m",
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CLK_SET_RATE_PARENT, 0x06c, 20, 0, },
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{HIX5HD2_I2C4_RST, "rst_i2c4", "clk_i2c4",
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CLK_SET_RATE_PARENT, 0x06c, 21, CLK_GATE_SET_TO_DISABLE, },
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{HIX5HD2_I2C5_CLK, "clk_i2c5", "100m",
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CLK_SET_RATE_PARENT, 0x06c, 0, 0, },
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{HIX5HD2_I2C5_RST, "rst_i2c5", "clk_i2c5",
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CLK_SET_RATE_PARENT, 0x06c, 1, CLK_GATE_SET_TO_DISABLE, },
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};
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enum hix5hd2_clk_type {
+12
include/dt-bindings/clock/hix5hd2-clock.h
+12
include/dt-bindings/clock/hix5hd2-clock.h
···
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#define HIX5HD2_SD_CIU_RST 138
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#define HIX5HD2_WDG0_CLK 139
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#define HIX5HD2_WDG0_RST 140
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#define HIX5HD2_I2C0_CLK 141
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#define HIX5HD2_I2C0_RST 142
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#define HIX5HD2_I2C1_CLK 143
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#define HIX5HD2_I2C1_RST 144
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#define HIX5HD2_I2C2_CLK 145
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#define HIX5HD2_I2C2_RST 146
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#define HIX5HD2_I2C3_CLK 147
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#define HIX5HD2_I2C3_RST 148
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#define HIX5HD2_I2C4_CLK 149
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#define HIX5HD2_I2C4_RST 150
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#define HIX5HD2_I2C5_CLK 151
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#define HIX5HD2_I2C5_RST 152
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/* complex */
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#define HIX5HD2_MAC0_CLK 192