mfd: palmas: Format the header file · tjh.dev/kernel@45ac60c

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

mfd: palmas: Format the header file

Formats the palmas header file. Convert all
the offset values to hexadecimal.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

authored by

Keerthy and committed by

Lee Jones 12 years ago 45ac60c0 a22c514c

+1083 -1083

1 changed file

expand all

include

linux

mfd

palmas.h

+1083 -1083

include/linux/mfd/palmas.h

··· 482 482 483 483 /* helper macro to get correct slave number */ 484 484 #define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) 485 - #define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y) 485 + #define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y) 486 486 487 487 /* Base addresses of IP blocks in Palmas */ 488 - #define PALMAS_SMPS_DVS_BASE 0x20 488 + #define PALMAS_SMPS_DVS_BASE 0x020 489 489 #define PALMAS_RTC_BASE 0x100 490 490 #define PALMAS_VALIDITY_BASE 0x118 491 491 #define PALMAS_SMPS_BASE 0x120 ··· 504 504 #define PALMAS_TRIM_GPADC_BASE 0x3CD 505 505 506 506 /* Registers for function RTC */ 507 - #define PALMAS_SECONDS_REG 0x0 508 - #define PALMAS_MINUTES_REG 0x1 509 - #define PALMAS_HOURS_REG 0x2 510 - #define PALMAS_DAYS_REG 0x3 511 - #define PALMAS_MONTHS_REG 0x4 512 - #define PALMAS_YEARS_REG 0x5 513 - #define PALMAS_WEEKS_REG 0x6 514 - #define PALMAS_ALARM_SECONDS_REG 0x8 515 - #define PALMAS_ALARM_MINUTES_REG 0x9 516 - #define PALMAS_ALARM_HOURS_REG 0xA 517 - #define PALMAS_ALARM_DAYS_REG 0xB 518 - #define PALMAS_ALARM_MONTHS_REG 0xC 519 - #define PALMAS_ALARM_YEARS_REG 0xD 507 + #define PALMAS_SECONDS_REG 0x00 508 + #define PALMAS_MINUTES_REG 0x01 509 + #define PALMAS_HOURS_REG 0x02 510 + #define PALMAS_DAYS_REG 0x03 511 + #define PALMAS_MONTHS_REG 0x04 512 + #define PALMAS_YEARS_REG 0x05 513 + #define PALMAS_WEEKS_REG 0x06 514 + #define PALMAS_ALARM_SECONDS_REG 0x08 515 + #define PALMAS_ALARM_MINUTES_REG 0x09 516 + #define PALMAS_ALARM_HOURS_REG 0x0A 517 + #define PALMAS_ALARM_DAYS_REG 0x0B 518 + #define PALMAS_ALARM_MONTHS_REG 0x0C 519 + #define PALMAS_ALARM_YEARS_REG 0x0D 520 520 #define PALMAS_RTC_CTRL_REG 0x10 521 521 #define PALMAS_RTC_STATUS_REG 0x11 522 522 #define PALMAS_RTC_INTERRUPTS_REG 0x12 ··· 527 527 528 528 /* Bit definitions for SECONDS_REG */ 529 529 #define PALMAS_SECONDS_REG_SEC1_MASK 0x70 530 - #define PALMAS_SECONDS_REG_SEC1_SHIFT 4 531 - #define PALMAS_SECONDS_REG_SEC0_MASK 0x0f 532 - #define PALMAS_SECONDS_REG_SEC0_SHIFT 0 530 + #define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04 531 + #define PALMAS_SECONDS_REG_SEC0_MASK 0x0F 532 + #define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00 533 533 534 534 /* Bit definitions for MINUTES_REG */ 535 535 #define PALMAS_MINUTES_REG_MIN1_MASK 0x70 536 - #define PALMAS_MINUTES_REG_MIN1_SHIFT 4 537 - #define PALMAS_MINUTES_REG_MIN0_MASK 0x0f 538 - #define PALMAS_MINUTES_REG_MIN0_SHIFT 0 536 + #define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04 537 + #define PALMAS_MINUTES_REG_MIN0_MASK 0x0F 538 + #define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00 539 539 540 540 /* Bit definitions for HOURS_REG */ 541 541 #define PALMAS_HOURS_REG_PM_NAM 0x80 542 - #define PALMAS_HOURS_REG_PM_NAM_SHIFT 7 542 + #define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07 543 543 #define PALMAS_HOURS_REG_HOUR1_MASK 0x30 544 - #define PALMAS_HOURS_REG_HOUR1_SHIFT 4 545 - #define PALMAS_HOURS_REG_HOUR0_MASK 0x0f 546 - #define PALMAS_HOURS_REG_HOUR0_SHIFT 0 544 + #define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04 545 + #define PALMAS_HOURS_REG_HOUR0_MASK 0x0F 546 + #define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00 547 547 548 548 /* Bit definitions for DAYS_REG */ 549 549 #define PALMAS_DAYS_REG_DAY1_MASK 0x30 550 - #define PALMAS_DAYS_REG_DAY1_SHIFT 4 551 - #define PALMAS_DAYS_REG_DAY0_MASK 0x0f 552 - #define PALMAS_DAYS_REG_DAY0_SHIFT 0 550 + #define PALMAS_DAYS_REG_DAY1_SHIFT 0x04 551 + #define PALMAS_DAYS_REG_DAY0_MASK 0x0F 552 + #define PALMAS_DAYS_REG_DAY0_SHIFT 0x00 553 553 554 554 /* Bit definitions for MONTHS_REG */ 555 555 #define PALMAS_MONTHS_REG_MONTH1 0x10 556 - #define PALMAS_MONTHS_REG_MONTH1_SHIFT 4 557 - #define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f 558 - #define PALMAS_MONTHS_REG_MONTH0_SHIFT 0 556 + #define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04 557 + #define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F 558 + #define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00 559 559 560 560 /* Bit definitions for YEARS_REG */ 561 561 #define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 562 - #define PALMAS_YEARS_REG_YEAR1_SHIFT 4 563 - #define PALMAS_YEARS_REG_YEAR0_MASK 0x0f 564 - #define PALMAS_YEARS_REG_YEAR0_SHIFT 0 562 + #define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04 563 + #define PALMAS_YEARS_REG_YEAR0_MASK 0x0F 564 + #define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00 565 565 566 566 /* Bit definitions for WEEKS_REG */ 567 567 #define PALMAS_WEEKS_REG_WEEK_MASK 0x07 568 - #define PALMAS_WEEKS_REG_WEEK_SHIFT 0 568 + #define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00 569 569 570 570 /* Bit definitions for ALARM_SECONDS_REG */ 571 571 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 572 - #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4 573 - #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f 574 - #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0 572 + #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04 573 + #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F 574 + #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00 575 575 576 576 /* Bit definitions for ALARM_MINUTES_REG */ 577 577 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 578 - #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4 579 - #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f 580 - #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0 578 + #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04 579 + #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F 580 + #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00 581 581 582 582 /* Bit definitions for ALARM_HOURS_REG */ 583 583 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 584 - #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7 584 + #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07 585 585 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 586 - #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4 587 - #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f 588 - #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0 586 + #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04 587 + #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F 588 + #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00 589 589 590 590 /* Bit definitions for ALARM_DAYS_REG */ 591 591 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 592 - #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4 593 - #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f 594 - #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0 592 + #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04 593 + #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F 594 + #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00 595 595 596 596 /* Bit definitions for ALARM_MONTHS_REG */ 597 597 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 598 - #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4 599 - #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f 600 - #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0 598 + #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04 599 + #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F 600 + #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00 601 601 602 602 /* Bit definitions for ALARM_YEARS_REG */ 603 603 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 604 - #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4 605 - #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f 606 - #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0 604 + #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04 605 + #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F 606 + #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00 607 607 608 608 /* Bit definitions for RTC_CTRL_REG */ 609 609 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 610 - #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7 610 + #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07 611 611 #define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 612 - #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6 612 + #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06 613 613 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 614 - #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5 614 + #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05 615 615 #define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 616 - #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4 616 + #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04 617 617 #define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 618 - #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3 618 + #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03 619 619 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 620 - #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2 620 + #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02 621 621 #define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 622 - #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1 622 + #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01 623 623 #define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 624 - #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0 624 + #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00 625 625 626 626 /* Bit definitions for RTC_STATUS_REG */ 627 627 #define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 628 - #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7 628 + #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07 629 629 #define PALMAS_RTC_STATUS_REG_ALARM 0x40 630 - #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6 630 + #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06 631 631 #define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 632 - #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5 632 + #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05 633 633 #define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 634 - #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4 634 + #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04 635 635 #define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 636 - #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3 636 + #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03 637 637 #define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 638 - #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2 638 + #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02 639 639 #define PALMAS_RTC_STATUS_REG_RUN 0x02 640 - #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1 640 + #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01 641 641 642 642 /* Bit definitions for RTC_INTERRUPTS_REG */ 643 643 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 644 - #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4 644 + #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04 645 645 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 646 - #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3 646 + #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03 647 647 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 648 - #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2 648 + #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02 649 649 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 650 - #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0 650 + #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00 651 651 652 652 /* Bit definitions for RTC_COMP_LSB_REG */ 653 - #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff 654 - #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0 653 + #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF 654 + #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00 655 655 656 656 /* Bit definitions for RTC_COMP_MSB_REG */ 657 - #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff 658 - #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0 657 + #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF 658 + #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00 659 659 660 660 /* Bit definitions for RTC_RES_PROG_REG */ 661 - #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f 662 - #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0 661 + #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F 662 + #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00 663 663 664 664 /* Bit definitions for RTC_RESET_STATUS_REG */ 665 665 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 666 - #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0 666 + #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00 667 667 668 668 /* Registers for function BACKUP */ 669 - #define PALMAS_BACKUP0 0x0 670 - #define PALMAS_BACKUP1 0x1 671 - #define PALMAS_BACKUP2 0x2 672 - #define PALMAS_BACKUP3 0x3 673 - #define PALMAS_BACKUP4 0x4 674 - #define PALMAS_BACKUP5 0x5 675 - #define PALMAS_BACKUP6 0x6 676 - #define PALMAS_BACKUP7 0x7 669 + #define PALMAS_BACKUP0 0x00 670 + #define PALMAS_BACKUP1 0x01 671 + #define PALMAS_BACKUP2 0x02 672 + #define PALMAS_BACKUP3 0x03 673 + #define PALMAS_BACKUP4 0x04 674 + #define PALMAS_BACKUP5 0x05 675 + #define PALMAS_BACKUP6 0x06 676 + #define PALMAS_BACKUP7 0x07 677 677 678 678 /* Bit definitions for BACKUP0 */ 679 - #define PALMAS_BACKUP0_BACKUP_MASK 0xff 680 - #define PALMAS_BACKUP0_BACKUP_SHIFT 0 679 + #define PALMAS_BACKUP0_BACKUP_MASK 0xFF 680 + #define PALMAS_BACKUP0_BACKUP_SHIFT 0x00 681 681 682 682 /* Bit definitions for BACKUP1 */ 683 - #define PALMAS_BACKUP1_BACKUP_MASK 0xff 684 - #define PALMAS_BACKUP1_BACKUP_SHIFT 0 683 + #define PALMAS_BACKUP1_BACKUP_MASK 0xFF 684 + #define PALMAS_BACKUP1_BACKUP_SHIFT 0x00 685 685 686 686 /* Bit definitions for BACKUP2 */ 687 - #define PALMAS_BACKUP2_BACKUP_MASK 0xff 688 - #define PALMAS_BACKUP2_BACKUP_SHIFT 0 687 + #define PALMAS_BACKUP2_BACKUP_MASK 0xFF 688 + #define PALMAS_BACKUP2_BACKUP_SHIFT 0x00 689 689 690 690 /* Bit definitions for BACKUP3 */ 691 - #define PALMAS_BACKUP3_BACKUP_MASK 0xff 692 - #define PALMAS_BACKUP3_BACKUP_SHIFT 0 691 + #define PALMAS_BACKUP3_BACKUP_MASK 0xFF 692 + #define PALMAS_BACKUP3_BACKUP_SHIFT 0x00 693 693 694 694 /* Bit definitions for BACKUP4 */ 695 - #define PALMAS_BACKUP4_BACKUP_MASK 0xff 696 - #define PALMAS_BACKUP4_BACKUP_SHIFT 0 695 + #define PALMAS_BACKUP4_BACKUP_MASK 0xFF 696 + #define PALMAS_BACKUP4_BACKUP_SHIFT 0x00 697 697 698 698 /* Bit definitions for BACKUP5 */ 699 - #define PALMAS_BACKUP5_BACKUP_MASK 0xff 700 - #define PALMAS_BACKUP5_BACKUP_SHIFT 0 699 + #define PALMAS_BACKUP5_BACKUP_MASK 0xFF 700 + #define PALMAS_BACKUP5_BACKUP_SHIFT 0x00 701 701 702 702 /* Bit definitions for BACKUP6 */ 703 - #define PALMAS_BACKUP6_BACKUP_MASK 0xff 704 - #define PALMAS_BACKUP6_BACKUP_SHIFT 0 703 + #define PALMAS_BACKUP6_BACKUP_MASK 0xFF 704 + #define PALMAS_BACKUP6_BACKUP_SHIFT 0x00 705 705 706 706 /* Bit definitions for BACKUP7 */ 707 - #define PALMAS_BACKUP7_BACKUP_MASK 0xff 708 - #define PALMAS_BACKUP7_BACKUP_SHIFT 0 707 + #define PALMAS_BACKUP7_BACKUP_MASK 0xFF 708 + #define PALMAS_BACKUP7_BACKUP_SHIFT 0x00 709 709 710 710 /* Registers for function SMPS */ 711 - #define PALMAS_SMPS12_CTRL 0x0 712 - #define PALMAS_SMPS12_TSTEP 0x1 713 - #define PALMAS_SMPS12_FORCE 0x2 714 - #define PALMAS_SMPS12_VOLTAGE 0x3 715 - #define PALMAS_SMPS3_CTRL 0x4 716 - #define PALMAS_SMPS3_VOLTAGE 0x7 717 - #define PALMAS_SMPS45_CTRL 0x8 718 - #define PALMAS_SMPS45_TSTEP 0x9 719 - #define PALMAS_SMPS45_FORCE 0xA 720 - #define PALMAS_SMPS45_VOLTAGE 0xB 721 - #define PALMAS_SMPS6_CTRL 0xC 722 - #define PALMAS_SMPS6_TSTEP 0xD 723 - #define PALMAS_SMPS6_FORCE 0xE 724 - #define PALMAS_SMPS6_VOLTAGE 0xF 711 + #define PALMAS_SMPS12_CTRL 0x00 712 + #define PALMAS_SMPS12_TSTEP 0x01 713 + #define PALMAS_SMPS12_FORCE 0x02 714 + #define PALMAS_SMPS12_VOLTAGE 0x03 715 + #define PALMAS_SMPS3_CTRL 0x04 716 + #define PALMAS_SMPS3_VOLTAGE 0x07 717 + #define PALMAS_SMPS45_CTRL 0x08 718 + #define PALMAS_SMPS45_TSTEP 0x09 719 + #define PALMAS_SMPS45_FORCE 0x0A 720 + #define PALMAS_SMPS45_VOLTAGE 0x0B 721 + #define PALMAS_SMPS6_CTRL 0x0C 722 + #define PALMAS_SMPS6_TSTEP 0x0D 723 + #define PALMAS_SMPS6_FORCE 0x0E 724 + #define PALMAS_SMPS6_VOLTAGE 0x0F 725 725 #define PALMAS_SMPS7_CTRL 0x10 726 726 #define PALMAS_SMPS7_VOLTAGE 0x13 727 727 #define PALMAS_SMPS8_CTRL 0x14 ··· 744 744 745 745 /* Bit definitions for SMPS12_CTRL */ 746 746 #define PALMAS_SMPS12_CTRL_WR_S 0x80 747 - #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7 747 + #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07 748 748 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 749 - #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6 749 + #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 750 750 #define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 751 - #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4 751 + #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04 752 752 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c 753 - #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2 753 + #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02 754 754 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 755 - #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0 755 + #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00 756 756 757 757 /* Bit definitions for SMPS12_TSTEP */ 758 758 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 759 - #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0 759 + #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00 760 760 761 761 /* Bit definitions for SMPS12_FORCE */ 762 762 #define PALMAS_SMPS12_FORCE_CMD 0x80 763 - #define PALMAS_SMPS12_FORCE_CMD_SHIFT 7 764 - #define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f 765 - #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0 763 + #define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07 764 + #define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F 765 + #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00 766 766 767 767 /* Bit definitions for SMPS12_VOLTAGE */ 768 768 #define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 769 - #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7 770 - #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f 771 - #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0 769 + #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07 770 + #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F 771 + #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00 772 772 773 773 /* Bit definitions for SMPS3_CTRL */ 774 774 #define PALMAS_SMPS3_CTRL_WR_S 0x80 775 - #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7 775 + #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07 776 776 #define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 777 - #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4 777 + #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04 778 778 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c 779 - #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2 779 + #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 780 780 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 781 - #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0 781 + #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 782 782 783 783 /* Bit definitions for SMPS3_VOLTAGE */ 784 784 #define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 785 - #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7 786 - #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f 787 - #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0 785 + #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 786 + #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F 787 + #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 788 788 789 789 /* Bit definitions for SMPS45_CTRL */ 790 790 #define PALMAS_SMPS45_CTRL_WR_S 0x80 791 - #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7 791 + #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07 792 792 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 793 - #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6 793 + #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 794 794 #define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 795 - #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4 795 + #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04 796 796 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c 797 - #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2 797 + #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02 798 798 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 799 - #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0 799 + #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00 800 800 801 801 /* Bit definitions for SMPS45_TSTEP */ 802 802 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 803 - #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0 803 + #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00 804 804 805 805 /* Bit definitions for SMPS45_FORCE */ 806 806 #define PALMAS_SMPS45_FORCE_CMD 0x80 807 - #define PALMAS_SMPS45_FORCE_CMD_SHIFT 7 808 - #define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f 809 - #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0 807 + #define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07 808 + #define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F 809 + #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00 810 810 811 811 /* Bit definitions for SMPS45_VOLTAGE */ 812 812 #define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 813 - #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7 814 - #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f 815 - #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0 813 + #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07 814 + #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F 815 + #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00 816 816 817 817 /* Bit definitions for SMPS6_CTRL */ 818 818 #define PALMAS_SMPS6_CTRL_WR_S 0x80 819 - #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7 819 + #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07 820 820 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 821 - #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6 821 + #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 822 822 #define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 823 - #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4 823 + #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04 824 824 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c 825 - #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2 825 + #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02 826 826 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 827 - #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0 827 + #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00 828 828 829 829 /* Bit definitions for SMPS6_TSTEP */ 830 830 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 831 - #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0 831 + #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00 832 832 833 833 /* Bit definitions for SMPS6_FORCE */ 834 834 #define PALMAS_SMPS6_FORCE_CMD 0x80 835 - #define PALMAS_SMPS6_FORCE_CMD_SHIFT 7 836 - #define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f 837 - #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0 835 + #define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07 836 + #define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F 837 + #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00 838 838 839 839 /* Bit definitions for SMPS6_VOLTAGE */ 840 840 #define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 841 - #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7 842 - #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f 843 - #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0 841 + #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07 842 + #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F 843 + #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00 844 844 845 845 /* Bit definitions for SMPS7_CTRL */ 846 846 #define PALMAS_SMPS7_CTRL_WR_S 0x80 847 - #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7 847 + #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07 848 848 #define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 849 - #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4 849 + #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04 850 850 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c 851 - #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2 851 + #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02 852 852 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 853 - #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0 853 + #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00 854 854 855 855 /* Bit definitions for SMPS7_VOLTAGE */ 856 856 #define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 857 - #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7 858 - #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f 859 - #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0 857 + #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07 858 + #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F 859 + #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00 860 860 861 861 /* Bit definitions for SMPS8_CTRL */ 862 862 #define PALMAS_SMPS8_CTRL_WR_S 0x80 863 - #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7 863 + #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07 864 864 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 865 - #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6 865 + #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 866 866 #define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 867 - #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4 867 + #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04 868 868 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c 869 - #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2 869 + #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02 870 870 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 871 - #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0 871 + #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00 872 872 873 873 /* Bit definitions for SMPS8_TSTEP */ 874 874 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 875 - #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0 875 + #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00 876 876 877 877 /* Bit definitions for SMPS8_FORCE */ 878 878 #define PALMAS_SMPS8_FORCE_CMD 0x80 879 - #define PALMAS_SMPS8_FORCE_CMD_SHIFT 7 880 - #define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f 881 - #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0 879 + #define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07 880 + #define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F 881 + #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00 882 882 883 883 /* Bit definitions for SMPS8_VOLTAGE */ 884 884 #define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 885 - #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7 886 - #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f 887 - #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0 885 + #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07 886 + #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F 887 + #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00 888 888 889 889 /* Bit definitions for SMPS9_CTRL */ 890 890 #define PALMAS_SMPS9_CTRL_WR_S 0x80 891 - #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7 891 + #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07 892 892 #define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 893 - #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4 893 + #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04 894 894 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c 895 - #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2 895 + #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02 896 896 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 897 - #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0 897 + #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00 898 898 899 899 /* Bit definitions for SMPS9_VOLTAGE */ 900 900 #define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 901 - #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7 902 - #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f 903 - #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0 901 + #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07 902 + #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F 903 + #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00 904 904 905 905 /* Bit definitions for SMPS10_CTRL */ 906 906 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 907 - #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4 908 - #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f 909 - #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0 907 + #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04 908 + #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F 909 + #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00 910 910 911 911 /* Bit definitions for SMPS10_STATUS */ 912 - #define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f 913 - #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0 912 + #define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F 913 + #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00 914 914 915 915 /* Bit definitions for SMPS_CTRL */ 916 916 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 917 - #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5 917 + #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05 918 918 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 919 - #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4 919 + #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04 920 920 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c 921 - #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2 921 + #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02 922 922 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 923 - #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0 923 + #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00 924 924 925 925 /* Bit definitions for SMPS_PD_CTRL */ 926 926 #define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 927 - #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6 927 + #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06 928 928 #define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 929 - #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5 929 + #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05 930 930 #define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 931 - #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4 931 + #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04 932 932 #define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 933 - #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3 933 + #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03 934 934 #define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 935 - #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2 935 + #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02 936 936 #define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 937 - #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1 937 + #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01 938 938 #define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 939 - #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0 939 + #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00 940 940 941 941 /* Bit definitions for SMPS_THERMAL_EN */ 942 942 #define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 943 - #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6 943 + #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06 944 944 #define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 945 - #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5 945 + #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05 946 946 #define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 947 - #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3 947 + #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03 948 948 #define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 949 - #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2 949 + #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02 950 950 #define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 951 - #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0 951 + #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00 952 952 953 953 /* Bit definitions for SMPS_THERMAL_STATUS */ 954 954 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 955 - #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6 955 + #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06 956 956 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 957 - #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5 957 + #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05 958 958 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 959 - #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3 959 + #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03 960 960 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 961 - #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2 961 + #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02 962 962 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 963 - #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0 963 + #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00 964 964 965 965 /* Bit definitions for SMPS_SHORT_STATUS */ 966 966 #define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 967 - #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7 967 + #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07 968 968 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 969 - #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6 969 + #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06 970 970 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 971 - #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5 971 + #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05 972 972 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 973 - #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4 973 + #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04 974 974 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 975 - #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3 975 + #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03 976 976 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 977 - #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2 977 + #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02 978 978 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 979 - #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1 979 + #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01 980 980 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 981 - #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0 981 + #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00 982 982 983 983 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 984 984 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 985 - #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6 985 + #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06 986 986 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 987 - #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5 987 + #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05 988 988 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 989 - #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4 989 + #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04 990 990 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 991 - #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3 991 + #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03 992 992 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 993 - #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2 993 + #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02 994 994 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 995 - #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1 995 + #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01 996 996 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 997 - #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0 997 + #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00 998 998 999 999 /* Bit definitions for SMPS_POWERGOOD_MASK1 */ 1000 1000 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 1001 - #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7 1001 + #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07 1002 1002 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 1003 - #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6 1003 + #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06 1004 1004 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 1005 - #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5 1005 + #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05 1006 1006 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 1007 - #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4 1007 + #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04 1008 1008 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 1009 - #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3 1009 + #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03 1010 1010 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 1011 - #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2 1011 + #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02 1012 1012 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 1013 - #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1 1013 + #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01 1014 1014 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 1015 - #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0 1015 + #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00 1016 1016 1017 1017 /* Bit definitions for SMPS_POWERGOOD_MASK2 */ 1018 1018 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 1019 - #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7 1019 + #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 1020 1020 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 1021 - #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2 1021 + #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02 1022 1022 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 1023 - #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1 1023 + #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01 1024 1024 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 1025 - #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0 1025 + #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00 1026 1026 1027 1027 /* Registers for function LDO */ 1028 - #define PALMAS_LDO1_CTRL 0x0 1029 - #define PALMAS_LDO1_VOLTAGE 0x1 1030 - #define PALMAS_LDO2_CTRL 0x2 1031 - #define PALMAS_LDO2_VOLTAGE 0x3 1032 - #define PALMAS_LDO3_CTRL 0x4 1033 - #define PALMAS_LDO3_VOLTAGE 0x5 1034 - #define PALMAS_LDO4_CTRL 0x6 1035 - #define PALMAS_LDO4_VOLTAGE 0x7 1036 - #define PALMAS_LDO5_CTRL 0x8 1037 - #define PALMAS_LDO5_VOLTAGE 0x9 1038 - #define PALMAS_LDO6_CTRL 0xA 1039 - #define PALMAS_LDO6_VOLTAGE 0xB 1040 - #define PALMAS_LDO7_CTRL 0xC 1041 - #define PALMAS_LDO7_VOLTAGE 0xD 1042 - #define PALMAS_LDO8_CTRL 0xE 1043 - #define PALMAS_LDO8_VOLTAGE 0xF 1028 + #define PALMAS_LDO1_CTRL 0x00 1029 + #define PALMAS_LDO1_VOLTAGE 0x01 1030 + #define PALMAS_LDO2_CTRL 0x02 1031 + #define PALMAS_LDO2_VOLTAGE 0x03 1032 + #define PALMAS_LDO3_CTRL 0x04 1033 + #define PALMAS_LDO3_VOLTAGE 0x05 1034 + #define PALMAS_LDO4_CTRL 0x06 1035 + #define PALMAS_LDO4_VOLTAGE 0x07 1036 + #define PALMAS_LDO5_CTRL 0x08 1037 + #define PALMAS_LDO5_VOLTAGE 0x09 1038 + #define PALMAS_LDO6_CTRL 0x0A 1039 + #define PALMAS_LDO6_VOLTAGE 0x0B 1040 + #define PALMAS_LDO7_CTRL 0x0C 1041 + #define PALMAS_LDO7_VOLTAGE 0x0D 1042 + #define PALMAS_LDO8_CTRL 0x0E 1043 + #define PALMAS_LDO8_VOLTAGE 0x0F 1044 1044 #define PALMAS_LDO9_CTRL 0x10 1045 1045 #define PALMAS_LDO9_VOLTAGE 0x11 1046 1046 #define PALMAS_LDOLN_CTRL 0x12 ··· 1055 1055 1056 1056 /* Bit definitions for LDO1_CTRL */ 1057 1057 #define PALMAS_LDO1_CTRL_WR_S 0x80 1058 - #define PALMAS_LDO1_CTRL_WR_S_SHIFT 7 1058 + #define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07 1059 1059 #define PALMAS_LDO1_CTRL_STATUS 0x10 1060 - #define PALMAS_LDO1_CTRL_STATUS_SHIFT 4 1060 + #define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04 1061 1061 #define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 1062 - #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2 1062 + #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 1063 1063 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 1064 - #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0 1064 + #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 1065 1065 1066 1066 /* Bit definitions for LDO1_VOLTAGE */ 1067 - #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f 1068 - #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0 1067 + #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F 1068 + #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00 1069 1069 1070 1070 /* Bit definitions for LDO2_CTRL */ 1071 1071 #define PALMAS_LDO2_CTRL_WR_S 0x80 1072 - #define PALMAS_LDO2_CTRL_WR_S_SHIFT 7 1072 + #define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07 1073 1073 #define PALMAS_LDO2_CTRL_STATUS 0x10 1074 - #define PALMAS_LDO2_CTRL_STATUS_SHIFT 4 1074 + #define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04 1075 1075 #define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 1076 - #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2 1076 + #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 1077 1077 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 1078 - #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0 1078 + #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 1079 1079 1080 1080 /* Bit definitions for LDO2_VOLTAGE */ 1081 - #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f 1082 - #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0 1081 + #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F 1082 + #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00 1083 1083 1084 1084 /* Bit definitions for LDO3_CTRL */ 1085 1085 #define PALMAS_LDO3_CTRL_WR_S 0x80 1086 - #define PALMAS_LDO3_CTRL_WR_S_SHIFT 7 1086 + #define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07 1087 1087 #define PALMAS_LDO3_CTRL_STATUS 0x10 1088 - #define PALMAS_LDO3_CTRL_STATUS_SHIFT 4 1088 + #define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04 1089 1089 #define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 1090 - #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2 1090 + #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 1091 1091 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 1092 - #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0 1092 + #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 1093 1093 1094 1094 /* Bit definitions for LDO3_VOLTAGE */ 1095 - #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f 1096 - #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0 1095 + #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F 1096 + #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00 1097 1097 1098 1098 /* Bit definitions for LDO4_CTRL */ 1099 1099 #define PALMAS_LDO4_CTRL_WR_S 0x80 1100 - #define PALMAS_LDO4_CTRL_WR_S_SHIFT 7 1100 + #define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07 1101 1101 #define PALMAS_LDO4_CTRL_STATUS 0x10 1102 - #define PALMAS_LDO4_CTRL_STATUS_SHIFT 4 1102 + #define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04 1103 1103 #define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 1104 - #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2 1104 + #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 1105 1105 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 1106 - #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0 1106 + #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 1107 1107 1108 1108 /* Bit definitions for LDO4_VOLTAGE */ 1109 - #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f 1110 - #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0 1109 + #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F 1110 + #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00 1111 1111 1112 1112 /* Bit definitions for LDO5_CTRL */ 1113 1113 #define PALMAS_LDO5_CTRL_WR_S 0x80 1114 - #define PALMAS_LDO5_CTRL_WR_S_SHIFT 7 1114 + #define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07 1115 1115 #define PALMAS_LDO5_CTRL_STATUS 0x10 1116 - #define PALMAS_LDO5_CTRL_STATUS_SHIFT 4 1116 + #define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04 1117 1117 #define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 1118 - #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2 1118 + #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 1119 1119 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 1120 - #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0 1120 + #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 1121 1121 1122 1122 /* Bit definitions for LDO5_VOLTAGE */ 1123 - #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f 1124 - #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0 1123 + #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F 1124 + #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00 1125 1125 1126 1126 /* Bit definitions for LDO6_CTRL */ 1127 1127 #define PALMAS_LDO6_CTRL_WR_S 0x80 1128 - #define PALMAS_LDO6_CTRL_WR_S_SHIFT 7 1128 + #define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07 1129 1129 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 1130 - #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6 1130 + #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06 1131 1131 #define PALMAS_LDO6_CTRL_STATUS 0x10 1132 - #define PALMAS_LDO6_CTRL_STATUS_SHIFT 4 1132 + #define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04 1133 1133 #define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 1134 - #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2 1134 + #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02 1135 1135 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 1136 - #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0 1136 + #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00 1137 1137 1138 1138 /* Bit definitions for LDO6_VOLTAGE */ 1139 - #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f 1140 - #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0 1139 + #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F 1140 + #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00 1141 1141 1142 1142 /* Bit definitions for LDO7_CTRL */ 1143 1143 #define PALMAS_LDO7_CTRL_WR_S 0x80 1144 - #define PALMAS_LDO7_CTRL_WR_S_SHIFT 7 1144 + #define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07 1145 1145 #define PALMAS_LDO7_CTRL_STATUS 0x10 1146 - #define PALMAS_LDO7_CTRL_STATUS_SHIFT 4 1146 + #define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04 1147 1147 #define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 1148 - #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2 1148 + #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02 1149 1149 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 1150 - #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0 1150 + #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00 1151 1151 1152 1152 /* Bit definitions for LDO7_VOLTAGE */ 1153 - #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f 1154 - #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0 1153 + #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F 1154 + #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00 1155 1155 1156 1156 /* Bit definitions for LDO8_CTRL */ 1157 1157 #define PALMAS_LDO8_CTRL_WR_S 0x80 1158 - #define PALMAS_LDO8_CTRL_WR_S_SHIFT 7 1158 + #define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07 1159 1159 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 1160 - #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6 1160 + #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06 1161 1161 #define PALMAS_LDO8_CTRL_STATUS 0x10 1162 - #define PALMAS_LDO8_CTRL_STATUS_SHIFT 4 1162 + #define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04 1163 1163 #define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 1164 - #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2 1164 + #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02 1165 1165 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 1166 - #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0 1166 + #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00 1167 1167 1168 1168 /* Bit definitions for LDO8_VOLTAGE */ 1169 - #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f 1170 - #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0 1169 + #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F 1170 + #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00 1171 1171 1172 1172 /* Bit definitions for LDO9_CTRL */ 1173 1173 #define PALMAS_LDO9_CTRL_WR_S 0x80 1174 - #define PALMAS_LDO9_CTRL_WR_S_SHIFT 7 1174 + #define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07 1175 1175 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 1176 - #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6 1176 + #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06 1177 1177 #define PALMAS_LDO9_CTRL_STATUS 0x10 1178 - #define PALMAS_LDO9_CTRL_STATUS_SHIFT 4 1178 + #define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04 1179 1179 #define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 1180 - #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2 1180 + #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02 1181 1181 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 1182 - #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0 1182 + #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00 1183 1183 1184 1184 /* Bit definitions for LDO9_VOLTAGE */ 1185 - #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f 1186 - #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0 1185 + #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F 1186 + #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00 1187 1187 1188 1188 /* Bit definitions for LDOLN_CTRL */ 1189 1189 #define PALMAS_LDOLN_CTRL_WR_S 0x80 1190 - #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7 1190 + #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07 1191 1191 #define PALMAS_LDOLN_CTRL_STATUS 0x10 1192 - #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4 1192 + #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04 1193 1193 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 1194 - #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2 1194 + #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02 1195 1195 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 1196 - #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0 1196 + #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00 1197 1197 1198 1198 /* Bit definitions for LDOLN_VOLTAGE */ 1199 - #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f 1200 - #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0 1199 + #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F 1200 + #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00 1201 1201 1202 1202 /* Bit definitions for LDOUSB_CTRL */ 1203 1203 #define PALMAS_LDOUSB_CTRL_WR_S 0x80 1204 - #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7 1204 + #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07 1205 1205 #define PALMAS_LDOUSB_CTRL_STATUS 0x10 1206 - #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4 1206 + #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04 1207 1207 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 1208 - #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2 1208 + #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02 1209 1209 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 1210 - #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0 1210 + #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00 1211 1211 1212 1212 /* Bit definitions for LDOUSB_VOLTAGE */ 1213 - #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f 1214 - #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0 1213 + #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F 1214 + #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00 1215 1215 1216 1216 /* Bit definitions for LDO_CTRL */ 1217 1217 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 1218 - #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0 1218 + #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00 1219 1219 1220 1220 /* Bit definitions for LDO_PD_CTRL1 */ 1221 1221 #define PALMAS_LDO_PD_CTRL1_LDO8 0x80 1222 - #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7 1222 + #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07 1223 1223 #define PALMAS_LDO_PD_CTRL1_LDO7 0x40 1224 - #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6 1224 + #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06 1225 1225 #define PALMAS_LDO_PD_CTRL1_LDO6 0x20 1226 - #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5 1226 + #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05 1227 1227 #define PALMAS_LDO_PD_CTRL1_LDO5 0x10 1228 - #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4 1228 + #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04 1229 1229 #define PALMAS_LDO_PD_CTRL1_LDO4 0x08 1230 - #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3 1230 + #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03 1231 1231 #define PALMAS_LDO_PD_CTRL1_LDO3 0x04 1232 - #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2 1232 + #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02 1233 1233 #define PALMAS_LDO_PD_CTRL1_LDO2 0x02 1234 - #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1 1234 + #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01 1235 1235 #define PALMAS_LDO_PD_CTRL1_LDO1 0x01 1236 - #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0 1236 + #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00 1237 1237 1238 1238 /* Bit definitions for LDO_PD_CTRL2 */ 1239 1239 #define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 1240 - #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2 1240 + #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02 1241 1241 #define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 1242 - #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1 1242 + #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01 1243 1243 #define PALMAS_LDO_PD_CTRL2_LDO9 0x01 1244 - #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0 1244 + #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00 1245 1245 1246 1246 /* Bit definitions for LDO_SHORT_STATUS1 */ 1247 1247 #define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 1248 - #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7 1248 + #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07 1249 1249 #define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 1250 - #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6 1250 + #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06 1251 1251 #define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 1252 - #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5 1252 + #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05 1253 1253 #define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 1254 - #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4 1254 + #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04 1255 1255 #define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 1256 - #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3 1256 + #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03 1257 1257 #define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 1258 - #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2 1258 + #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02 1259 1259 #define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 1260 - #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1 1260 + #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 1261 1261 #define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 1262 - #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0 1262 + #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 1263 1263 1264 1264 /* Bit definitions for LDO_SHORT_STATUS2 */ 1265 1265 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 1266 - #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3 1266 + #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03 1267 1267 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 1268 - #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2 1268 + #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02 1269 1269 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 1270 - #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1 1270 + #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01 1271 1271 #define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 1272 - #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0 1272 + #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00 1273 1273 1274 1274 /* Registers for function PMU_CONTROL */ 1275 - #define PALMAS_DEV_CTRL 0x0 1276 - #define PALMAS_POWER_CTRL 0x1 1277 - #define PALMAS_VSYS_LO 0x2 1278 - #define PALMAS_VSYS_MON 0x3 1279 - #define PALMAS_VBAT_MON 0x4 1280 - #define PALMAS_WATCHDOG 0x5 1281 - #define PALMAS_BOOT_STATUS 0x6 1282 - #define PALMAS_BATTERY_BOUNCE 0x7 1283 - #define PALMAS_BACKUP_BATTERY_CTRL 0x8 1284 - #define PALMAS_LONG_PRESS_KEY 0x9 1285 - #define PALMAS_OSC_THERM_CTRL 0xA 1286 - #define PALMAS_BATDEBOUNCING 0xB 1287 - #define PALMAS_SWOFF_HWRST 0xF 1275 + #define PALMAS_DEV_CTRL 0x00 1276 + #define PALMAS_POWER_CTRL 0x01 1277 + #define PALMAS_VSYS_LO 0x02 1278 + #define PALMAS_VSYS_MON 0x03 1279 + #define PALMAS_VBAT_MON 0x04 1280 + #define PALMAS_WATCHDOG 0x05 1281 + #define PALMAS_BOOT_STATUS 0x06 1282 + #define PALMAS_BATTERY_BOUNCE 0x07 1283 + #define PALMAS_BACKUP_BATTERY_CTRL 0x08 1284 + #define PALMAS_LONG_PRESS_KEY 0x09 1285 + #define PALMAS_OSC_THERM_CTRL 0x0A 1286 + #define PALMAS_BATDEBOUNCING 0x0B 1287 + #define PALMAS_SWOFF_HWRST 0x0F 1288 1288 #define PALMAS_SWOFF_COLDRST 0x10 1289 1289 #define PALMAS_SWOFF_STATUS 0x11 1290 1290 #define PALMAS_PMU_CONFIG 0x12 ··· 1296 1296 1297 1297 /* Bit definitions for DEV_CTRL */ 1298 1298 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c 1299 - #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2 1299 + #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02 1300 1300 #define PALMAS_DEV_CTRL_SW_RST 0x02 1301 - #define PALMAS_DEV_CTRL_SW_RST_SHIFT 1 1301 + #define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01 1302 1302 #define PALMAS_DEV_CTRL_DEV_ON 0x01 1303 - #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0 1303 + #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00 1304 1304 1305 1305 /* Bit definitions for POWER_CTRL */ 1306 1306 #define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 1307 - #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2 1307 + #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02 1308 1308 #define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 1309 - #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1 1309 + #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01 1310 1310 #define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 1311 - #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0 1311 + #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00 1312 1312 1313 1313 /* Bit definitions for VSYS_LO */ 1314 - #define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f 1315 - #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0 1314 + #define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F 1315 + #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00 1316 1316 1317 1317 /* Bit definitions for VSYS_MON */ 1318 1318 #define PALMAS_VSYS_MON_ENABLE 0x80 1319 - #define PALMAS_VSYS_MON_ENABLE_SHIFT 7 1320 - #define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f 1321 - #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0 1319 + #define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07 1320 + #define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F 1321 + #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00 1322 1322 1323 1323 /* Bit definitions for VBAT_MON */ 1324 1324 #define PALMAS_VBAT_MON_ENABLE 0x80 1325 - #define PALMAS_VBAT_MON_ENABLE_SHIFT 7 1326 - #define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f 1327 - #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0 1325 + #define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07 1326 + #define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F 1327 + #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00 1328 1328 1329 1329 /* Bit definitions for WATCHDOG */ 1330 1330 #define PALMAS_WATCHDOG_LOCK 0x20 1331 - #define PALMAS_WATCHDOG_LOCK_SHIFT 5 1331 + #define PALMAS_WATCHDOG_LOCK_SHIFT 0x05 1332 1332 #define PALMAS_WATCHDOG_ENABLE 0x10 1333 - #define PALMAS_WATCHDOG_ENABLE_SHIFT 4 1333 + #define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04 1334 1334 #define PALMAS_WATCHDOG_MODE 0x08 1335 - #define PALMAS_WATCHDOG_MODE_SHIFT 3 1335 + #define PALMAS_WATCHDOG_MODE_SHIFT 0x03 1336 1336 #define PALMAS_WATCHDOG_TIMER_MASK 0x07 1337 - #define PALMAS_WATCHDOG_TIMER_SHIFT 0 1337 + #define PALMAS_WATCHDOG_TIMER_SHIFT 0x00 1338 1338 1339 1339 /* Bit definitions for BOOT_STATUS */ 1340 1340 #define PALMAS_BOOT_STATUS_BOOT1 0x02 1341 - #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1 1341 + #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01 1342 1342 #define PALMAS_BOOT_STATUS_BOOT0 0x01 1343 - #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0 1343 + #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00 1344 1344 1345 1345 /* Bit definitions for BATTERY_BOUNCE */ 1346 - #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f 1347 - #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0 1346 + #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F 1347 + #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00 1348 1348 1349 1349 /* Bit definitions for BACKUP_BATTERY_CTRL */ 1350 1350 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 1351 - #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7 1351 + #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07 1352 1352 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 1353 - #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6 1353 + #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06 1354 1354 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 1355 - #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5 1355 + #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05 1356 1356 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 1357 - #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4 1357 + #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04 1358 1358 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 1359 - #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3 1359 + #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03 1360 1360 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 1361 - #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1 1361 + #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01 1362 1362 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 1363 - #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0 1363 + #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00 1364 1364 1365 1365 /* Bit definitions for LONG_PRESS_KEY */ 1366 1366 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 1367 - #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7 1367 + #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07 1368 1368 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 1369 - #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4 1369 + #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04 1370 1370 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c 1371 - #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2 1371 + #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02 1372 1372 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 1373 - #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0 1373 + #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00 1374 1374 1375 1375 /* Bit definitions for OSC_THERM_CTRL */ 1376 1376 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 1377 - #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7 1377 + #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07 1378 1378 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 1379 - #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6 1379 + #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06 1380 1380 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 1381 - #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5 1381 + #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05 1382 1382 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 1383 - #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4 1383 + #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04 1384 1384 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c 1385 - #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2 1385 + #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02 1386 1386 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 1387 - #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1 1387 + #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01 1388 1388 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 1389 - #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0 1389 + #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00 1390 1390 1391 1391 /* Bit definitions for BATDEBOUNCING */ 1392 1392 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 1393 - #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7 1393 + #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07 1394 1394 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 1395 - #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3 1395 + #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03 1396 1396 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 1397 - #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0 1397 + #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00 1398 1398 1399 1399 /* Bit definitions for SWOFF_HWRST */ 1400 1400 #define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 1401 - #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7 1401 + #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07 1402 1402 #define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 1403 - #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6 1403 + #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06 1404 1404 #define PALMAS_SWOFF_HWRST_WTD 0x20 1405 - #define PALMAS_SWOFF_HWRST_WTD_SHIFT 5 1405 + #define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05 1406 1406 #define PALMAS_SWOFF_HWRST_TSHUT 0x10 1407 - #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4 1407 + #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04 1408 1408 #define PALMAS_SWOFF_HWRST_RESET_IN 0x08 1409 - #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3 1409 + #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03 1410 1410 #define PALMAS_SWOFF_HWRST_SW_RST 0x04 1411 - #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2 1411 + #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02 1412 1412 #define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 1413 - #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1 1413 + #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01 1414 1414 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 1415 - #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0 1415 + #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00 1416 1416 1417 1417 /* Bit definitions for SWOFF_COLDRST */ 1418 1418 #define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 1419 - #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7 1419 + #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07 1420 1420 #define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 1421 - #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6 1421 + #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06 1422 1422 #define PALMAS_SWOFF_COLDRST_WTD 0x20 1423 - #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5 1423 + #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05 1424 1424 #define PALMAS_SWOFF_COLDRST_TSHUT 0x10 1425 - #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4 1425 + #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04 1426 1426 #define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 1427 - #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3 1427 + #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03 1428 1428 #define PALMAS_SWOFF_COLDRST_SW_RST 0x04 1429 - #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2 1429 + #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02 1430 1430 #define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 1431 - #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1 1431 + #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01 1432 1432 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 1433 - #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0 1433 + #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00 1434 1434 1435 1435 /* Bit definitions for SWOFF_STATUS */ 1436 1436 #define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 1437 - #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7 1437 + #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07 1438 1438 #define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 1439 - #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6 1439 + #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06 1440 1440 #define PALMAS_SWOFF_STATUS_WTD 0x20 1441 - #define PALMAS_SWOFF_STATUS_WTD_SHIFT 5 1441 + #define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05 1442 1442 #define PALMAS_SWOFF_STATUS_TSHUT 0x10 1443 - #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4 1443 + #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04 1444 1444 #define PALMAS_SWOFF_STATUS_RESET_IN 0x08 1445 - #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3 1445 + #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03 1446 1446 #define PALMAS_SWOFF_STATUS_SW_RST 0x04 1447 - #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2 1447 + #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02 1448 1448 #define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 1449 - #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1 1449 + #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01 1450 1450 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 1451 - #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0 1451 + #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00 1452 1452 1453 1453 /* Bit definitions for PMU_CONFIG */ 1454 1454 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 1455 - #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6 1455 + #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06 1456 1456 #define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 1457 - #define PALMAS_PMU_CONFIG_SPARE_SHIFT 4 1457 + #define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04 1458 1458 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c 1459 - #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2 1459 + #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02 1460 1460 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 1461 - #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1 1461 + #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01 1462 1462 #define PALMAS_PMU_CONFIG_AUTODEVON 0x01 1463 - #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0 1463 + #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00 1464 1464 1465 1465 /* Bit definitions for SPARE */ 1466 1466 #define PALMAS_SPARE_SPARE_MASK 0xf8 1467 - #define PALMAS_SPARE_SPARE_SHIFT 3 1467 + #define PALMAS_SPARE_SPARE_SHIFT 0x03 1468 1468 #define PALMAS_SPARE_REGEN3_OD 0x04 1469 - #define PALMAS_SPARE_REGEN3_OD_SHIFT 2 1469 + #define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02 1470 1470 #define PALMAS_SPARE_REGEN2_OD 0x02 1471 - #define PALMAS_SPARE_REGEN2_OD_SHIFT 1 1471 + #define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01 1472 1472 #define PALMAS_SPARE_REGEN1_OD 0x01 1473 - #define PALMAS_SPARE_REGEN1_OD_SHIFT 0 1473 + #define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00 1474 1474 1475 1475 /* Bit definitions for PMU_SECONDARY_INT */ 1476 1476 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 1477 - #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7 1477 + #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07 1478 1478 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 1479 - #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6 1479 + #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06 1480 1480 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 1481 - #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5 1481 + #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05 1482 1482 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 1483 - #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4 1483 + #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04 1484 1484 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 1485 - #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3 1485 + #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03 1486 1486 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 1487 - #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2 1487 + #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02 1488 1488 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 1489 - #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1 1489 + #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01 1490 1490 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 1491 - #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0 1491 + #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00 1492 1492 1493 1493 /* Bit definitions for SW_REVISION */ 1494 - #define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff 1495 - #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0 1494 + #define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF 1495 + #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00 1496 1496 1497 1497 /* Bit definitions for EXT_CHRG_CTRL */ 1498 1498 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 1499 - #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7 1499 + #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07 1500 1500 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 1501 - #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6 1501 + #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06 1502 1502 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 1503 - #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3 1503 + #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03 1504 1504 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 1505 - #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2 1505 + #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02 1506 1506 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 1507 - #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1 1507 + #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01 1508 1508 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 1509 - #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0 1509 + #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00 1510 1510 1511 1511 /* Bit definitions for PMU_SECONDARY_INT2 */ 1512 1512 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 1513 - #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5 1513 + #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05 1514 1514 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 1515 - #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4 1515 + #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04 1516 1516 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 1517 - #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1 1517 + #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01 1518 1518 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 1519 - #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0 1519 + #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00 1520 1520 1521 1521 /* Registers for function RESOURCE */ 1522 - #define PALMAS_CLK32KG_CTRL 0x0 1523 - #define PALMAS_CLK32KGAUDIO_CTRL 0x1 1524 - #define PALMAS_REGEN1_CTRL 0x2 1525 - #define PALMAS_REGEN2_CTRL 0x3 1526 - #define PALMAS_SYSEN1_CTRL 0x4 1527 - #define PALMAS_SYSEN2_CTRL 0x5 1528 - #define PALMAS_NSLEEP_RES_ASSIGN 0x6 1529 - #define PALMAS_NSLEEP_SMPS_ASSIGN 0x7 1530 - #define PALMAS_NSLEEP_LDO_ASSIGN1 0x8 1531 - #define PALMAS_NSLEEP_LDO_ASSIGN2 0x9 1532 - #define PALMAS_ENABLE1_RES_ASSIGN 0xA 1533 - #define PALMAS_ENABLE1_SMPS_ASSIGN 0xB 1534 - #define PALMAS_ENABLE1_LDO_ASSIGN1 0xC 1535 - #define PALMAS_ENABLE1_LDO_ASSIGN2 0xD 1536 - #define PALMAS_ENABLE2_RES_ASSIGN 0xE 1537 - #define PALMAS_ENABLE2_SMPS_ASSIGN 0xF 1522 + #define PALMAS_CLK32KG_CTRL 0x00 1523 + #define PALMAS_CLK32KGAUDIO_CTRL 0x01 1524 + #define PALMAS_REGEN1_CTRL 0x02 1525 + #define PALMAS_REGEN2_CTRL 0x03 1526 + #define PALMAS_SYSEN1_CTRL 0x04 1527 + #define PALMAS_SYSEN2_CTRL 0x05 1528 + #define PALMAS_NSLEEP_RES_ASSIGN 0x06 1529 + #define PALMAS_NSLEEP_SMPS_ASSIGN 0x07 1530 + #define PALMAS_NSLEEP_LDO_ASSIGN1 0x08 1531 + #define PALMAS_NSLEEP_LDO_ASSIGN2 0x09 1532 + #define PALMAS_ENABLE1_RES_ASSIGN 0x0A 1533 + #define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B 1534 + #define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C 1535 + #define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D 1536 + #define PALMAS_ENABLE2_RES_ASSIGN 0x0E 1537 + #define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F 1538 1538 #define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 1539 1539 #define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 1540 1540 #define PALMAS_REGEN3_CTRL 0x12 1541 1541 1542 1542 /* Bit definitions for CLK32KG_CTRL */ 1543 1543 #define PALMAS_CLK32KG_CTRL_STATUS 0x10 1544 - #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4 1544 + #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04 1545 1545 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 1546 - #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2 1546 + #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02 1547 1547 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 1548 - #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0 1548 + #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00 1549 1549 1550 1550 /* Bit definitions for CLK32KGAUDIO_CTRL */ 1551 1551 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 1552 - #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4 1552 + #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04 1553 1553 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 1554 - #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3 1554 + #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03 1555 1555 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 1556 - #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2 1556 + #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02 1557 1557 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 1558 - #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0 1558 + #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00 1559 1559 1560 1560 /* Bit definitions for REGEN1_CTRL */ 1561 1561 #define PALMAS_REGEN1_CTRL_STATUS 0x10 1562 - #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4 1562 + #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04 1563 1563 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 1564 - #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2 1564 + #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 1565 1565 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 1566 - #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0 1566 + #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 1567 1567 1568 1568 /* Bit definitions for REGEN2_CTRL */ 1569 1569 #define PALMAS_REGEN2_CTRL_STATUS 0x10 1570 - #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4 1570 + #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04 1571 1571 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 1572 - #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2 1572 + #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 1573 1573 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 1574 - #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0 1574 + #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 1575 1575 1576 1576 /* Bit definitions for SYSEN1_CTRL */ 1577 1577 #define PALMAS_SYSEN1_CTRL_STATUS 0x10 1578 - #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4 1578 + #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04 1579 1579 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 1580 - #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2 1580 + #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02 1581 1581 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 1582 - #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0 1582 + #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 1583 1583 1584 1584 /* Bit definitions for SYSEN2_CTRL */ 1585 1585 #define PALMAS_SYSEN2_CTRL_STATUS 0x10 1586 - #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4 1586 + #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04 1587 1587 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 1588 - #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2 1588 + #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02 1589 1589 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 1590 - #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0 1590 + #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 1591 1591 1592 1592 /* Bit definitions for NSLEEP_RES_ASSIGN */ 1593 1593 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 1594 - #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6 1594 + #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06 1595 1595 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 1596 - #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1596 + #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 1597 1597 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 1598 - #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4 1598 + #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04 1599 1599 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 1600 - #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3 1600 + #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03 1601 1601 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 1602 - #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2 1602 + #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02 1603 1603 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 1604 - #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1 1604 + #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 1605 1605 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 1606 - #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0 1606 + #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 1607 1607 1608 1608 /* Bit definitions for NSLEEP_SMPS_ASSIGN */ 1609 1609 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 1610 - #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7 1610 + #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07 1611 1611 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 1612 - #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6 1612 + #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06 1613 1613 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 1614 - #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5 1614 + #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05 1615 1615 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 1616 - #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4 1616 + #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04 1617 1617 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 1618 - #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3 1618 + #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03 1619 1619 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 1620 - #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2 1620 + #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02 1621 1621 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 1622 - #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1 1622 + #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01 1623 1623 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 1624 - #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0 1624 + #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00 1625 1625 1626 1626 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 1627 1627 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 1628 - #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7 1628 + #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07 1629 1629 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 1630 - #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6 1630 + #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06 1631 1631 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 1632 - #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5 1632 + #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05 1633 1633 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 1634 - #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4 1634 + #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04 1635 1635 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 1636 - #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3 1636 + #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03 1637 1637 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 1638 - #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2 1638 + #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02 1639 1639 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 1640 - #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1 1640 + #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 1641 1641 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 1642 - #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0 1642 + #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 1643 1643 1644 1644 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 1645 1645 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 1646 - #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2 1646 + #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 1647 1647 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 1648 - #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1 1648 + #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01 1649 1649 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 1650 - #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0 1650 + #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00 1651 1651 1652 1652 /* Bit definitions for ENABLE1_RES_ASSIGN */ 1653 1653 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 1654 - #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6 1654 + #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06 1655 1655 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 1656 - #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1656 + #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 1657 1657 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 1658 - #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4 1658 + #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04 1659 1659 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 1660 - #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3 1660 + #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03 1661 1661 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 1662 - #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2 1662 + #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02 1663 1663 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 1664 - #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1 1664 + #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 1665 1665 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 1666 - #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0 1666 + #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 1667 1667 1668 1668 /* Bit definitions for ENABLE1_SMPS_ASSIGN */ 1669 1669 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 1670 - #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7 1670 + #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07 1671 1671 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 1672 - #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6 1672 + #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06 1673 1673 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 1674 - #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5 1674 + #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05 1675 1675 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 1676 - #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4 1676 + #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04 1677 1677 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 1678 - #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3 1678 + #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03 1679 1679 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 1680 - #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2 1680 + #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02 1681 1681 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 1682 - #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1 1682 + #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01 1683 1683 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 1684 - #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0 1684 + #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00 1685 1685 1686 1686 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 1687 1687 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 1688 - #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7 1688 + #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07 1689 1689 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 1690 - #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6 1690 + #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06 1691 1691 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 1692 - #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5 1692 + #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05 1693 1693 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 1694 - #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4 1694 + #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04 1695 1695 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 1696 - #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3 1696 + #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03 1697 1697 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 1698 - #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2 1698 + #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02 1699 1699 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 1700 - #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1 1700 + #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 1701 1701 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 1702 - #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0 1702 + #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 1703 1703 1704 1704 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 1705 1705 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 1706 - #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2 1706 + #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 1707 1707 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 1708 - #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1 1708 + #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01 1709 1709 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 1710 - #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0 1710 + #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00 1711 1711 1712 1712 /* Bit definitions for ENABLE2_RES_ASSIGN */ 1713 1713 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 1714 - #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6 1714 + #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06 1715 1715 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 1716 - #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1716 + #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 1717 1717 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 1718 - #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4 1718 + #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04 1719 1719 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 1720 - #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3 1720 + #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03 1721 1721 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 1722 - #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2 1722 + #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02 1723 1723 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 1724 - #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1 1724 + #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 1725 1725 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 1726 - #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0 1726 + #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 1727 1727 1728 1728 /* Bit definitions for ENABLE2_SMPS_ASSIGN */ 1729 1729 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 1730 - #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7 1730 + #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07 1731 1731 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 1732 - #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6 1732 + #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06 1733 1733 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 1734 - #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5 1734 + #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05 1735 1735 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 1736 - #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4 1736 + #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04 1737 1737 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 1738 - #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3 1738 + #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03 1739 1739 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 1740 - #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2 1740 + #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02 1741 1741 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 1742 - #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1 1742 + #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01 1743 1743 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 1744 - #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0 1744 + #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00 1745 1745 1746 1746 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 1747 1747 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 1748 - #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7 1748 + #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07 1749 1749 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 1750 - #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6 1750 + #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06 1751 1751 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 1752 - #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5 1752 + #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05 1753 1753 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 1754 - #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4 1754 + #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04 1755 1755 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 1756 - #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3 1756 + #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03 1757 1757 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 1758 - #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2 1758 + #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02 1759 1759 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 1760 - #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1 1760 + #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 1761 1761 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 1762 - #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0 1762 + #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 1763 1763 1764 1764 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 1765 1765 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 1766 - #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2 1766 + #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 1767 1767 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 1768 - #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1 1768 + #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01 1769 1769 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 1770 - #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0 1770 + #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00 1771 1771 1772 1772 /* Bit definitions for REGEN3_CTRL */ 1773 1773 #define PALMAS_REGEN3_CTRL_STATUS 0x10 1774 - #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4 1774 + #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04 1775 1775 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 1776 - #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2 1776 + #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 1777 1777 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 1778 - #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 1778 + #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 1779 1779 1780 1780 /* Registers for function PAD_CONTROL */ 1781 - #define PALMAS_OD_OUTPUT_CTRL2 0x2 1782 - #define PALMAS_POLARITY_CTRL2 0x3 1783 - #define PALMAS_PU_PD_INPUT_CTRL1 0x4 1784 - #define PALMAS_PU_PD_INPUT_CTRL2 0x5 1785 - #define PALMAS_PU_PD_INPUT_CTRL3 0x6 1786 - #define PALMAS_PU_PD_INPUT_CTRL5 0x7 1787 - #define PALMAS_OD_OUTPUT_CTRL 0x8 1788 - #define PALMAS_POLARITY_CTRL 0x9 1789 - #define PALMAS_PRIMARY_SECONDARY_PAD1 0xA 1790 - #define PALMAS_PRIMARY_SECONDARY_PAD2 0xB 1791 - #define PALMAS_I2C_SPI 0xC 1792 - #define PALMAS_PU_PD_INPUT_CTRL4 0xD 1793 - #define PALMAS_PRIMARY_SECONDARY_PAD3 0xE 1794 - #define PALMAS_PRIMARY_SECONDARY_PAD4 0xF 1781 + #define PALMAS_OD_OUTPUT_CTRL2 0x02 1782 + #define PALMAS_POLARITY_CTRL2 0x03 1783 + #define PALMAS_PU_PD_INPUT_CTRL1 0x04 1784 + #define PALMAS_PU_PD_INPUT_CTRL2 0x05 1785 + #define PALMAS_PU_PD_INPUT_CTRL3 0x06 1786 + #define PALMAS_PU_PD_INPUT_CTRL5 0x07 1787 + #define PALMAS_OD_OUTPUT_CTRL 0x08 1788 + #define PALMAS_POLARITY_CTRL 0x09 1789 + #define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A 1790 + #define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B 1791 + #define PALMAS_I2C_SPI 0x0C 1792 + #define PALMAS_PU_PD_INPUT_CTRL4 0x0D 1793 + #define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E 1794 + #define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F 1795 1795 1796 1796 /* Bit definitions for PU_PD_INPUT_CTRL1 */ 1797 1797 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1798 - #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6 1798 + #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06 1799 1799 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 1800 - #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5 1800 + #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05 1801 1801 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 1802 - #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4 1802 + #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04 1803 1803 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 1804 - #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2 1804 + #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02 1805 1805 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 1806 - #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1 1806 + #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01 1807 1807 1808 1808 /* Bit definitions for PU_PD_INPUT_CTRL2 */ 1809 1809 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 1810 - #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5 1810 + #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05 1811 1811 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 1812 - #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4 1812 + #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04 1813 1813 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 1814 - #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3 1814 + #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03 1815 1815 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 1816 - #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2 1816 + #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02 1817 1817 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 1818 - #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1 1818 + #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01 1819 1819 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 1820 - #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0 1820 + #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00 1821 1821 1822 1822 /* Bit definitions for PU_PD_INPUT_CTRL3 */ 1823 1823 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 1824 - #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6 1824 + #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06 1825 1825 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 1826 - #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4 1826 + #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04 1827 1827 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 1828 - #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2 1828 + #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02 1829 1829 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 1830 - #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0 1830 + #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00 1831 1831 1832 1832 /* Bit definitions for OD_OUTPUT_CTRL */ 1833 1833 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 1834 - #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7 1834 + #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07 1835 1835 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 1836 - #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6 1836 + #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06 1837 1837 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 1838 - #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5 1838 + #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05 1839 1839 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 1840 - #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3 1840 + #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03 1841 1841 1842 1842 /* Bit definitions for POLARITY_CTRL */ 1843 1843 #define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 1844 - #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7 1844 + #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07 1845 1845 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 1846 - #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6 1846 + #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06 1847 1847 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 1848 - #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5 1848 + #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05 1849 1849 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 1850 - #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4 1850 + #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04 1851 1851 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 1852 - #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3 1852 + #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03 1853 1853 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 1854 - #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2 1854 + #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02 1855 1855 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 1856 - #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1 1856 + #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01 1857 1857 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 1858 - #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0 1858 + #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00 1859 1859 1860 1860 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */ 1861 1861 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 1862 - #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7 1862 + #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07 1863 1863 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 1864 - #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5 1864 + #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05 1865 1865 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 1866 - #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3 1866 + #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03 1867 1867 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 1868 - #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2 1868 + #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02 1869 1869 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 1870 - #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1 1870 + #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01 1871 1871 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 1872 - #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0 1872 + #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00 1873 1873 1874 1874 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */ 1875 1875 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 1876 - #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4 1876 + #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04 1877 1877 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 1878 - #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3 1878 + #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03 1879 1879 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 1880 - #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1 1880 + #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01 1881 1881 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 1882 - #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0 1882 + #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00 1883 1883 1884 1884 /* Bit definitions for I2C_SPI */ 1885 1885 #define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 1886 - #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7 1886 + #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07 1887 1887 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 1888 - #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6 1888 + #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06 1889 1889 #define PALMAS_I2C_SPI_ID_I2C2 0x20 1890 - #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5 1890 + #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05 1891 1891 #define PALMAS_I2C_SPI_I2C_SPI 0x10 1892 - #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4 1893 - #define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f 1894 - #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0 1892 + #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04 1893 + #define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F 1894 + #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00 1895 1895 1896 1896 /* Bit definitions for PU_PD_INPUT_CTRL4 */ 1897 1897 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 1898 - #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6 1898 + #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06 1899 1899 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 1900 - #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4 1900 + #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04 1901 1901 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 1902 - #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2 1902 + #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02 1903 1903 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 1904 - #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0 1904 + #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00 1905 1905 1906 1906 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */ 1907 1907 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 1908 - #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1 1908 + #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01 1909 1909 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 1910 - #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0 1910 + #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00 1911 1911 1912 1912 /* Registers for function LED_PWM */ 1913 - #define PALMAS_LED_PERIOD_CTRL 0x0 1914 - #define PALMAS_LED_CTRL 0x1 1915 - #define PALMAS_PWM_CTRL1 0x2 1916 - #define PALMAS_PWM_CTRL2 0x3 1913 + #define PALMAS_LED_PERIOD_CTRL 0x00 1914 + #define PALMAS_LED_CTRL 0x01 1915 + #define PALMAS_PWM_CTRL1 0x02 1916 + #define PALMAS_PWM_CTRL2 0x03 1917 1917 1918 1918 /* Bit definitions for LED_PERIOD_CTRL */ 1919 1919 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 1920 - #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3 1920 + #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03 1921 1921 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 1922 - #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0 1922 + #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00 1923 1923 1924 1924 /* Bit definitions for LED_CTRL */ 1925 1925 #define PALMAS_LED_CTRL_LED_2_SEQ 0x20 1926 - #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5 1926 + #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05 1927 1927 #define PALMAS_LED_CTRL_LED_1_SEQ 0x10 1928 - #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4 1928 + #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04 1929 1929 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c 1930 - #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2 1930 + #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02 1931 1931 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 1932 - #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0 1932 + #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00 1933 1933 1934 1934 /* Bit definitions for PWM_CTRL1 */ 1935 1935 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 1936 - #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1 1936 + #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01 1937 1937 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 1938 - #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0 1938 + #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00 1939 1939 1940 1940 /* Bit definitions for PWM_CTRL2 */ 1941 - #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff 1942 - #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0 1941 + #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF 1942 + #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00 1943 1943 1944 1944 /* Registers for function INTERRUPT */ 1945 - #define PALMAS_INT1_STATUS 0x0 1946 - #define PALMAS_INT1_MASK 0x1 1947 - #define PALMAS_INT1_LINE_STATE 0x2 1948 - #define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3 1949 - #define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4 1950 - #define PALMAS_INT2_STATUS 0x5 1951 - #define PALMAS_INT2_MASK 0x6 1952 - #define PALMAS_INT2_LINE_STATE 0x7 1953 - #define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8 1954 - #define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9 1955 - #define PALMAS_INT3_STATUS 0xA 1956 - #define PALMAS_INT3_MASK 0xB 1957 - #define PALMAS_INT3_LINE_STATE 0xC 1958 - #define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD 1959 - #define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE 1960 - #define PALMAS_INT4_STATUS 0xF 1945 + #define PALMAS_INT1_STATUS 0x00 1946 + #define PALMAS_INT1_MASK 0x01 1947 + #define PALMAS_INT1_LINE_STATE 0x02 1948 + #define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03 1949 + #define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04 1950 + #define PALMAS_INT2_STATUS 0x05 1951 + #define PALMAS_INT2_MASK 0x06 1952 + #define PALMAS_INT2_LINE_STATE 0x07 1953 + #define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08 1954 + #define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09 1955 + #define PALMAS_INT3_STATUS 0x0A 1956 + #define PALMAS_INT3_MASK 0x0B 1957 + #define PALMAS_INT3_LINE_STATE 0x0C 1958 + #define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D 1959 + #define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E 1960 + #define PALMAS_INT4_STATUS 0x0F 1961 1961 #define PALMAS_INT4_MASK 0x10 1962 1962 #define PALMAS_INT4_LINE_STATE 0x11 1963 1963 #define PALMAS_INT4_EDGE_DETECT1 0x12 ··· 1966 1966 1967 1967 /* Bit definitions for INT1_STATUS */ 1968 1968 #define PALMAS_INT1_STATUS_VBAT_MON 0x80 1969 - #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7 1969 + #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07 1970 1970 #define PALMAS_INT1_STATUS_VSYS_MON 0x40 1971 - #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6 1971 + #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06 1972 1972 #define PALMAS_INT1_STATUS_HOTDIE 0x20 1973 - #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5 1973 + #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05 1974 1974 #define PALMAS_INT1_STATUS_PWRDOWN 0x10 1975 - #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4 1975 + #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04 1976 1976 #define PALMAS_INT1_STATUS_RPWRON 0x08 1977 - #define PALMAS_INT1_STATUS_RPWRON_SHIFT 3 1977 + #define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03 1978 1978 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 1979 - #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2 1979 + #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 1980 1980 #define PALMAS_INT1_STATUS_PWRON 0x02 1981 - #define PALMAS_INT1_STATUS_PWRON_SHIFT 1 1981 + #define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01 1982 1982 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 1983 - #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0 1983 + #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 1984 1984 1985 1985 /* Bit definitions for INT1_MASK */ 1986 1986 #define PALMAS_INT1_MASK_VBAT_MON 0x80 1987 - #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7 1987 + #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07 1988 1988 #define PALMAS_INT1_MASK_VSYS_MON 0x40 1989 - #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6 1989 + #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06 1990 1990 #define PALMAS_INT1_MASK_HOTDIE 0x20 1991 - #define PALMAS_INT1_MASK_HOTDIE_SHIFT 5 1991 + #define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05 1992 1992 #define PALMAS_INT1_MASK_PWRDOWN 0x10 1993 - #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4 1993 + #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04 1994 1994 #define PALMAS_INT1_MASK_RPWRON 0x08 1995 - #define PALMAS_INT1_MASK_RPWRON_SHIFT 3 1995 + #define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03 1996 1996 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 1997 - #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2 1997 + #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 1998 1998 #define PALMAS_INT1_MASK_PWRON 0x02 1999 - #define PALMAS_INT1_MASK_PWRON_SHIFT 1 1999 + #define PALMAS_INT1_MASK_PWRON_SHIFT 0x01 2000 2000 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 2001 - #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0 2001 + #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 2002 2002 2003 2003 /* Bit definitions for INT1_LINE_STATE */ 2004 2004 #define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 2005 - #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7 2005 + #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07 2006 2006 #define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 2007 - #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6 2007 + #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 2008 2008 #define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 2009 - #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5 2009 + #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 2010 2010 #define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 2011 - #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4 2011 + #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 2012 2012 #define PALMAS_INT1_LINE_STATE_RPWRON 0x08 2013 - #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3 2013 + #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03 2014 2014 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 2015 - #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2 2015 + #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 2016 2016 #define PALMAS_INT1_LINE_STATE_PWRON 0x02 2017 - #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1 2017 + #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01 2018 2018 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 2019 - #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0 2019 + #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 2020 2020 2021 2021 /* Bit definitions for INT2_STATUS */ 2022 2022 #define PALMAS_INT2_STATUS_VAC_ACOK 0x80 2023 - #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7 2023 + #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07 2024 2024 #define PALMAS_INT2_STATUS_SHORT 0x40 2025 - #define PALMAS_INT2_STATUS_SHORT_SHIFT 6 2025 + #define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06 2026 2026 #define PALMAS_INT2_STATUS_FBI_BB 0x20 2027 - #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5 2027 + #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05 2028 2028 #define PALMAS_INT2_STATUS_RESET_IN 0x10 2029 - #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4 2029 + #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04 2030 2030 #define PALMAS_INT2_STATUS_BATREMOVAL 0x08 2031 - #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3 2031 + #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03 2032 2032 #define PALMAS_INT2_STATUS_WDT 0x04 2033 - #define PALMAS_INT2_STATUS_WDT_SHIFT 2 2033 + #define PALMAS_INT2_STATUS_WDT_SHIFT 0x02 2034 2034 #define PALMAS_INT2_STATUS_RTC_TIMER 0x02 2035 - #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1 2035 + #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01 2036 2036 #define PALMAS_INT2_STATUS_RTC_ALARM 0x01 2037 - #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0 2037 + #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00 2038 2038 2039 2039 /* Bit definitions for INT2_MASK */ 2040 2040 #define PALMAS_INT2_MASK_VAC_ACOK 0x80 2041 - #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7 2041 + #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07 2042 2042 #define PALMAS_INT2_MASK_SHORT 0x40 2043 - #define PALMAS_INT2_MASK_SHORT_SHIFT 6 2043 + #define PALMAS_INT2_MASK_SHORT_SHIFT 0x06 2044 2044 #define PALMAS_INT2_MASK_FBI_BB 0x20 2045 - #define PALMAS_INT2_MASK_FBI_BB_SHIFT 5 2045 + #define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05 2046 2046 #define PALMAS_INT2_MASK_RESET_IN 0x10 2047 - #define PALMAS_INT2_MASK_RESET_IN_SHIFT 4 2047 + #define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04 2048 2048 #define PALMAS_INT2_MASK_BATREMOVAL 0x08 2049 - #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3 2049 + #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03 2050 2050 #define PALMAS_INT2_MASK_WDT 0x04 2051 - #define PALMAS_INT2_MASK_WDT_SHIFT 2 2051 + #define PALMAS_INT2_MASK_WDT_SHIFT 0x02 2052 2052 #define PALMAS_INT2_MASK_RTC_TIMER 0x02 2053 - #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1 2053 + #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01 2054 2054 #define PALMAS_INT2_MASK_RTC_ALARM 0x01 2055 - #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0 2055 + #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00 2056 2056 2057 2057 /* Bit definitions for INT2_LINE_STATE */ 2058 2058 #define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 2059 - #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7 2059 + #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07 2060 2060 #define PALMAS_INT2_LINE_STATE_SHORT 0x40 2061 - #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6 2061 + #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06 2062 2062 #define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 2063 - #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5 2063 + #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05 2064 2064 #define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 2065 - #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4 2065 + #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 2066 2066 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 2067 - #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3 2067 + #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03 2068 2068 #define PALMAS_INT2_LINE_STATE_WDT 0x04 2069 - #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2 2069 + #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02 2070 2070 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 2071 - #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1 2071 + #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01 2072 2072 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 2073 - #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0 2073 + #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00 2074 2074 2075 2075 /* Bit definitions for INT3_STATUS */ 2076 2076 #define PALMAS_INT3_STATUS_VBUS 0x80 2077 - #define PALMAS_INT3_STATUS_VBUS_SHIFT 7 2077 + #define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07 2078 2078 #define PALMAS_INT3_STATUS_VBUS_OTG 0x40 2079 - #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6 2079 + #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06 2080 2080 #define PALMAS_INT3_STATUS_ID 0x20 2081 - #define PALMAS_INT3_STATUS_ID_SHIFT 5 2081 + #define PALMAS_INT3_STATUS_ID_SHIFT 0x05 2082 2082 #define PALMAS_INT3_STATUS_ID_OTG 0x10 2083 - #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4 2083 + #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04 2084 2084 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 2085 - #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3 2085 + #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03 2086 2086 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 2087 - #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2 2087 + #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 2088 2088 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 2089 - #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1 2089 + #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 2090 2090 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 2091 - #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0 2091 + #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 2092 2092 2093 2093 /* Bit definitions for INT3_MASK */ 2094 2094 #define PALMAS_INT3_MASK_VBUS 0x80 2095 - #define PALMAS_INT3_MASK_VBUS_SHIFT 7 2095 + #define PALMAS_INT3_MASK_VBUS_SHIFT 0x07 2096 2096 #define PALMAS_INT3_MASK_VBUS_OTG 0x40 2097 - #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6 2097 + #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06 2098 2098 #define PALMAS_INT3_MASK_ID 0x20 2099 - #define PALMAS_INT3_MASK_ID_SHIFT 5 2099 + #define PALMAS_INT3_MASK_ID_SHIFT 0x05 2100 2100 #define PALMAS_INT3_MASK_ID_OTG 0x10 2101 - #define PALMAS_INT3_MASK_ID_OTG_SHIFT 4 2101 + #define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04 2102 2102 #define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 2103 - #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3 2103 + #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03 2104 2104 #define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 2105 - #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2 2105 + #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 2106 2106 #define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 2107 - #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1 2107 + #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 2108 2108 #define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 2109 - #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0 2109 + #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 2110 2110 2111 2111 /* Bit definitions for INT3_LINE_STATE */ 2112 2112 #define PALMAS_INT3_LINE_STATE_VBUS 0x80 2113 - #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7 2113 + #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07 2114 2114 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 2115 - #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6 2115 + #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06 2116 2116 #define PALMAS_INT3_LINE_STATE_ID 0x20 2117 - #define PALMAS_INT3_LINE_STATE_ID_SHIFT 5 2117 + #define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05 2118 2118 #define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 2119 - #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4 2119 + #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04 2120 2120 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 2121 - #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3 2121 + #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03 2122 2122 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 2123 - #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2 2123 + #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 2124 2124 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 2125 - #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1 2125 + #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 2126 2126 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 2127 - #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0 2127 + #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 2128 2128 2129 2129 /* Bit definitions for INT4_STATUS */ 2130 2130 #define PALMAS_INT4_STATUS_GPIO_7 0x80 2131 - #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7 2131 + #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07 2132 2132 #define PALMAS_INT4_STATUS_GPIO_6 0x40 2133 - #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6 2133 + #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06 2134 2134 #define PALMAS_INT4_STATUS_GPIO_5 0x20 2135 - #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5 2135 + #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05 2136 2136 #define PALMAS_INT4_STATUS_GPIO_4 0x10 2137 - #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4 2137 + #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04 2138 2138 #define PALMAS_INT4_STATUS_GPIO_3 0x08 2139 - #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3 2139 + #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03 2140 2140 #define PALMAS_INT4_STATUS_GPIO_2 0x04 2141 - #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2 2141 + #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02 2142 2142 #define PALMAS_INT4_STATUS_GPIO_1 0x02 2143 - #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1 2143 + #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01 2144 2144 #define PALMAS_INT4_STATUS_GPIO_0 0x01 2145 - #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0 2145 + #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00 2146 2146 2147 2147 /* Bit definitions for INT4_MASK */ 2148 2148 #define PALMAS_INT4_MASK_GPIO_7 0x80 2149 - #define PALMAS_INT4_MASK_GPIO_7_SHIFT 7 2149 + #define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07 2150 2150 #define PALMAS_INT4_MASK_GPIO_6 0x40 2151 - #define PALMAS_INT4_MASK_GPIO_6_SHIFT 6 2151 + #define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06 2152 2152 #define PALMAS_INT4_MASK_GPIO_5 0x20 2153 - #define PALMAS_INT4_MASK_GPIO_5_SHIFT 5 2153 + #define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05 2154 2154 #define PALMAS_INT4_MASK_GPIO_4 0x10 2155 - #define PALMAS_INT4_MASK_GPIO_4_SHIFT 4 2155 + #define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04 2156 2156 #define PALMAS_INT4_MASK_GPIO_3 0x08 2157 - #define PALMAS_INT4_MASK_GPIO_3_SHIFT 3 2157 + #define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03 2158 2158 #define PALMAS_INT4_MASK_GPIO_2 0x04 2159 - #define PALMAS_INT4_MASK_GPIO_2_SHIFT 2 2159 + #define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02 2160 2160 #define PALMAS_INT4_MASK_GPIO_1 0x02 2161 - #define PALMAS_INT4_MASK_GPIO_1_SHIFT 1 2161 + #define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01 2162 2162 #define PALMAS_INT4_MASK_GPIO_0 0x01 2163 - #define PALMAS_INT4_MASK_GPIO_0_SHIFT 0 2163 + #define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00 2164 2164 2165 2165 /* Bit definitions for INT4_LINE_STATE */ 2166 2166 #define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 2167 - #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7 2167 + #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07 2168 2168 #define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 2169 - #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6 2169 + #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 2170 2170 #define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 2171 - #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5 2171 + #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 2172 2172 #define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 2173 - #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4 2173 + #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 2174 2174 #define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 2175 - #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3 2175 + #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 2176 2176 #define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 2177 - #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2 2177 + #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 2178 2178 #define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 2179 - #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1 2179 + #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 2180 2180 #define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 2181 - #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0 2181 + #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 2182 2182 2183 2183 /* Bit definitions for INT4_EDGE_DETECT1 */ 2184 2184 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 2185 - #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7 2185 + #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 2186 2186 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 2187 - #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6 2187 + #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 2188 2188 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 2189 - #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5 2189 + #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 2190 2190 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 2191 - #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4 2191 + #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 2192 2192 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 2193 - #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3 2193 + #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 2194 2194 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 2195 - #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2 2195 + #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 2196 2196 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 2197 - #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1 2197 + #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 2198 2198 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 2199 - #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0 2199 + #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 2200 2200 2201 2201 /* Bit definitions for INT4_EDGE_DETECT2 */ 2202 2202 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 2203 - #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7 2203 + #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07 2204 2204 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 2205 - #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6 2205 + #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06 2206 2206 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 2207 - #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5 2207 + #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 2208 2208 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 2209 - #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4 2209 + #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 2210 2210 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 2211 - #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3 2211 + #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 2212 2212 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 2213 - #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2 2213 + #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 2214 2214 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 2215 - #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1 2215 + #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 2216 2216 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 2217 - #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0 2217 + #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 2218 2218 2219 2219 /* Bit definitions for INT_CTRL */ 2220 2220 #define PALMAS_INT_CTRL_INT_PENDING 0x04 2221 - #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2 2221 + #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02 2222 2222 #define PALMAS_INT_CTRL_INT_CLEAR 0x01 2223 - #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0 2223 + #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00 2224 2224 2225 2225 /* Registers for function USB_OTG */ 2226 - #define PALMAS_USB_WAKEUP 0x3 2227 - #define PALMAS_USB_VBUS_CTRL_SET 0x4 2228 - #define PALMAS_USB_VBUS_CTRL_CLR 0x5 2229 - #define PALMAS_USB_ID_CTRL_SET 0x6 2230 - #define PALMAS_USB_ID_CTRL_CLEAR 0x7 2231 - #define PALMAS_USB_VBUS_INT_SRC 0x8 2232 - #define PALMAS_USB_VBUS_INT_LATCH_SET 0x9 2233 - #define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA 2234 - #define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB 2235 - #define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC 2236 - #define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD 2237 - #define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE 2238 - #define PALMAS_USB_ID_INT_SRC 0xF 2226 + #define PALMAS_USB_WAKEUP 0x03 2227 + #define PALMAS_USB_VBUS_CTRL_SET 0x04 2228 + #define PALMAS_USB_VBUS_CTRL_CLR 0x05 2229 + #define PALMAS_USB_ID_CTRL_SET 0x06 2230 + #define PALMAS_USB_ID_CTRL_CLEAR 0x07 2231 + #define PALMAS_USB_VBUS_INT_SRC 0x08 2232 + #define PALMAS_USB_VBUS_INT_LATCH_SET 0x09 2233 + #define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A 2234 + #define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B 2235 + #define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C 2236 + #define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D 2237 + #define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E 2238 + #define PALMAS_USB_ID_INT_SRC 0x0F 2239 2239 #define PALMAS_USB_ID_INT_LATCH_SET 0x10 2240 2240 #define PALMAS_USB_ID_INT_LATCH_CLR 0x11 2241 2241 #define PALMAS_USB_ID_INT_EN_LO_SET 0x12 ··· 2250 2250 2251 2251 /* Bit definitions for USB_WAKEUP */ 2252 2252 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 2253 - #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0 2253 + #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00 2254 2254 2255 2255 /* Bit definitions for USB_VBUS_CTRL_SET */ 2256 2256 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 2257 - #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7 2257 + #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07 2258 2258 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 2259 - #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5 2259 + #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05 2260 2260 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 2261 - #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4 2261 + #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04 2262 2262 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 2263 - #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3 2263 + #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03 2264 2264 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 2265 - #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2 2265 + #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02 2266 2266 2267 2267 /* Bit definitions for USB_VBUS_CTRL_CLR */ 2268 2268 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 2269 - #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7 2269 + #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07 2270 2270 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 2271 - #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5 2271 + #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05 2272 2272 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 2273 - #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4 2273 + #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04 2274 2274 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 2275 - #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3 2275 + #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03 2276 2276 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 2277 - #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2 2277 + #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02 2278 2278 2279 2279 /* Bit definitions for USB_ID_CTRL_SET */ 2280 2280 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 2281 - #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7 2281 + #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07 2282 2282 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 2283 - #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6 2283 + #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06 2284 2284 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 2285 - #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5 2285 + #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05 2286 2286 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 2287 - #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4 2287 + #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04 2288 2288 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 2289 - #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3 2289 + #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03 2290 2290 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 2291 - #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2 2291 + #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02 2292 2292 2293 2293 /* Bit definitions for USB_ID_CTRL_CLEAR */ 2294 2294 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 2295 - #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7 2295 + #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07 2296 2296 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 2297 - #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6 2297 + #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06 2298 2298 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 2299 - #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5 2299 + #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05 2300 2300 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 2301 - #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4 2301 + #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04 2302 2302 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 2303 - #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3 2303 + #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03 2304 2304 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 2305 - #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2 2305 + #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02 2306 2306 2307 2307 /* Bit definitions for USB_VBUS_INT_SRC */ 2308 2308 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 2309 - #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7 2309 + #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07 2310 2310 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 2311 - #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6 2311 + #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06 2312 2312 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 2313 - #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5 2313 + #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05 2314 2314 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 2315 - #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3 2315 + #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03 2316 2316 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 2317 - #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2 2317 + #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02 2318 2318 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 2319 - #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1 2319 + #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01 2320 2320 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 2321 - #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0 2321 + #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00 2322 2322 2323 2323 /* Bit definitions for USB_VBUS_INT_LATCH_SET */ 2324 2324 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 2325 - #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7 2325 + #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07 2326 2326 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 2327 - #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6 2327 + #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06 2328 2328 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 2329 - #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5 2329 + #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05 2330 2330 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 2331 - #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4 2331 + #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04 2332 2332 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 2333 - #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3 2333 + #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03 2334 2334 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 2335 - #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2 2335 + #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02 2336 2336 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 2337 - #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1 2337 + #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01 2338 2338 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 2339 - #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0 2339 + #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00 2340 2340 2341 2341 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */ 2342 2342 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 2343 - #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7 2343 + #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07 2344 2344 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 2345 - #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6 2345 + #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06 2346 2346 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 2347 - #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5 2347 + #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05 2348 2348 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 2349 - #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4 2349 + #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04 2350 2350 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 2351 - #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3 2351 + #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03 2352 2352 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 2353 - #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2 2353 + #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02 2354 2354 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 2355 - #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1 2355 + #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01 2356 2356 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 2357 - #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0 2357 + #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00 2358 2358 2359 2359 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */ 2360 2360 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 2361 - #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7 2361 + #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07 2362 2362 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 2363 - #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6 2363 + #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06 2364 2364 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 2365 - #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5 2365 + #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05 2366 2366 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 2367 - #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3 2367 + #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03 2368 2368 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 2369 - #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2 2369 + #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02 2370 2370 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 2371 - #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1 2371 + #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01 2372 2372 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 2373 - #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0 2373 + #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00 2374 2374 2375 2375 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ 2376 2376 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 2377 - #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7 2377 + #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07 2378 2378 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 2379 - #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6 2379 + #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06 2380 2380 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 2381 - #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5 2381 + #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05 2382 2382 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 2383 - #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3 2383 + #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03 2384 2384 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 2385 - #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2 2385 + #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02 2386 2386 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 2387 - #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1 2387 + #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01 2388 2388 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 2389 - #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0 2389 + #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00 2390 2390 2391 2391 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */ 2392 2392 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 2393 - #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7 2393 + #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07 2394 2394 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 2395 - #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6 2395 + #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06 2396 2396 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 2397 - #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5 2397 + #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05 2398 2398 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 2399 - #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4 2399 + #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04 2400 2400 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 2401 - #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3 2401 + #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03 2402 2402 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 2403 - #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2 2403 + #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02 2404 2404 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 2405 - #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1 2405 + #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01 2406 2406 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 2407 - #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0 2407 + #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00 2408 2408 2409 2409 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ 2410 2410 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 2411 - #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7 2411 + #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07 2412 2412 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 2413 - #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6 2413 + #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06 2414 2414 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 2415 - #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5 2415 + #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05 2416 2416 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 2417 - #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4 2417 + #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04 2418 2418 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 2419 - #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3 2419 + #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03 2420 2420 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 2421 - #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2 2421 + #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02 2422 2422 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 2423 - #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1 2423 + #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01 2424 2424 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 2425 - #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0 2425 + #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00 2426 2426 2427 2427 /* Bit definitions for USB_ID_INT_SRC */ 2428 2428 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 2429 - #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4 2429 + #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04 2430 2430 #define PALMAS_USB_ID_INT_SRC_ID_A 0x08 2431 - #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3 2431 + #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03 2432 2432 #define PALMAS_USB_ID_INT_SRC_ID_B 0x04 2433 - #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2 2433 + #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02 2434 2434 #define PALMAS_USB_ID_INT_SRC_ID_C 0x02 2435 - #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1 2435 + #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01 2436 2436 #define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 2437 - #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0 2437 + #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00 2438 2438 2439 2439 /* Bit definitions for USB_ID_INT_LATCH_SET */ 2440 2440 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 2441 - #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4 2441 + #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04 2442 2442 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 2443 - #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3 2443 + #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03 2444 2444 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 2445 - #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2 2445 + #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02 2446 2446 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 2447 - #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1 2447 + #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01 2448 2448 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 2449 - #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0 2449 + #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00 2450 2450 2451 2451 /* Bit definitions for USB_ID_INT_LATCH_CLR */ 2452 2452 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 2453 - #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4 2453 + #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04 2454 2454 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 2455 - #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3 2455 + #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03 2456 2456 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 2457 - #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2 2457 + #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02 2458 2458 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 2459 - #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1 2459 + #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01 2460 2460 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 2461 - #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0 2461 + #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00 2462 2462 2463 2463 /* Bit definitions for USB_ID_INT_EN_LO_SET */ 2464 2464 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 2465 - #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4 2465 + #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04 2466 2466 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 2467 - #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3 2467 + #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03 2468 2468 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 2469 - #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2 2469 + #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02 2470 2470 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 2471 - #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1 2471 + #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01 2472 2472 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 2473 - #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0 2473 + #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00 2474 2474 2475 2475 /* Bit definitions for USB_ID_INT_EN_LO_CLR */ 2476 2476 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 2477 - #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4 2477 + #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04 2478 2478 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 2479 - #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3 2479 + #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03 2480 2480 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 2481 - #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2 2481 + #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02 2482 2482 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 2483 - #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1 2483 + #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01 2484 2484 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 2485 - #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0 2485 + #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00 2486 2486 2487 2487 /* Bit definitions for USB_ID_INT_EN_HI_SET */ 2488 2488 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 2489 - #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4 2489 + #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04 2490 2490 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 2491 - #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3 2491 + #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03 2492 2492 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 2493 - #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2 2493 + #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02 2494 2494 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 2495 - #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1 2495 + #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01 2496 2496 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 2497 - #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0 2497 + #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00 2498 2498 2499 2499 /* Bit definitions for USB_ID_INT_EN_HI_CLR */ 2500 2500 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 2501 - #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4 2501 + #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04 2502 2502 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 2503 - #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3 2503 + #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03 2504 2504 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 2505 - #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2 2505 + #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02 2506 2506 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 2507 - #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1 2507 + #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01 2508 2508 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 2509 - #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0 2509 + #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00 2510 2510 2511 2511 /* Bit definitions for USB_OTG_ADP_CTRL */ 2512 2512 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 2513 - #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2 2513 + #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02 2514 2514 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 2515 - #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0 2515 + #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00 2516 2516 2517 2517 /* Bit definitions for USB_OTG_ADP_HIGH */ 2518 - #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff 2519 - #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0 2518 + #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF 2519 + #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00 2520 2520 2521 2521 /* Bit definitions for USB_OTG_ADP_LOW */ 2522 - #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff 2523 - #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0 2522 + #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF 2523 + #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00 2524 2524 2525 2525 /* Bit definitions for USB_OTG_ADP_RISE */ 2526 - #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff 2527 - #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0 2526 + #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF 2527 + #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00 2528 2528 2529 2529 /* Bit definitions for USB_OTG_REVISION */ 2530 2530 #define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 2531 - #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0 2531 + #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00 2532 2532 2533 2533 /* Registers for function VIBRATOR */ 2534 - #define PALMAS_VIBRA_CTRL 0x0 2534 + #define PALMAS_VIBRA_CTRL 0x00 2535 2535 2536 2536 /* Bit definitions for VIBRA_CTRL */ 2537 2537 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 2538 - #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1 2538 + #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01 2539 2539 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 2540 - #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0 2540 + #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00 2541 2541 2542 2542 /* Registers for function GPIO */ 2543 - #define PALMAS_GPIO_DATA_IN 0x0 2544 - #define PALMAS_GPIO_DATA_DIR 0x1 2545 - #define PALMAS_GPIO_DATA_OUT 0x2 2546 - #define PALMAS_GPIO_DEBOUNCE_EN 0x3 2547 - #define PALMAS_GPIO_CLEAR_DATA_OUT 0x4 2548 - #define PALMAS_GPIO_SET_DATA_OUT 0x5 2549 - #define PALMAS_PU_PD_GPIO_CTRL1 0x6 2550 - #define PALMAS_PU_PD_GPIO_CTRL2 0x7 2551 - #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 2552 - #define PALMAS_GPIO_DATA_IN2 0x9 2543 + #define PALMAS_GPIO_DATA_IN 0x00 2544 + #define PALMAS_GPIO_DATA_DIR 0x01 2545 + #define PALMAS_GPIO_DATA_OUT 0x02 2546 + #define PALMAS_GPIO_DEBOUNCE_EN 0x03 2547 + #define PALMAS_GPIO_CLEAR_DATA_OUT 0x04 2548 + #define PALMAS_GPIO_SET_DATA_OUT 0x05 2549 + #define PALMAS_PU_PD_GPIO_CTRL1 0x06 2550 + #define PALMAS_PU_PD_GPIO_CTRL2 0x07 2551 + #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08 2552 + #define PALMAS_GPIO_DATA_IN2 0x09 2553 2553 #define PALMAS_GPIO_DATA_DIR2 0x0A 2554 2554 #define PALMAS_GPIO_DATA_OUT2 0x0B 2555 2555 #define PALMAS_GPIO_DEBOUNCE_EN2 0x0C ··· 2561 2561 2562 2562 /* Bit definitions for GPIO_DATA_IN */ 2563 2563 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2564 - #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7 2564 + #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07 2565 2565 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 2566 - #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6 2566 + #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06 2567 2567 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 2568 - #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5 2568 + #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05 2569 2569 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 2570 - #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4 2570 + #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04 2571 2571 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 2572 - #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3 2572 + #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03 2573 2573 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 2574 - #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2 2574 + #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02 2575 2575 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 2576 - #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1 2576 + #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01 2577 2577 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 2578 - #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0 2578 + #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00 2579 2579 2580 2580 /* Bit definitions for GPIO_DATA_DIR */ 2581 2581 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 2582 - #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7 2582 + #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07 2583 2583 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 2584 - #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6 2584 + #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06 2585 2585 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 2586 - #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5 2586 + #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05 2587 2587 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 2588 - #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4 2588 + #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04 2589 2589 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 2590 - #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3 2590 + #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03 2591 2591 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 2592 - #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2 2592 + #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02 2593 2593 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 2594 - #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1 2594 + #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01 2595 2595 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 2596 - #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0 2596 + #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00 2597 2597 2598 2598 /* Bit definitions for GPIO_DATA_OUT */ 2599 2599 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 2600 - #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7 2600 + #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07 2601 2601 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 2602 - #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6 2602 + #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06 2603 2603 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 2604 - #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5 2604 + #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05 2605 2605 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 2606 - #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4 2606 + #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04 2607 2607 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 2608 - #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3 2608 + #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03 2609 2609 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 2610 - #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2 2610 + #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02 2611 2611 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 2612 - #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1 2612 + #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01 2613 2613 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 2614 - #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0 2614 + #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00 2615 2615 2616 2616 /* Bit definitions for GPIO_DEBOUNCE_EN */ 2617 2617 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 2618 - #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7 2618 + #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07 2619 2619 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 2620 - #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6 2620 + #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06 2621 2621 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 2622 - #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5 2622 + #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05 2623 2623 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 2624 - #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4 2624 + #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04 2625 2625 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 2626 - #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3 2626 + #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03 2627 2627 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 2628 - #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2 2628 + #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02 2629 2629 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 2630 - #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1 2630 + #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01 2631 2631 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 2632 - #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0 2632 + #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00 2633 2633 2634 2634 /* Bit definitions for GPIO_CLEAR_DATA_OUT */ 2635 2635 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 2636 - #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7 2636 + #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07 2637 2637 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 2638 - #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6 2638 + #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06 2639 2639 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 2640 - #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5 2640 + #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05 2641 2641 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 2642 - #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4 2642 + #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04 2643 2643 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 2644 - #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3 2644 + #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03 2645 2645 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 2646 - #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2 2646 + #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02 2647 2647 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 2648 - #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1 2648 + #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01 2649 2649 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 2650 - #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0 2650 + #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00 2651 2651 2652 2652 /* Bit definitions for GPIO_SET_DATA_OUT */ 2653 2653 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 2654 - #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7 2654 + #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07 2655 2655 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 2656 - #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6 2656 + #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06 2657 2657 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 2658 - #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5 2658 + #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05 2659 2659 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 2660 - #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4 2660 + #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04 2661 2661 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 2662 - #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3 2662 + #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03 2663 2663 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 2664 - #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2 2664 + #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02 2665 2665 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 2666 - #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1 2666 + #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01 2667 2667 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 2668 - #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0 2668 + #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00 2669 2669 2670 2670 /* Bit definitions for PU_PD_GPIO_CTRL1 */ 2671 2671 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 2672 - #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6 2672 + #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06 2673 2673 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 2674 - #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5 2674 + #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05 2675 2675 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 2676 - #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4 2676 + #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04 2677 2677 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 2678 - #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3 2678 + #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03 2679 2679 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 2680 - #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2 2680 + #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02 2681 2681 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 2682 - #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0 2682 + #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00 2683 2683 2684 2684 /* Bit definitions for PU_PD_GPIO_CTRL2 */ 2685 2685 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 2686 - #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6 2686 + #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06 2687 2687 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 2688 - #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5 2688 + #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05 2689 2689 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 2690 - #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4 2690 + #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04 2691 2691 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 2692 - #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3 2692 + #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03 2693 2693 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 2694 - #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2 2694 + #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02 2695 2695 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 2696 - #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1 2696 + #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01 2697 2697 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 2698 - #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0 2698 + #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00 2699 2699 2700 2700 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */ 2701 2701 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 2702 - #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5 2702 + #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05 2703 2703 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 2704 - #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2 2704 + #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02 2705 2705 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 2706 - #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1 2706 + #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01 2707 2707 2708 2708 /* Registers for function GPADC */ 2709 - #define PALMAS_GPADC_CTRL1 0x0 2710 - #define PALMAS_GPADC_CTRL2 0x1 2711 - #define PALMAS_GPADC_RT_CTRL 0x2 2712 - #define PALMAS_GPADC_AUTO_CTRL 0x3 2713 - #define PALMAS_GPADC_STATUS 0x4 2714 - #define PALMAS_GPADC_RT_SELECT 0x5 2715 - #define PALMAS_GPADC_RT_CONV0_LSB 0x6 2716 - #define PALMAS_GPADC_RT_CONV0_MSB 0x7 2717 - #define PALMAS_GPADC_AUTO_SELECT 0x8 2718 - #define PALMAS_GPADC_AUTO_CONV0_LSB 0x9 2719 - #define PALMAS_GPADC_AUTO_CONV0_MSB 0xA 2720 - #define PALMAS_GPADC_AUTO_CONV1_LSB 0xB 2721 - #define PALMAS_GPADC_AUTO_CONV1_MSB 0xC 2722 - #define PALMAS_GPADC_SW_SELECT 0xD 2723 - #define PALMAS_GPADC_SW_CONV0_LSB 0xE 2724 - #define PALMAS_GPADC_SW_CONV0_MSB 0xF 2709 + #define PALMAS_GPADC_CTRL1 0x00 2710 + #define PALMAS_GPADC_CTRL2 0x01 2711 + #define PALMAS_GPADC_RT_CTRL 0x02 2712 + #define PALMAS_GPADC_AUTO_CTRL 0x03 2713 + #define PALMAS_GPADC_STATUS 0x04 2714 + #define PALMAS_GPADC_RT_SELECT 0x05 2715 + #define PALMAS_GPADC_RT_CONV0_LSB 0x06 2716 + #define PALMAS_GPADC_RT_CONV0_MSB 0x07 2717 + #define PALMAS_GPADC_AUTO_SELECT 0x08 2718 + #define PALMAS_GPADC_AUTO_CONV0_LSB 0x09 2719 + #define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A 2720 + #define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B 2721 + #define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C 2722 + #define PALMAS_GPADC_SW_SELECT 0x0D 2723 + #define PALMAS_GPADC_SW_CONV0_LSB 0x0E 2724 + #define PALMAS_GPADC_SW_CONV0_MSB 0x0F 2725 2725 #define PALMAS_GPADC_THRES_CONV0_LSB 0x10 2726 2726 #define PALMAS_GPADC_THRES_CONV0_MSB 0x11 2727 2727 #define PALMAS_GPADC_THRES_CONV1_LSB 0x12 ··· 2731 2731 2732 2732 /* Bit definitions for GPADC_CTRL1 */ 2733 2733 #define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 2734 - #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6 2734 + #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06 2735 2735 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 2736 - #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4 2736 + #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04 2737 2737 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c 2738 - #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2 2738 + #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02 2739 2739 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 2740 - #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1 2740 + #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01 2741 2741 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 2742 - #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0 2742 + #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00 2743 2743 2744 2744 /* Bit definitions for GPADC_CTRL2 */ 2745 2745 #define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 2746 - #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1 2746 + #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01 2747 2747 2748 2748 /* Bit definitions for GPADC_RT_CTRL */ 2749 2749 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 2750 - #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1 2750 + #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01 2751 2751 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 2752 - #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0 2752 + #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00 2753 2753 2754 2754 /* Bit definitions for GPADC_AUTO_CTRL */ 2755 2755 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 2756 - #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7 2756 + #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07 2757 2757 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 2758 - #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6 2758 + #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06 2759 2759 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 2760 - #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5 2760 + #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05 2761 2761 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 2762 - #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4 2763 - #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f 2764 - #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0 2762 + #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04 2763 + #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F 2764 + #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00 2765 2765 2766 2766 /* Bit definitions for GPADC_STATUS */ 2767 2767 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 2768 - #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4 2768 + #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04 2769 2769 2770 2770 /* Bit definitions for GPADC_RT_SELECT */ 2771 2771 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 2772 - #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7 2773 - #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f 2774 - #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0 2772 + #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07 2773 + #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F 2774 + #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00 2775 2775 2776 2776 /* Bit definitions for GPADC_RT_CONV0_LSB */ 2777 - #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff 2778 - #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0 2777 + #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF 2778 + #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00 2779 2779 2780 2780 /* Bit definitions for GPADC_RT_CONV0_MSB */ 2781 - #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f 2782 - #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0 2781 + #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F 2782 + #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00 2783 2783 2784 2784 /* Bit definitions for GPADC_AUTO_SELECT */ 2785 - #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0 2786 - #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4 2787 - #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f 2788 - #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0 2785 + #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0 2786 + #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04 2787 + #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F 2788 + #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00 2789 2789 2790 2790 /* Bit definitions for GPADC_AUTO_CONV0_LSB */ 2791 - #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff 2792 - #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0 2791 + #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF 2792 + #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00 2793 2793 2794 2794 /* Bit definitions for GPADC_AUTO_CONV0_MSB */ 2795 - #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f 2796 - #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0 2795 + #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F 2796 + #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00 2797 2797 2798 2798 /* Bit definitions for GPADC_AUTO_CONV1_LSB */ 2799 - #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff 2800 - #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0 2799 + #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF 2800 + #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00 2801 2801 2802 2802 /* Bit definitions for GPADC_AUTO_CONV1_MSB */ 2803 - #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f 2804 - #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0 2803 + #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F 2804 + #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00 2805 2805 2806 2806 /* Bit definitions for GPADC_SW_SELECT */ 2807 2807 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 2808 - #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7 2808 + #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07 2809 2809 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 2810 - #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4 2811 - #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f 2812 - #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0 2810 + #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04 2811 + #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F 2812 + #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00 2813 2813 2814 2814 /* Bit definitions for GPADC_SW_CONV0_LSB */ 2815 - #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff 2816 - #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0 2815 + #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF 2816 + #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00 2817 2817 2818 2818 /* Bit definitions for GPADC_SW_CONV0_MSB */ 2819 - #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f 2820 - #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0 2819 + #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F 2820 + #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00 2821 2821 2822 2822 /* Bit definitions for GPADC_THRES_CONV0_LSB */ 2823 - #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff 2824 - #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0 2823 + #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF 2824 + #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00 2825 2825 2826 2826 /* Bit definitions for GPADC_THRES_CONV0_MSB */ 2827 2827 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 2828 - #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7 2829 - #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f 2830 - #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0 2828 + #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07 2829 + #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F 2830 + #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00 2831 2831 2832 2832 /* Bit definitions for GPADC_THRES_CONV1_LSB */ 2833 - #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff 2834 - #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0 2833 + #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF 2834 + #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00 2835 2835 2836 2836 /* Bit definitions for GPADC_THRES_CONV1_MSB */ 2837 2837 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 2838 - #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7 2839 - #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f 2840 - #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0 2838 + #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07 2839 + #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F 2840 + #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00 2841 2841 2842 2842 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ 2843 2843 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 2844 - #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5 2844 + #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05 2845 2845 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 2846 - #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4 2847 - #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f 2848 - #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0 2846 + #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04 2847 + #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F 2848 + #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00 2849 2849 2850 2850 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ 2851 2851 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 2852 - #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7 2853 - #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f 2854 - #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0 2852 + #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07 2853 + #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F 2854 + #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00 2855 2855 2856 2856 /* Registers for function GPADC */ 2857 - #define PALMAS_GPADC_TRIM1 0x0 2858 - #define PALMAS_GPADC_TRIM2 0x1 2859 - #define PALMAS_GPADC_TRIM3 0x2 2860 - #define PALMAS_GPADC_TRIM4 0x3 2861 - #define PALMAS_GPADC_TRIM5 0x4 2862 - #define PALMAS_GPADC_TRIM6 0x5 2863 - #define PALMAS_GPADC_TRIM7 0x6 2864 - #define PALMAS_GPADC_TRIM8 0x7 2865 - #define PALMAS_GPADC_TRIM9 0x8 2866 - #define PALMAS_GPADC_TRIM10 0x9 2867 - #define PALMAS_GPADC_TRIM11 0xA 2868 - #define PALMAS_GPADC_TRIM12 0xB 2869 - #define PALMAS_GPADC_TRIM13 0xC 2870 - #define PALMAS_GPADC_TRIM14 0xD 2871 - #define PALMAS_GPADC_TRIM15 0xE 2872 - #define PALMAS_GPADC_TRIM16 0xF 2857 + #define PALMAS_GPADC_TRIM1 0x00 2858 + #define PALMAS_GPADC_TRIM2 0x01 2859 + #define PALMAS_GPADC_TRIM3 0x02 2860 + #define PALMAS_GPADC_TRIM4 0x03 2861 + #define PALMAS_GPADC_TRIM5 0x04 2862 + #define PALMAS_GPADC_TRIM6 0x05 2863 + #define PALMAS_GPADC_TRIM7 0x06 2864 + #define PALMAS_GPADC_TRIM8 0x07 2865 + #define PALMAS_GPADC_TRIM9 0x08 2866 + #define PALMAS_GPADC_TRIM10 0x09 2867 + #define PALMAS_GPADC_TRIM11 0x0A 2868 + #define PALMAS_GPADC_TRIM12 0x0B 2869 + #define PALMAS_GPADC_TRIM13 0x0C 2870 + #define PALMAS_GPADC_TRIM14 0x0D 2871 + #define PALMAS_GPADC_TRIM15 0x0E 2872 + #define PALMAS_GPADC_TRIM16 0x0F 2873 2873 2874 2874 static inline int palmas_read(struct palmas *palmas, unsigned int base, 2875 2875 unsigned int reg, unsigned int *val) 2876 2876 { 2877 - unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2877 + unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2878 2878 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2879 2879 2880 2880 return regmap_read(palmas->regmap[slave_id], addr, val);