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Merge branch 'net-stmmac-convert-meson8b-to-use-stmmac_get_phy_intf_sel'

Russell King says:

====================
net: stmmac: convert meson8b to use stmmac_get_phy_intf_sel()

This series splits out meson8b from the previous 16 patch series
as that now has r-b tags.

This series converts meson8b to use stmmac_get_phy_intf_sel(). This
driver is not converted to the set_phy_intf_sel() method as it is
unclear whether there are ordering dependencies that would prevent
it. I would appreciate the driver author looking in to whether this
conversion is possible.
====================

Link: https://patch.msgid.link/aRH50uVDX4_9O5ZU@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

+10 -20
+10 -20
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
··· 26 26 #define PRG_ETH0_RGMII_MODE BIT(0) 27 27 28 28 #define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) 29 - #define PRG_ETH0_EXT_RGMII_MODE 1 30 - #define PRG_ETH0_EXT_RMII_MODE 4 31 29 32 30 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ 33 31 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) ··· 236 238 237 239 static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac) 238 240 { 239 - switch (dwmac->phy_mode) { 240 - case PHY_INTERFACE_MODE_RGMII: 241 - case PHY_INTERFACE_MODE_RGMII_RXID: 242 - case PHY_INTERFACE_MODE_RGMII_ID: 243 - case PHY_INTERFACE_MODE_RGMII_TXID: 244 - /* enable RGMII mode */ 245 - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 246 - PRG_ETH0_EXT_PHY_MODE_MASK, 247 - PRG_ETH0_EXT_RGMII_MODE); 248 - break; 249 - case PHY_INTERFACE_MODE_RMII: 250 - /* disable RGMII mode -> enables RMII mode */ 251 - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 252 - PRG_ETH0_EXT_PHY_MODE_MASK, 253 - PRG_ETH0_EXT_RMII_MODE); 254 - break; 255 - default: 241 + int phy_intf_sel; 242 + 243 + phy_intf_sel = stmmac_get_phy_intf_sel(dwmac->phy_mode); 244 + if (phy_intf_sel != PHY_INTF_SEL_RGMII && 245 + phy_intf_sel != PHY_INTF_SEL_RMII) { 256 246 dev_err(dwmac->dev, "fail to set phy-mode %s\n", 257 247 phy_modes(dwmac->phy_mode)); 258 - return -EINVAL; 248 + return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; 259 249 } 250 + 251 + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_EXT_PHY_MODE_MASK, 252 + FIELD_PREP(PRG_ETH0_EXT_PHY_MODE_MASK, 253 + phy_intf_sel)); 260 254 261 255 return 0; 262 256 }