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ARM: dts: imx6ul: segin: Reduce eth drive strength

Reduce the drive strength for the MDC, MDIO and TX pins of FEC1 and FEC2
on the phyBOARD-Segin to improve signal quality and EMC. Also disable
internal pull-ups on the MDC and MDIO pins.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

authored by

Stefan Riedmueller and committed by
Shawn Guo 45826415 e37816bf

+10 -10
+6 -6
arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
··· 93 93 &iomuxc { 94 94 pinctrl_enet1: enet1grp { 95 95 fsl,pins = < 96 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 97 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 96 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010 97 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010 98 98 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 99 99 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 100 100 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 101 101 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 102 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 103 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 104 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 105 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 102 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 103 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 104 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 105 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 106 106 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059 107 107 >; 108 108 };
+4 -4
arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
··· 230 230 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 231 231 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 232 232 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 233 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 234 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 235 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 236 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 233 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 234 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 235 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 236 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 237 237 >; 238 238 }; 239 239