tjh.dev / kernel
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kernel os linux
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phy: usb: suppress OC condition for 7439b2

We hit a false positive OC for 7439b2 in DRD/device mode for the
second port. So disable the OC check for this use case. Add capability
to suppress OC condition for specific ports.

Signed-off-by: Justin Chen <justin.chen@broadcom.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/r/1686859578-45242-3-git-send-email-justin.chen@broadcom.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Justin Chen and committed by
Vinod Koul 4536fe96 5095d045

+34
+34
drivers/phy/broadcom/phy-brcm-usb-init.c
··· 35 35 #define USB_CTRL_SETUP_STRAP_IPP_SEL_MASK BIT(25) /* option */ 36 36 #define USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK BIT(26) /* option */ 37 37 #define USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK BIT(27) /* opt */ 38 + #define USB_CTRL_SETUP_OC_DISABLE_PORT0_MASK BIT(28) 39 + #define USB_CTRL_SETUP_OC_DISABLE_PORT1_MASK BIT(29) 40 + #define USB_CTRL_SETUP_OC_DISABLE_MASK GENMASK(29, 28) /* option */ 41 + #define USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK BIT(30) 42 + #define USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK BIT(31) 38 43 #define USB_CTRL_SETUP_OC3_DISABLE_MASK GENMASK(31, 30) /* option */ 39 44 #define USB_CTRL_PLL_CTL 0x04 40 45 #define USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK BIT(27) ··· 119 114 USB_CTRL_SETUP_SCB2_EN_SELECTOR, 120 115 USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR, 121 116 USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR, 117 + USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR, 118 + USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR, 122 119 USB_CTRL_SETUP_OC3_DISABLE_SELECTOR, 123 120 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR, 124 121 USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR, ··· 197 190 USB_CTRL_SETUP_SCB2_EN_MASK, 198 191 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 199 192 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 193 + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, 194 + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, 200 195 USB_CTRL_SETUP_OC3_DISABLE_MASK, 201 196 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 202 197 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ ··· 241 232 USB_CTRL_SETUP_SCB2_EN_MASK, 242 233 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 243 234 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 235 + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, 236 + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, 244 237 USB_CTRL_SETUP_OC3_DISABLE_MASK, 245 238 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 246 239 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ ··· 264 253 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ 265 254 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 266 255 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 256 + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, 257 + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, 267 258 USB_CTRL_SETUP_OC3_DISABLE_MASK, 268 259 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 269 260 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, ··· 287 274 USB_CTRL_SETUP_SCB2_EN_MASK, 288 275 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 289 276 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 277 + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, 278 + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, 290 279 USB_CTRL_SETUP_OC3_DISABLE_MASK, 291 280 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 292 281 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ ··· 310 295 USB_CTRL_SETUP_SCB2_EN_MASK, 311 296 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 312 297 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 298 + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, 299 + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, 313 300 USB_CTRL_SETUP_OC3_DISABLE_MASK, 314 301 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 315 302 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ ··· 333 316 USB_CTRL_SETUP_SCB2_EN_MASK, 334 317 USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK, 335 318 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 319 + 0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK */ 320 + 0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK */ 336 321 0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */ 337 322 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 338 323 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ ··· 356 337 USB_CTRL_SETUP_SCB2_EN_MASK, 357 338 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 358 339 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 340 + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, 341 + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, 359 342 USB_CTRL_SETUP_OC3_DISABLE_MASK, 360 343 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 361 344 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, ··· 379 358 USB_CTRL_SETUP_SCB2_EN_MASK, 380 359 USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK, 381 360 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 361 + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, 362 + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, 382 363 USB_CTRL_SETUP_OC3_DISABLE_MASK, 383 364 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 384 365 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ ··· 402 379 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ 403 380 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 404 381 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 382 + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, 383 + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, 405 384 USB_CTRL_SETUP_OC3_DISABLE_MASK, 406 385 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 407 386 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, ··· 425 400 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ 426 401 0, /*USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */ 427 402 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 403 + USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK, 404 + USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK, 428 405 USB_CTRL_SETUP_OC3_DISABLE_MASK, 429 406 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 430 407 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, ··· 898 871 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP)); 899 872 900 873 brcmusb_memc_fix(params); 874 + 875 + /* Workaround for false positive OC for 7439b2 in DRD/Device mode */ 876 + if ((params->family_id == 0x74390012) && 877 + (params->supported_port_modes != USB_CTLR_MODE_HOST)) { 878 + USB_CTRL_SET(ctrl, SETUP, OC_DISABLE_PORT1); 879 + USB_CTRL_SET_FAMILY(params, SETUP, OC3_DISABLE_PORT1); 880 + } 901 881 902 882 if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) { 903 883 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));