tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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ARM: Orion: mbus_dram_info consolidation

Move the *_mbus_dram_info structure into the orion platform and call it
orion_mbus_dram_info everywhere.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Michael Walle <michael@walle.cc>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>

authored by

Andrew Lunn and committed by
Nicolas Pitre 45173d5e b6d1c33a

+50 -55
+3 -5
arch/arm/mach-dove/addr-map.c
··· 35 35 #define ATTR_PCIE_MEM 0xe8 36 36 #define ATTR_SCRATCHPAD 0x0 37 37 38 - struct mbus_dram_target_info dove_mbus_dram_info; 39 - 40 38 static inline void __iomem *ddr_map_sc(int i) 41 39 { 42 40 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); ··· 100 102 /* 101 103 * Setup MBUS dram target info. 102 104 */ 103 - dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 105 + orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 104 106 105 107 for (i = 0, cs = 0; i < 2; i++) { 106 108 u32 map = readl(ddr_map_sc(i)); ··· 111 113 if (map & 1) { 112 114 struct mbus_dram_window *w; 113 115 114 - w = &dove_mbus_dram_info.cs[cs++]; 116 + w = &orion_mbus_dram_info.cs[cs++]; 115 117 w->cs_index = i; 116 118 w->mbus_attr = 0; /* CS address decoding done inside */ 117 119 /* the DDR controller, no need to */ ··· 120 122 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); 121 123 } 122 124 } 123 - dove_mbus_dram_info.num_cs = cs; 125 + orion_mbus_dram_info.num_cs = cs; 124 126 }
+6 -5
arch/arm/mach-dove/common.c
··· 30 30 #include <linux/irq.h> 31 31 #include <plat/time.h> 32 32 #include <plat/common.h> 33 + #include <plat/addr-map.h> 33 34 #include "common.h" 34 35 35 36 static int get_tclk(void); ··· 72 71 ****************************************************************************/ 73 72 void __init dove_ehci0_init(void) 74 73 { 75 - orion_ehci_init(&dove_mbus_dram_info, 74 + orion_ehci_init(&orion_mbus_dram_info, 76 75 DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); 77 76 } 78 77 ··· 81 80 ****************************************************************************/ 82 81 void __init dove_ehci1_init(void) 83 82 { 84 - orion_ehci_1_init(&dove_mbus_dram_info, 83 + orion_ehci_1_init(&orion_mbus_dram_info, 85 84 DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); 86 85 } 87 86 ··· 90 89 ****************************************************************************/ 91 90 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 92 91 { 93 - orion_ge00_init(eth_data, &dove_mbus_dram_info, 92 + orion_ge00_init(eth_data, &orion_mbus_dram_info, 94 93 DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, 95 94 0, get_tclk()); 96 95 } ··· 108 107 ****************************************************************************/ 109 108 void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 110 109 { 111 - orion_sata_init(sata_data, &dove_mbus_dram_info, 110 + orion_sata_init(sata_data, &orion_mbus_dram_info, 112 111 DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); 113 112 114 113 } ··· 199 198 ****************************************************************************/ 200 199 void __init dove_xor0_init(void) 201 200 { 202 - orion_xor0_init(&dove_mbus_dram_info, 201 + orion_xor0_init(&orion_mbus_dram_info, 203 202 DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, 204 203 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); 205 204 }
-1
arch/arm/mach-dove/common.h
··· 15 15 struct mv_sata_platform_data; 16 16 17 17 extern struct sys_timer dove_timer; 18 - extern struct mbus_dram_target_info dove_mbus_dram_info; 19 18 20 19 /* 21 20 * Basic Dove init functions used early by machine-setup.
+2 -1
arch/arm/mach-dove/pcie.c
··· 19 19 #include <plat/pcie.h> 20 20 #include <mach/irqs.h> 21 21 #include <mach/bridge-regs.h> 22 + #include <plat/addr-map.h> 22 23 #include "common.h" 23 24 24 25 struct pcie_port { ··· 51 50 */ 52 51 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 53 52 54 - orion_pcie_setup(pp->base, &dove_mbus_dram_info); 53 + orion_pcie_setup(pp->base, &orion_mbus_dram_info); 55 54 56 55 /* 57 56 * IORESOURCE_IO
+1 -4
arch/arm/mach-kirkwood/addr-map.c
··· 35 35 #define ATTR_PCIE1_MEM 0xd8 36 36 #define ATTR_SRAM 0x01 37 37 38 - struct mbus_dram_target_info kirkwood_mbus_dram_info; 39 - 40 38 /* 41 39 * Description of the windows needed by the platform code 42 40 */ ··· 86 88 /* 87 89 * Setup MBUS dram target info. 88 90 */ 89 - orion_setup_cpu_mbus_target(&addr_map_cfg, &kirkwood_mbus_dram_info, 90 - DDR_WINDOW_CPU_BASE); 91 + orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE); 91 92 }
+8 -7
arch/arm/mach-kirkwood/common.c
··· 30 30 #include <plat/orion_nand.h> 31 31 #include <plat/common.h> 32 32 #include <plat/time.h> 33 + #include <plat/addr-map.h> 33 34 #include "common.h" 34 35 35 36 /***************************************************************************** ··· 74 73 void __init kirkwood_ehci_init(void) 75 74 { 76 75 kirkwood_clk_ctrl |= CGC_USB0; 77 - orion_ehci_init(&kirkwood_mbus_dram_info, 76 + orion_ehci_init(&orion_mbus_dram_info, 78 77 USB_PHYS_BASE, IRQ_KIRKWOOD_USB); 79 78 } 80 79 ··· 86 85 { 87 86 kirkwood_clk_ctrl |= CGC_GE0; 88 87 89 - orion_ge00_init(eth_data, &kirkwood_mbus_dram_info, 88 + orion_ge00_init(eth_data, &orion_mbus_dram_info, 90 89 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, 91 90 IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk); 92 91 } ··· 100 99 101 100 kirkwood_clk_ctrl |= CGC_GE1; 102 101 103 - orion_ge01_init(eth_data, &kirkwood_mbus_dram_info, 102 + orion_ge01_init(eth_data, &orion_mbus_dram_info, 104 103 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, 105 104 IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk); 106 105 } ··· 179 178 if (sata_data->n_ports > 1) 180 179 kirkwood_clk_ctrl |= CGC_SATA1; 181 180 182 - orion_sata_init(sata_data, &kirkwood_mbus_dram_info, 181 + orion_sata_init(sata_data, &orion_mbus_dram_info, 183 182 SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); 184 183 } 185 184 ··· 222 221 mvsdio_data->clock = 100000000; 223 222 else 224 223 mvsdio_data->clock = 200000000; 225 - mvsdio_data->dram = &kirkwood_mbus_dram_info; 224 + mvsdio_data->dram = &orion_mbus_dram_info; 226 225 kirkwood_clk_ctrl |= CGC_SDIO; 227 226 kirkwood_sdio.dev.platform_data = mvsdio_data; 228 227 platform_device_register(&kirkwood_sdio); ··· 286 285 { 287 286 kirkwood_clk_ctrl |= CGC_XOR0; 288 287 289 - orion_xor0_init(&kirkwood_mbus_dram_info, 288 + orion_xor0_init(&orion_mbus_dram_info, 290 289 XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, 291 290 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); 292 291 } ··· 365 364 }; 366 365 367 366 static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { 368 - .dram = &kirkwood_mbus_dram_info, 367 + .dram = &orion_mbus_dram_info, 369 368 .burst = 128, 370 369 }; 371 370
-1
arch/arm/mach-kirkwood/common.h
··· 30 30 void kirkwood_init_early(void); 31 31 void kirkwood_init_irq(void); 32 32 33 - extern struct mbus_dram_target_info kirkwood_mbus_dram_info; 34 33 void kirkwood_setup_cpu_mbus(void); 35 34 36 35 void kirkwood_enable_pcie(void);
+2 -1
arch/arm/mach-kirkwood/pcie.c
··· 17 17 #include <asm/mach/pci.h> 18 18 #include <plat/pcie.h> 19 19 #include <mach/bridge-regs.h> 20 + #include <plat/addr-map.h> 20 21 #include "common.h" 21 22 22 23 void kirkwood_enable_pcie(void) ··· 209 208 */ 210 209 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 211 210 212 - orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info); 211 + orion_pcie_setup(pp->base, &orion_mbus_dram_info); 213 212 214 213 return 1; 215 214 }
-4
arch/arm/mach-mv78xx0/addr-map.c
··· 37 37 #define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) 38 38 #define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) 39 39 40 - struct mbus_dram_target_info mv78xx0_mbus_dram_info; 41 - 42 40 static void __init __iomem *win_cfg_base(int win) 43 41 { 44 42 /* ··· 71 73 */ 72 74 if (mv78xx0_core_index() == 0) 73 75 orion_setup_cpu_mbus_target(&addr_map_cfg, 74 - &mv78xx0_mbus_dram_info, 75 76 DDR_WINDOW_CPU0_BASE); 76 77 else 77 78 orion_setup_cpu_mbus_target(&addr_map_cfg, 78 - &mv78xx0_mbus_dram_info, 79 79 DDR_WINDOW_CPU1_BASE); 80 80 } 81 81
+9 -8
arch/arm/mach-mv78xx0/common.c
··· 23 23 #include <plat/orion_nand.h> 24 24 #include <plat/time.h> 25 25 #include <plat/common.h> 26 + #include <plat/addr-map.h> 26 27 #include "common.h" 27 28 28 29 static int get_tclk(void); ··· 170 169 ****************************************************************************/ 171 170 void __init mv78xx0_ehci0_init(void) 172 171 { 173 - orion_ehci_init(&mv78xx0_mbus_dram_info, 172 + orion_ehci_init(&orion_mbus_dram_info, 174 173 USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); 175 174 } 176 175 ··· 180 179 ****************************************************************************/ 181 180 void __init mv78xx0_ehci1_init(void) 182 181 { 183 - orion_ehci_1_init(&mv78xx0_mbus_dram_info, 182 + orion_ehci_1_init(&orion_mbus_dram_info, 184 183 USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); 185 184 } 186 185 ··· 190 189 ****************************************************************************/ 191 190 void __init mv78xx0_ehci2_init(void) 192 191 { 193 - orion_ehci_2_init(&mv78xx0_mbus_dram_info, 192 + orion_ehci_2_init(&orion_mbus_dram_info, 194 193 USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); 195 194 } 196 195 ··· 200 199 ****************************************************************************/ 201 200 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) 202 201 { 203 - orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info, 202 + orion_ge00_init(eth_data, &orion_mbus_dram_info, 204 203 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, 205 204 IRQ_MV78XX0_GE_ERR, get_tclk()); 206 205 } ··· 211 210 ****************************************************************************/ 212 211 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) 213 212 { 214 - orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info, 213 + orion_ge01_init(eth_data, &orion_mbus_dram_info, 215 214 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, 216 215 NO_IRQ, get_tclk()); 217 216 } ··· 235 234 eth_data->duplex = DUPLEX_FULL; 236 235 } 237 236 238 - orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info, 237 + orion_ge10_init(eth_data, &orion_mbus_dram_info, 239 238 GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, 240 239 NO_IRQ, get_tclk()); 241 240 } ··· 259 258 eth_data->duplex = DUPLEX_FULL; 260 259 } 261 260 262 - orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info, 261 + orion_ge11_init(eth_data, &orion_mbus_dram_info, 263 262 GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, 264 263 NO_IRQ, get_tclk()); 265 264 } ··· 278 277 ****************************************************************************/ 279 278 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) 280 279 { 281 - orion_sata_init(sata_data, &mv78xx0_mbus_dram_info, 280 + orion_sata_init(sata_data, &orion_mbus_dram_info, 282 281 SATA_PHYS_BASE, IRQ_MV78XX0_SATA); 283 282 } 284 283
-1
arch/arm/mach-mv78xx0/common.h
··· 23 23 void mv78xx0_init_early(void); 24 24 void mv78xx0_init_irq(void); 25 25 26 - extern struct mbus_dram_target_info mv78xx0_mbus_dram_info; 27 26 void mv78xx0_setup_cpu_mbus(void); 28 27 void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, 29 28 int maj, int min);
+2 -1
arch/arm/mach-mv78xx0/pcie.c
··· 15 15 #include <asm/irq.h> 16 16 #include <asm/mach/pci.h> 17 17 #include <plat/pcie.h> 18 + #include <plat/addr-map.h> 18 19 #include "common.h" 19 20 20 21 struct pcie_port { ··· 154 153 * Generic PCIe unit setup. 155 154 */ 156 155 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 157 - orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info); 156 + orion_pcie_setup(pp->base, &orion_mbus_dram_info); 158 157 159 158 sys->resource[0] = &pp->res[0]; 160 159 sys->resource[1] = &pp->res[1];
+1 -3
arch/arm/mach-orion5x/addr-map.c
··· 56 56 #define ATTR_DEV_BOOT 0xf 57 57 #define ATTR_SRAM 0x0 58 58 59 - struct mbus_dram_target_info orion5x_mbus_dram_info; 60 59 static int __initdata win_alloc_count; 61 60 62 61 static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, ··· 113 114 /* 114 115 * Setup MBUS dram target info. 115 116 */ 116 - orion_setup_cpu_mbus_target(&addr_map_cfg, &orion5x_mbus_dram_info, 117 - ORION5X_DDR_WINDOW_CPU_BASE); 117 + orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE); 118 118 } 119 119 120 120 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
+6 -5
arch/arm/mach-orion5x/common.c
··· 31 31 #include <plat/orion_nand.h> 32 32 #include <plat/time.h> 33 33 #include <plat/common.h> 34 + #include <plat/addr-map.h> 34 35 #include "common.h" 35 36 36 37 /***************************************************************************** ··· 72 71 ****************************************************************************/ 73 72 void __init orion5x_ehci0_init(void) 74 73 { 75 - orion_ehci_init(&orion5x_mbus_dram_info, 74 + orion_ehci_init(&orion_mbus_dram_info, 76 75 ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); 77 76 } 78 77 ··· 82 81 ****************************************************************************/ 83 82 void __init orion5x_ehci1_init(void) 84 83 { 85 - orion_ehci_1_init(&orion5x_mbus_dram_info, 84 + orion_ehci_1_init(&orion_mbus_dram_info, 86 85 ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); 87 86 } 88 87 ··· 92 91 ****************************************************************************/ 93 92 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) 94 93 { 95 - orion_ge00_init(eth_data, &orion5x_mbus_dram_info, 94 + orion_ge00_init(eth_data, &orion_mbus_dram_info, 96 95 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, 97 96 IRQ_ORION5X_ETH_ERR, orion5x_tclk); 98 97 } ··· 122 121 ****************************************************************************/ 123 122 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) 124 123 { 125 - orion_sata_init(sata_data, &orion5x_mbus_dram_info, 124 + orion_sata_init(sata_data, &orion_mbus_dram_info, 126 125 ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); 127 126 } 128 127 ··· 159 158 ****************************************************************************/ 160 159 void __init orion5x_xor_init(void) 161 160 { 162 - orion_xor0_init(&orion5x_mbus_dram_info, 161 + orion_xor0_init(&orion_mbus_dram_info, 163 162 ORION5X_XOR_PHYS_BASE, 164 163 ORION5X_XOR_PHYS_BASE + 0x200, 165 164 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
-1
arch/arm/mach-orion5x/common.h
··· 20 20 * functions to map its interfaces and by the machine-setup to map its on- 21 21 * board devices. Details in /mach-orion/addr-map.c 22 22 */ 23 - extern struct mbus_dram_target_info orion5x_mbus_dram_info; 24 23 void orion5x_setup_cpu_mbus_bridge(void); 25 24 void orion5x_setup_dev_boot_win(u32 base, u32 size); 26 25 void orion5x_setup_dev0_win(u32 base, u32 size);
+3 -2
arch/arm/mach-orion5x/pci.c
··· 18 18 #include <asm/irq.h> 19 19 #include <asm/mach/pci.h> 20 20 #include <plat/pcie.h> 21 + #include <plat/addr-map.h> 21 22 #include "common.h" 22 23 23 24 /***************************************************************************** ··· 146 145 /* 147 146 * Generic PCIe unit setup. 148 147 */ 149 - orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); 148 + orion_pcie_setup(PCIE_BASE, &orion_mbus_dram_info); 150 149 151 150 /* 152 151 * Check whether to apply Orion-1/Orion-NAS PCIe config ··· 478 477 /* 479 478 * Point PCI unit MBUS decode windows to DRAM space. 480 479 */ 481 - orion5x_setup_pci_wins(&orion5x_mbus_dram_info); 480 + orion5x_setup_pci_wins(&orion_mbus_dram_info); 482 481 483 482 /* 484 483 * Master + Slave enable
+5 -4
arch/arm/plat-orion/addr-map.c
··· 14 14 #include <linux/io.h> 15 15 #include <plat/addr-map.h> 16 16 17 + struct mbus_dram_target_info orion_mbus_dram_info; 18 + 17 19 /* 18 20 * DDR target is the same on all Orion platforms. 19 21 */ ··· 136 134 * Setup MBUS dram target info. 137 135 */ 138 136 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, 139 - struct mbus_dram_target_info *info, 140 137 const u32 ddr_window_cpu_base) 141 138 { 142 139 void __iomem *addr; 143 140 int i; 144 141 int cs; 145 142 146 - info->mbus_dram_target_id = TARGET_DDR; 143 + orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 147 144 148 145 addr = (void __iomem *)ddr_window_cpu_base; 149 146 ··· 156 155 if (size & 1) { 157 156 struct mbus_dram_window *w; 158 157 159 - w = &info->cs[cs++]; 158 + w = &orion_mbus_dram_info.cs[cs++]; 160 159 w->cs_index = i; 161 160 w->mbus_attr = 0xf & ~(1 << i); 162 161 w->base = base & 0xffff0000; 163 162 w->size = (size | 0x0000ffff) + 1; 164 163 } 165 164 } 166 - info->num_cs = cs; 165 + orion_mbus_dram_info.num_cs = cs; 167 166 }
+2 -1
arch/arm/plat-orion/include/plat/addr-map.h
··· 11 11 #ifndef __PLAT_ADDR_MAP_H 12 12 #define __PLAT_ADDR_MAP_H 13 13 14 + extern struct mbus_dram_target_info orion_mbus_dram_info; 15 + 14 16 struct orion_addr_map_cfg { 15 17 const int num_wins; /* Total number of windows */ 16 18 const int remappable_wins; ··· 49 47 const u8 attr, const int remap); 50 48 51 49 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, 52 - struct mbus_dram_target_info *info, 53 50 const u32 ddr_window_cpu_base); 54 51 #endif