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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
MIPS: Hibernation: Remove SMP TLB and cacheflushing code.
We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled. A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled. A local
flush is not needed either because we didn't change any mappings. So
just delete the code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-9
arch/mips/power/hibernate.S
-9
arch/mips/power/hibernate.S
···
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bne t1, t3, 1b
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PTR_L t0, PBE_NEXT(t0)
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bnez t0, 0b
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-
/* flush caches to make sure context is in memory */
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-
PTR_L t0, __flush_cache_all
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-
jalr t0
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-
/* flush tlb entries */
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#ifdef CONFIG_SMP
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jal flush_tlb_all
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-
#else
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jal local_flush_tlb_all
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-
#endif
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46
PTR_LA t0, saved_regs
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PTR_L ra, PT_R31(t0)
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48
PTR_L sp, PT_R29(t0)