tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: dont save/restore VGA state for kms
The only thing we really care about that it is off. To do so, reuse
the recently created i915_redisable_vga function, which is already
used to put obnoxious firmware into check on lid reopening.
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+28
-23
+1
drivers/gpu/drm/i915/i915_drv.h
+1
drivers/gpu/drm/i915/i915_drv.h
···
1789
1789
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1790
1790
extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1791
1791
bool force_restore);
1792
+
extern void i915_redisable_vga(struct drm_device *dev);
1792
1793
extern bool intel_fbc_enabled(struct drm_device *dev);
1793
1794
extern void intel_disable_fbc(struct drm_device *dev);
1794
1795
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
+26
-22
drivers/gpu/drm/i915/i915_suspend.c
+26
-22
drivers/gpu/drm/i915/i915_suspend.c
···
69
69
int i;
70
70
u16 cr_index, cr_data, st01;
71
71
72
+
/* VGA state */
73
+
dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
74
+
dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
75
+
dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
76
+
if (HAS_PCH_SPLIT(dev))
77
+
dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
78
+
else
79
+
dev_priv->regfile.saveVGACNTRL = I915_READ(VGACNTRL);
80
+
72
81
/* VGA color palette registers */
73
82
dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
74
83
···
135
126
struct drm_i915_private *dev_priv = dev->dev_private;
136
127
int i;
137
128
u16 cr_index, cr_data, st01;
129
+
130
+
/* VGA state */
131
+
if (HAS_PCH_SPLIT(dev))
132
+
I915_WRITE(CPU_VGACNTRL, dev_priv->regfile.saveVGACNTRL);
133
+
else
134
+
I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
135
+
136
+
I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
137
+
I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
138
+
I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
139
+
POSTING_READ(VGA_PD);
140
+
udelay(150);
138
141
139
142
/* MSR bits */
140
143
I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
···
272
251
}
273
252
}
274
253
275
-
/* VGA state */
276
-
dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
277
-
dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
278
-
dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
279
-
if (HAS_PCH_SPLIT(dev))
280
-
dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
281
-
else
282
-
dev_priv->regfile.saveVGACNTRL = I915_READ(VGACNTRL);
283
-
284
-
i915_save_vga(dev);
254
+
if (!drm_core_check_feature(dev, DRIVER_MODESET))
255
+
i915_save_vga(dev);
285
256
}
286
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static void i915_restore_display(struct drm_device *dev)
···
347
334
I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
348
335
}
349
336
}
350
-
/* VGA state */
351
-
if (HAS_PCH_SPLIT(dev))
352
-
I915_WRITE(CPU_VGACNTRL, dev_priv->regfile.saveVGACNTRL);
337
+
if (!drm_core_check_feature(dev, DRIVER_MODESET))
338
+
i915_restore_vga(dev);
353
339
else
354
-
I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
355
-
356
-
I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
357
-
I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
358
-
I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
359
-
POSTING_READ(VGA_PD);
360
-
udelay(150);
361
-
362
-
i915_restore_vga(dev);
340
+
i915_redisable_vga(dev);
363
341
}
364
342
365
343
int i915_save_state(struct drm_device *dev)
+1
-1
drivers/gpu/drm/i915/intel_display.c
+1
-1
drivers/gpu/drm/i915/intel_display.c