clk: spear3xx: Set proper clock parent of uart1/2

The uarts only work when the parent is ras_ahb_clk. The stale 3.5
based ST tree does this in the board file.

Add it to the clk init function. Not pretty, but the mess there is
amazing anyway.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

authored by Thomas Gleixner and committed by Mike Turquette 44943777 15ebb052

Changed files
+10 -4
drivers
clk
+10 -4
drivers/clk/spear/spear3xx_clock.c
··· 245 245 "ras_syn0_gclk", }; 246 246 static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", }; 247 247 248 - static void __init spear320_clk_init(void __iomem *soc_config_base) 248 + static void __init spear320_clk_init(void __iomem *soc_config_base, 249 + struct clk *ras_apb_clk) 249 250 { 250 251 struct clk *clk; 251 252 ··· 343 342 SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK, 344 343 0, &_lock); 345 344 clk_register_clkdev(clk, NULL, "a3000000.serial"); 345 + /* Enforce ras_apb_clk */ 346 + clk_set_parent(clk, ras_apb_clk); 346 347 347 348 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, 348 349 ARRAY_SIZE(uartx_parents), ··· 352 349 SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT, 353 350 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 354 351 clk_register_clkdev(clk, NULL, "a4000000.serial"); 352 + /* Enforce ras_apb_clk */ 353 + clk_set_parent(clk, ras_apb_clk); 355 354 356 355 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, 357 356 ARRAY_SIZE(uartx_parents), ··· 384 379 clk_register_clkdev(clk, NULL, "60100000.serial"); 385 380 } 386 381 #else 387 - static inline void spear320_clk_init(void __iomem *soc_config_base) { } 382 + static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { } 388 383 #endif 389 384 390 385 void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) 391 386 { 392 - struct clk *clk, *clk1; 387 + struct clk *clk, *clk1, *ras_apb_clk; 393 388 394 389 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 395 390 32000); ··· 618 613 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB, 619 614 RAS_APB_CLK_ENB, 0, &_lock); 620 615 clk_register_clkdev(clk, "ras_apb_clk", NULL); 616 + ras_apb_clk = clk; 621 617 622 618 clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0, 623 619 RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock); ··· 665 659 else if (of_machine_is_compatible("st,spear310")) 666 660 spear310_clk_init(); 667 661 else if (of_machine_is_compatible("st,spear320")) 668 - spear320_clk_init(soc_config_base); 662 + spear320_clk_init(soc_config_base, ras_apb_clk); 669 663 }