dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Add clock management unit bindings for PERIC0 and PERIC1 blocks
which provide clocks for USI, I2C and UART peripherals.

Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

authored by

Denzeel Oliva and committed by

Krzysztof Kozlowski 7 months ago 43bd82eb f00a5dc8

+200

2 changed files

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Documentation

devicetree

bindings

clock

samsung,exynos990-clock.yaml

include

dt-bindings

clock

samsung,exynos990.h

+24

Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml

··· 30 30 properties: 31 31 compatible: 32 32 enum: 33 + - samsung,exynos990-cmu-peric1 34 + - samsung,exynos990-cmu-peric0 33 35 - samsung,exynos990-cmu-hsi0 34 36 - samsung,exynos990-cmu-peris 35 37 - samsung,exynos990-cmu-top ··· 58 56 - reg 59 57 60 58 allOf: 59 + - if: 60 + properties: 61 + compatible: 62 + contains: 63 + enum: 64 + - samsung,exynos990-cmu-peric1 65 + - samsung,exynos990-cmu-peric0 66 + 67 + then: 68 + properties: 69 + clocks: 70 + items: 71 + - description: External reference clock (26 MHz) 72 + - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP) 73 + - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP) 74 + 75 + clock-names: 76 + items: 77 + - const: oscclk 78 + - const: bus 79 + - const: ip 80 + 61 81 - if: 62 82 properties: 63 83 compatible:

+176

include/dt-bindings/clock/samsung,exynos990.h

··· 238 238 #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22 239 239 #define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK 23 240 240 241 + /* CMU_PERIC0 */ 242 + #define CLK_MOUT_PERIC0_BUS_USER 1 243 + #define CLK_MOUT_PERIC0_UART_DBG 2 244 + #define CLK_MOUT_PERIC0_USI00_USI_USER 3 245 + #define CLK_MOUT_PERIC0_USI01_USI_USER 4 246 + #define CLK_MOUT_PERIC0_USI02_USI_USER 5 247 + #define CLK_MOUT_PERIC0_USI03_USI_USER 6 248 + #define CLK_MOUT_PERIC0_USI04_USI_USER 7 249 + #define CLK_MOUT_PERIC0_USI05_USI_USER 8 250 + #define CLK_MOUT_PERIC0_USI13_USI_USER 9 251 + #define CLK_MOUT_PERIC0_USI14_USI_USER 10 252 + #define CLK_MOUT_PERIC0_USI15_USI_USER 11 253 + #define CLK_MOUT_PERIC0_USI_I2C_USER 12 254 + #define CLK_DOUT_PERIC0_UART_DBG 13 255 + #define CLK_DOUT_PERIC0_USI00_USI 14 256 + #define CLK_DOUT_PERIC0_USI01_USI 15 257 + #define CLK_DOUT_PERIC0_USI02_USI 16 258 + #define CLK_DOUT_PERIC0_USI03_USI 17 259 + #define CLK_DOUT_PERIC0_USI04_USI 18 260 + #define CLK_DOUT_PERIC0_USI05_USI 19 261 + #define CLK_DOUT_PERIC0_USI13_USI 20 262 + #define CLK_DOUT_PERIC0_USI14_USI 21 263 + #define CLK_DOUT_PERIC0_USI15_USI 22 264 + #define CLK_DOUT_PERIC0_USI_I2C 23 265 + #define CLK_GOUT_PERIC0_CMU_PCLK 24 266 + #define CLK_GOUT_PERIC0_OSCCLK_CLK 25 267 + #define CLK_GOUT_PERIC0_D_TZPC_PCLK 26 268 + #define CLK_GOUT_PERIC0_GPIO_PCLK 27 269 + #define CLK_GOUT_PERIC0_LHM_AXI_P_CLK 28 270 + #define CLK_GOUT_PERIC0_TOP0_IPCLK_10 29 271 + #define CLK_GOUT_PERIC0_TOP0_IPCLK_11 30 272 + #define CLK_GOUT_PERIC0_TOP0_IPCLK_12 31 273 + #define CLK_GOUT_PERIC0_TOP0_IPCLK_13 32 274 + #define CLK_GOUT_PERIC0_TOP0_IPCLK_14 33 275 + #define CLK_GOUT_PERIC0_TOP0_IPCLK_15 34 276 + #define CLK_GOUT_PERIC0_TOP0_IPCLK_4 35 277 + #define CLK_GOUT_PERIC0_TOP0_IPCLK_5 36 278 + #define CLK_GOUT_PERIC0_TOP0_IPCLK_6 37 279 + #define CLK_GOUT_PERIC0_TOP0_IPCLK_7 38 280 + #define CLK_GOUT_PERIC0_TOP0_IPCLK_8 39 281 + #define CLK_GOUT_PERIC0_TOP0_IPCLK_9 40 282 + #define CLK_GOUT_PERIC0_TOP0_PCLK_10 41 283 + #define CLK_GOUT_PERIC0_TOP0_PCLK_11 42 284 + #define CLK_GOUT_PERIC0_TOP0_PCLK_12 43 285 + #define CLK_GOUT_PERIC0_TOP0_PCLK_13 44 286 + #define CLK_GOUT_PERIC0_TOP0_PCLK_14 45 287 + #define CLK_GOUT_PERIC0_TOP0_PCLK_15 46 288 + #define CLK_GOUT_PERIC0_TOP0_PCLK_4 47 289 + #define CLK_GOUT_PERIC0_TOP0_PCLK_5 48 290 + #define CLK_GOUT_PERIC0_TOP0_PCLK_6 49 291 + #define CLK_GOUT_PERIC0_TOP0_PCLK_7 50 292 + #define CLK_GOUT_PERIC0_TOP0_PCLK_8 51 293 + #define CLK_GOUT_PERIC0_TOP0_PCLK_9 52 294 + #define CLK_GOUT_PERIC0_TOP1_IPCLK_0 53 295 + #define CLK_GOUT_PERIC0_TOP1_IPCLK_3 54 296 + #define CLK_GOUT_PERIC0_TOP1_IPCLK_4 55 297 + #define CLK_GOUT_PERIC0_TOP1_IPCLK_5 56 298 + #define CLK_GOUT_PERIC0_TOP1_IPCLK_6 57 299 + #define CLK_GOUT_PERIC0_TOP1_IPCLK_7 58 300 + #define CLK_GOUT_PERIC0_TOP1_IPCLK_8 59 301 + #define CLK_GOUT_PERIC0_TOP1_PCLK_0 60 302 + #define CLK_GOUT_PERIC0_TOP1_PCLK_15 61 303 + #define CLK_GOUT_PERIC0_TOP1_PCLK_3 62 304 + #define CLK_GOUT_PERIC0_TOP1_PCLK_4 63 305 + #define CLK_GOUT_PERIC0_TOP1_PCLK_5 64 306 + #define CLK_GOUT_PERIC0_TOP1_PCLK_6 65 307 + #define CLK_GOUT_PERIC0_TOP1_PCLK_7 66 308 + #define CLK_GOUT_PERIC0_TOP1_PCLK_8 67 309 + #define CLK_GOUT_PERIC0_BUSP_CLK 68 310 + #define CLK_GOUT_PERIC0_UART_DBG_CLK 69 311 + #define CLK_GOUT_PERIC0_USI00_USI_CLK 70 312 + #define CLK_GOUT_PERIC0_USI01_USI_CLK 71 313 + #define CLK_GOUT_PERIC0_USI02_USI_CLK 72 314 + #define CLK_GOUT_PERIC0_USI03_USI_CLK 73 315 + #define CLK_GOUT_PERIC0_USI04_USI_CLK 74 316 + #define CLK_GOUT_PERIC0_USI05_USI_CLK 75 317 + #define CLK_GOUT_PERIC0_USI13_USI_CLK 76 318 + #define CLK_GOUT_PERIC0_USI14_USI_CLK 77 319 + #define CLK_GOUT_PERIC0_USI15_USI_CLK 78 320 + #define CLK_GOUT_PERIC0_USI_I2C_CLK 79 321 + #define CLK_GOUT_PERIC0_SYSREG_PCLK 80 322 + 323 + /* CMU_PERIC1 */ 324 + #define CLK_MOUT_PERIC1_BUS_USER 1 325 + #define CLK_MOUT_PERIC1_UART_BT_USER 2 326 + #define CLK_MOUT_PERIC1_USI06_USI_USER 3 327 + #define CLK_MOUT_PERIC1_USI07_USI_USER 4 328 + #define CLK_MOUT_PERIC1_USI08_USI_USER 5 329 + #define CLK_MOUT_PERIC1_USI09_USI_USER 6 330 + #define CLK_MOUT_PERIC1_USI10_USI_USER 7 331 + #define CLK_MOUT_PERIC1_USI11_USI_USER 8 332 + #define CLK_MOUT_PERIC1_USI12_USI_USER 9 333 + #define CLK_MOUT_PERIC1_USI18_USI_USER 10 334 + #define CLK_MOUT_PERIC1_USI16_USI_USER 11 335 + #define CLK_MOUT_PERIC1_USI17_USI_USER 12 336 + #define CLK_MOUT_PERIC1_USI_I2C_USER 13 337 + #define CLK_DOUT_PERIC1_UART_BT 14 338 + #define CLK_DOUT_PERIC1_USI06_USI 15 339 + #define CLK_DOUT_PERIC1_USI07_USI 16 340 + #define CLK_DOUT_PERIC1_USI08_USI 17 341 + #define CLK_DOUT_PERIC1_USI18_USI 18 342 + #define CLK_DOUT_PERIC1_USI12_USI 19 343 + #define CLK_DOUT_PERIC1_USI09_USI 20 344 + #define CLK_DOUT_PERIC1_USI10_USI 21 345 + #define CLK_DOUT_PERIC1_USI11_USI 22 346 + #define CLK_DOUT_PERIC1_USI16_USI 23 347 + #define CLK_DOUT_PERIC1_USI17_USI 24 348 + #define CLK_DOUT_PERIC1_USI_I2C 25 349 + #define CLK_GOUT_PERIC1_CMU_PCLK 26 350 + #define CLK_GOUT_PERIC1_UART_BT_CLK 27 351 + #define CLK_GOUT_PERIC1_USI12_USI_CLK 28 352 + #define CLK_GOUT_PERIC1_USI18_USI_CLK 29 353 + #define CLK_GOUT_PERIC1_D_TZPC_PCLK 30 354 + #define CLK_GOUT_PERIC1_GPIO_PCLK 31 355 + #define CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK 32 356 + #define CLK_GOUT_PERIC1_LHM_AXI_P_CLK 33 357 + #define CLK_GOUT_PERIC1_TOP0_IPCLK_10 34 358 + #define CLK_GOUT_PERIC1_TOP0_IPCLK_11 35 359 + #define CLK_GOUT_PERIC1_TOP0_IPCLK_12 36 360 + #define CLK_GOUT_PERIC1_TOP0_IPCLK_13 37 361 + #define CLK_GOUT_PERIC1_TOP0_IPCLK_14 38 362 + #define CLK_GOUT_PERIC1_TOP0_IPCLK_15 39 363 + #define CLK_GOUT_PERIC1_TOP0_IPCLK_4 40 364 + #define CLK_GOUT_PERIC1_TOP0_PCLK_10 41 365 + #define CLK_GOUT_PERIC1_TOP0_PCLK_11 42 366 + #define CLK_GOUT_PERIC1_TOP0_PCLK_12 43 367 + #define CLK_GOUT_PERIC1_TOP0_PCLK_13 44 368 + #define CLK_GOUT_PERIC1_TOP0_PCLK_14 45 369 + #define CLK_GOUT_PERIC1_TOP0_PCLK_15 46 370 + #define CLK_GOUT_PERIC1_TOP0_PCLK_4 47 371 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_0 48 372 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_1 49 373 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_10 50 374 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_12 51 375 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_13 52 376 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_14 53 377 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_15 54 378 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_2 55 379 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_3 56 380 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_4 57 381 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_5 58 382 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_6 59 383 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_7 60 384 + #define CLK_GOUT_PERIC1_TOP1_IPCLK_9 61 385 + #define CLK_GOUT_PERIC1_TOP1_PCLK_0 62 386 + #define CLK_GOUT_PERIC1_TOP1_PCLK_1 63 387 + #define CLK_GOUT_PERIC1_TOP1_PCLK_10 64 388 + #define CLK_GOUT_PERIC1_TOP1_PCLK_12 65 389 + #define CLK_GOUT_PERIC1_TOP1_PCLK_13 66 390 + #define CLK_GOUT_PERIC1_TOP1_PCLK_14 67 391 + #define CLK_GOUT_PERIC1_TOP1_PCLK_15 68 392 + #define CLK_GOUT_PERIC1_TOP1_PCLK_2 69 393 + #define CLK_GOUT_PERIC1_TOP1_PCLK_3 70 394 + #define CLK_GOUT_PERIC1_TOP1_PCLK_4 71 395 + #define CLK_GOUT_PERIC1_TOP1_PCLK_5 72 396 + #define CLK_GOUT_PERIC1_TOP1_PCLK_6 73 397 + #define CLK_GOUT_PERIC1_TOP1_PCLK_7 74 398 + #define CLK_GOUT_PERIC1_TOP1_PCLK_9 75 399 + #define CLK_GOUT_PERIC1_BUSP_CLK 76 400 + #define CLK_GOUT_PERIC1_OSCCLK_CLK 77 401 + #define CLK_GOUT_PERIC1_USI06_USI_CLK 78 402 + #define CLK_GOUT_PERIC1_USI07_USI_CLK 79 403 + #define CLK_GOUT_PERIC1_USI08_USI_CLK 80 404 + #define CLK_GOUT_PERIC1_USI09_USI_CLK 81 405 + #define CLK_GOUT_PERIC1_USI10_USI_CLK 82 406 + #define CLK_GOUT_PERIC1_USI11_USI_CLK 83 407 + #define CLK_GOUT_PERIC1_USI16_USI_CLK 84 408 + #define CLK_GOUT_PERIC1_USI17_USI_CLK 85 409 + #define CLK_GOUT_PERIC1_USI_I2C_CLK 86 410 + #define CLK_GOUT_PERIC1_SYSREG_PCLK 87 411 + #define CLK_GOUT_PERIC1_USI16_I3C_PCLK 88 412 + #define CLK_GOUT_PERIC1_USI16_I3C_SCLK 89 413 + #define CLK_GOUT_PERIC1_USI17_I3C_PCLK 90 414 + #define CLK_GOUT_PERIC1_USI17_I3C_SCLK 91 415 + #define CLK_GOUT_PERIC1_XIU_P_ACLK 92 416 + 241 417 /* CMU_PERIS */ 242 418 #define CLK_MOUT_PERIS_BUS_USER 1 243 419 #define CLK_MOUT_PERIS_CLK_PERIS_GIC 2