tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Olof Johansson:
"A few fixes this time around:

- Fixup of some clock specifications for DRA7 (device-tree fix)

- Removal of some dead/legacy CPU OPP/PM code for OMAP that throws
warnings at boot

- A few more minor fixups for OMAPs, most around display

- Enable STM32 QSPI as =y since their rootfs sometimes comes from
there

- Switch CONFIG_REMOTEPROC to =y since it went from tristate to bool

- Fix of thermal zone definition for ux500 (5.4 regression)"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: multi_v7_defconfig: Fix SPI_STM32_QSPI support
ARM: dts: ux500: Fix up the CPU thermal zone
arm64/ARM: configs: Change CONFIG_REMOTEPROC from m to y
ARM: dts: am4372: Set memory bandwidth limit for DISPC
ARM: OMAP2+: Fix warnings with broken omap2_set_init_voltage()
ARM: OMAP2+: Add missing LCDC midlemode for am335x
ARM: OMAP2+: Fix missing reset done flag for am3 and am43
ARM: dts: Fix gpio0 flags for am335x-icev2
ARM: omap2plus_defconfig: Enable more droid4 devices as loadable modules
ARM: omap2plus_defconfig: Enable DRM_TI_TFP410
DTS: ARM: gta04: introduce legacy spi-cs-high to make display work again
ARM: dts: Fix wrong clocks for dra7 mcasp
clk: ti: dra7: Fix mcasp8 clock bits

Linus Torvalds 43b815c6 2d00aee2

+53 -144
+1 -1
arch/arm/boot/dts/am335x-icev2.dts
··· 432 432 pinctrl-0 = <&mmc0_pins_default>; 433 433 }; 434 434 435 - &gpio0 { 435 + &gpio0_target { 436 436 /* Do not idle the GPIO used for holding the VTT regulator */ 437 437 ti,no-reset-on-init; 438 438 ti,no-idle-on-init;
+4 -2
arch/arm/boot/dts/am33xx-l4.dtsi
··· 127 127 ranges = <0x0 0x5000 0x1000>; 128 128 }; 129 129 130 - target-module@7000 { /* 0x44e07000, ap 14 20.0 */ 130 + gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ 131 131 compatible = "ti,sysc-omap2", "ti,sysc"; 132 132 ti,hwmods = "gpio1"; 133 133 reg = <0x7000 0x4>, ··· 2038 2038 reg = <0xe000 0x4>, 2039 2039 <0xe054 0x4>; 2040 2040 reg-names = "rev", "sysc"; 2041 - ti,sysc-midle ; 2041 + ti,sysc-midle = <SYSC_IDLE_FORCE>, 2042 + <SYSC_IDLE_NO>, 2043 + <SYSC_IDLE_SMART>; 2042 2044 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2043 2045 <SYSC_IDLE_NO>, 2044 2046 <SYSC_IDLE_SMART>;
+2
arch/arm/boot/dts/am4372.dtsi
··· 337 337 ti,hwmods = "dss_dispc"; 338 338 clocks = <&disp_clk>; 339 339 clock-names = "fck"; 340 + 341 + max-memory-bandwidth = <230000000>; 340 342 }; 341 343 342 344 rfbi: rfbi@4832a800 {
+21 -27
arch/arm/boot/dts/dra7-l4.dtsi
··· 2732 2732 interrupt-names = "tx", "rx"; 2733 2733 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; 2734 2734 dma-names = "tx", "rx"; 2735 - clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>, 2735 + clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, 2736 2736 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, 2737 2737 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; 2738 2738 clock-names = "fck", "ahclkx", "ahclkr"; ··· 2768 2768 interrupt-names = "tx", "rx"; 2769 2769 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; 2770 2770 dma-names = "tx", "rx"; 2771 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>, 2772 - <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, 2771 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, 2772 + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, 2773 2773 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; 2774 2774 clock-names = "fck", "ahclkx", "ahclkr"; 2775 2775 status = "disabled"; ··· 2786 2786 <SYSC_IDLE_SMART>; 2787 2787 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2788 2788 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, 2789 - <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>, 2790 - <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>; 2791 - clock-names = "fck", "ahclkx", "ahclkr"; 2789 + <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 2790 + clock-names = "fck", "ahclkx"; 2792 2791 #address-cells = <1>; 2793 2792 #size-cells = <1>; 2794 2793 ranges = <0x0 0x68000 0x2000>, ··· 2803 2804 interrupt-names = "tx", "rx"; 2804 2805 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; 2805 2806 dma-names = "tx", "rx"; 2806 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>, 2807 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, 2807 2808 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 2808 2809 clock-names = "fck", "ahclkx"; 2809 2810 status = "disabled"; ··· 2820 2821 <SYSC_IDLE_SMART>; 2821 2822 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2822 2823 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, 2823 - <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>, 2824 - <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>; 2825 - clock-names = "fck", "ahclkx", "ahclkr"; 2824 + <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; 2825 + clock-names = "fck", "ahclkx"; 2826 2826 #address-cells = <1>; 2827 2827 #size-cells = <1>; 2828 2828 ranges = <0x0 0x6c000 0x2000>, ··· 2837 2839 interrupt-names = "tx", "rx"; 2838 2840 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; 2839 2841 dma-names = "tx", "rx"; 2840 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>, 2842 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, 2841 2843 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; 2842 2844 clock-names = "fck", "ahclkx"; 2843 2845 status = "disabled"; ··· 2854 2856 <SYSC_IDLE_SMART>; 2855 2857 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2856 2858 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, 2857 - <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>, 2858 - <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>; 2859 - clock-names = "fck", "ahclkx", "ahclkr"; 2859 + <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; 2860 + clock-names = "fck", "ahclkx"; 2860 2861 #address-cells = <1>; 2861 2862 #size-cells = <1>; 2862 2863 ranges = <0x0 0x70000 0x2000>, ··· 2871 2874 interrupt-names = "tx", "rx"; 2872 2875 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; 2873 2876 dma-names = "tx", "rx"; 2874 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>, 2877 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, 2875 2878 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; 2876 2879 clock-names = "fck", "ahclkx"; 2877 2880 status = "disabled"; ··· 2888 2891 <SYSC_IDLE_SMART>; 2889 2892 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2890 2893 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, 2891 - <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>, 2892 - <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>; 2893 - clock-names = "fck", "ahclkx", "ahclkr"; 2894 + <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; 2895 + clock-names = "fck", "ahclkx"; 2894 2896 #address-cells = <1>; 2895 2897 #size-cells = <1>; 2896 2898 ranges = <0x0 0x74000 0x2000>, ··· 2905 2909 interrupt-names = "tx", "rx"; 2906 2910 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; 2907 2911 dma-names = "tx", "rx"; 2908 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>, 2912 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, 2909 2913 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; 2910 2914 clock-names = "fck", "ahclkx"; 2911 2915 status = "disabled"; ··· 2922 2926 <SYSC_IDLE_SMART>; 2923 2927 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2924 2928 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, 2925 - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>, 2926 - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>; 2927 - clock-names = "fck", "ahclkx", "ahclkr"; 2929 + <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; 2930 + clock-names = "fck", "ahclkx"; 2928 2931 #address-cells = <1>; 2929 2932 #size-cells = <1>; 2930 2933 ranges = <0x0 0x78000 0x2000>, ··· 2939 2944 interrupt-names = "tx", "rx"; 2940 2945 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; 2941 2946 dma-names = "tx", "rx"; 2942 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>, 2947 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, 2943 2948 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; 2944 2949 clock-names = "fck", "ahclkx"; 2945 2950 status = "disabled"; ··· 2956 2961 <SYSC_IDLE_SMART>; 2957 2962 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2958 2963 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, 2959 - <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>, 2960 - <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>; 2961 - clock-names = "fck", "ahclkx", "ahclkr"; 2964 + <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; 2965 + clock-names = "fck", "ahclkx"; 2962 2966 #address-cells = <1>; 2963 2967 #size-cells = <1>; 2964 2968 ranges = <0x0 0x7c000 0x2000>, ··· 2973 2979 interrupt-names = "tx", "rx"; 2974 2980 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; 2975 2981 dma-names = "tx", "rx"; 2976 - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>, 2982 + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, 2977 2983 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; 2978 2984 clock-names = "fck", "ahclkx"; 2979 2985 status = "disabled";
+1
arch/arm/boot/dts/omap3-gta04.dtsi
··· 124 124 spi-max-frequency = <100000>; 125 125 spi-cpol; 126 126 spi-cpha; 127 + spi-cs-high; 127 128 128 129 backlight= <&backlight>; 129 130 label = "lcd";
+8 -3
arch/arm/boot/dts/ste-dbx5x0.dtsi
··· 8 8 #include <dt-bindings/mfd/dbx500-prcmu.h> 9 9 #include <dt-bindings/arm/ux500_pm_domains.h> 10 10 #include <dt-bindings/gpio/gpio.h> 11 + #include <dt-bindings/thermal/thermal.h> 11 12 12 13 / { 13 14 #address-cells = <1>; ··· 60 59 * cooling. 61 60 */ 62 61 cpu_thermal: cpu-thermal { 63 - polling-delay-passive = <0>; 64 - polling-delay = <1000>; 62 + polling-delay-passive = <250>; 63 + /* 64 + * This sensor fires interrupts to update the thermal 65 + * zone, so no polling is needed. 66 + */ 67 + polling-delay = <0>; 65 68 66 69 thermal-sensors = <&thermal>; 67 70 ··· 84 79 85 80 cooling-maps { 86 81 trip = <&cpu_alert>; 87 - cooling-device = <&CPU0 0 2>; 82 + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 88 83 contribution = <100>; 89 84 }; 90 85 };
+1 -1
arch/arm/configs/davinci_all_defconfig
··· 228 228 CONFIG_DMADEVICES=y 229 229 CONFIG_TI_EDMA=y 230 230 CONFIG_COMMON_CLK_PWM=m 231 - CONFIG_REMOTEPROC=m 231 + CONFIG_REMOTEPROC=y 232 232 CONFIG_DA8XX_REMOTEPROC=m 233 233 CONFIG_MEMORY=y 234 234 CONFIG_TI_AEMIF=m
+2 -2
arch/arm/configs/multi_v7_defconfig
··· 415 415 CONFIG_SPI_SH_HSPI=y 416 416 CONFIG_SPI_SIRF=y 417 417 CONFIG_SPI_STM32=m 418 - CONFIG_SPI_STM32_QSPI=m 418 + CONFIG_SPI_STM32_QSPI=y 419 419 CONFIG_SPI_SUN4I=y 420 420 CONFIG_SPI_SUN6I=y 421 421 CONFIG_SPI_TEGRA114=y ··· 933 933 CONFIG_ROCKCHIP_IOMMU=y 934 934 CONFIG_TEGRA_IOMMU_GART=y 935 935 CONFIG_TEGRA_IOMMU_SMMU=y 936 - CONFIG_REMOTEPROC=m 936 + CONFIG_REMOTEPROC=y 937 937 CONFIG_ST_REMOTEPROC=m 938 938 CONFIG_RPMSG_VIRTIO=m 939 939 CONFIG_ASPEED_LPC_CTRL=m
+4 -1
arch/arm/configs/omap2plus_defconfig
··· 364 364 CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m 365 365 CONFIG_DRM_TILCDC=m 366 366 CONFIG_DRM_PANEL_SIMPLE=m 367 + CONFIG_DRM_TI_TFP410=m 367 368 CONFIG_FB=y 368 369 CONFIG_FIRMWARE_EDID=y 369 370 CONFIG_FB_MODE_HELPERS=y ··· 424 423 CONFIG_USB_SERIAL_SIMPLE=m 425 424 CONFIG_USB_SERIAL_FTDI_SIO=m 426 425 CONFIG_USB_SERIAL_PL2303=m 426 + CONFIG_USB_SERIAL_OPTION=m 427 427 CONFIG_USB_TEST=m 428 428 CONFIG_NOP_USB_XCEIV=m 429 429 CONFIG_AM335X_PHY_USB=m ··· 462 460 CONFIG_NEW_LEDS=y 463 461 CONFIG_LEDS_CLASS=m 464 462 CONFIG_LEDS_CPCAP=m 463 + CONFIG_LEDS_LM3532=m 465 464 CONFIG_LEDS_GPIO=m 466 465 CONFIG_LEDS_PCA963X=m 467 466 CONFIG_LEDS_PWM=m ··· 484 481 CONFIG_RTC_DRV_CPCAP=m 485 482 CONFIG_DMADEVICES=y 486 483 CONFIG_OMAP_IOMMU=y 487 - CONFIG_REMOTEPROC=m 484 + CONFIG_REMOTEPROC=y 488 485 CONFIG_OMAP_REMOTEPROC=m 489 486 CONFIG_WKUP_M3_RPROC=m 490 487 CONFIG_SOC_TI=y
+2 -1
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
··· 763 763 .rev_offs = 0x0000, 764 764 .sysc_offs = 0x0010, 765 765 .syss_offs = 0x0014, 766 - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 766 + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 767 + SYSC_HAS_RESET_STATUS, 767 768 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 768 769 SIDLE_SMART_WKUP), 769 770 .sysc_fields = &omap_hwmod_sysc_type2,
+3 -2
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
··· 231 231 static struct omap_hwmod_class_sysconfig lcdc_sysc = { 232 232 .rev_offs = 0x0, 233 233 .sysc_offs = 0x54, 234 - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), 235 - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 234 + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE, 235 + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 236 + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART, 236 237 .sysc_fields = &omap_hwmod_sysc_type2, 237 238 }; 238 239
-100
arch/arm/mach-omap2/pm.c
··· 74 74 return 0; 75 75 } 76 76 77 - /* 78 - * This API is to be called during init to set the various voltage 79 - * domains to the voltage as per the opp table. Typically we boot up 80 - * at the nominal voltage. So this function finds out the rate of 81 - * the clock associated with the voltage domain, finds out the correct 82 - * opp entry and sets the voltage domain to the voltage specified 83 - * in the opp entry 84 - */ 85 - static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, 86 - const char *oh_name) 87 - { 88 - struct voltagedomain *voltdm; 89 - struct clk *clk; 90 - struct dev_pm_opp *opp; 91 - unsigned long freq, bootup_volt; 92 - struct device *dev; 93 - 94 - if (!vdd_name || !clk_name || !oh_name) { 95 - pr_err("%s: invalid parameters\n", __func__); 96 - goto exit; 97 - } 98 - 99 - if (!strncmp(oh_name, "mpu", 3)) 100 - /* 101 - * All current OMAPs share voltage rail and clock 102 - * source, so CPU0 is used to represent the MPU-SS. 103 - */ 104 - dev = get_cpu_device(0); 105 - else 106 - dev = omap_device_get_by_hwmod_name(oh_name); 107 - 108 - if (IS_ERR(dev)) { 109 - pr_err("%s: Unable to get dev pointer for hwmod %s\n", 110 - __func__, oh_name); 111 - goto exit; 112 - } 113 - 114 - voltdm = voltdm_lookup(vdd_name); 115 - if (!voltdm) { 116 - pr_err("%s: unable to get vdd pointer for vdd_%s\n", 117 - __func__, vdd_name); 118 - goto exit; 119 - } 120 - 121 - clk = clk_get(NULL, clk_name); 122 - if (IS_ERR(clk)) { 123 - pr_err("%s: unable to get clk %s\n", __func__, clk_name); 124 - goto exit; 125 - } 126 - 127 - freq = clk_get_rate(clk); 128 - clk_put(clk); 129 - 130 - opp = dev_pm_opp_find_freq_ceil(dev, &freq); 131 - if (IS_ERR(opp)) { 132 - pr_err("%s: unable to find boot up OPP for vdd_%s\n", 133 - __func__, vdd_name); 134 - goto exit; 135 - } 136 - 137 - bootup_volt = dev_pm_opp_get_voltage(opp); 138 - dev_pm_opp_put(opp); 139 - 140 - if (!bootup_volt) { 141 - pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n", 142 - __func__, vdd_name); 143 - goto exit; 144 - } 145 - 146 - voltdm_scale(voltdm, bootup_volt); 147 - return 0; 148 - 149 - exit: 150 - pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name); 151 - return -EINVAL; 152 - } 153 - 154 77 #ifdef CONFIG_SUSPEND 155 78 static int omap_pm_enter(suspend_state_t suspend_state) 156 79 { ··· 131 208 } 132 209 #endif /* CONFIG_SUSPEND */ 133 210 134 - static void __init omap3_init_voltages(void) 135 - { 136 - if (!soc_is_omap34xx()) 137 - return; 138 - 139 - omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu"); 140 - omap2_set_init_voltage("core", "l3_ick", "l3_main"); 141 - } 142 - 143 - static void __init omap4_init_voltages(void) 144 - { 145 - if (!soc_is_omap44xx()) 146 - return; 147 - 148 - omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu"); 149 - omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1"); 150 - omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva"); 151 - } 152 - 153 211 int __maybe_unused omap_pm_nop_init(void) 154 212 { 155 213 return 0; ··· 149 245 omap3_twl_init(); 150 246 omap4_twl_init(); 151 247 omap_voltage_late_init(); 152 - 153 - /* Initialize the voltages */ 154 - omap3_init_voltages(); 155 - omap4_init_voltages(); 156 248 157 249 /* Smartreflex device init */ 158 250 omap_devinit_smartreflex();
+1 -1
arch/arm64/configs/defconfig
··· 723 723 CONFIG_ARM_SMMU=y 724 724 CONFIG_ARM_SMMU_V3=y 725 725 CONFIG_QCOM_IOMMU=y 726 - CONFIG_REMOTEPROC=m 726 + CONFIG_REMOTEPROC=y 727 727 CONFIG_QCOM_Q6V5_MSS=m 728 728 CONFIG_QCOM_Q6V5_PAS=m 729 729 CONFIG_QCOM_SYSMON=m
+3 -3
drivers/clk/ti/clk-7xx.c
··· 683 683 { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" }, 684 684 { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" }, 685 685 { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" }, 686 - { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" }, 686 + { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" }, 687 687 { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" }, 688 688 { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" }, 689 689 { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" }, ··· 828 828 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"), 829 829 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"), 830 830 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"), 831 - DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"), 832 - DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"), 831 + DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"), 832 + DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"), 833 833 DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"), 834 834 DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"), 835 835 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),