tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: imx8mp: add clkout1/2 support

clkout1 and clkout2 allow to supply clocks from the SoC to the board,
which is used by some board designs to provide reference clocks.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220427162131.3127303-1-l.stach@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

authored by

Lucas Stach and committed by
Abel Vesa 43896f56 bfd594b3

+21 -2
+14
drivers/clk/imx/clk-imx8mp.c
··· 399 399 400 400 static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; 401 401 402 + static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out", 403 + "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", 404 + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", 405 + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; 406 + 402 407 static struct clk_hw **hws; 403 408 static struct clk_hw_onecell_data *clk_hw_data; 404 409 ··· 508 503 hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); 509 504 hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); 510 505 hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); 506 + 507 + hws[IMX8MP_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", anatop_base + 0x128, 4, 4, 508 + imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels)); 509 + hws[IMX8MP_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", anatop_base + 0x128, 0, 4); 510 + hws[IMX8MP_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", anatop_base + 0x128, 8); 511 + hws[IMX8MP_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", anatop_base + 0x128, 20, 4, 512 + imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels)); 513 + hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4); 514 + hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24); 511 515 512 516 hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000); 513 517 hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
+7 -2
include/dt-bindings/clock/imx8mp-clock.h
··· 317 317 #define IMX8MP_CLK_AUDIO_AXI 310 318 318 #define IMX8MP_CLK_HSIO_AXI 311 319 319 #define IMX8MP_CLK_MEDIA_ISP 312 320 - 321 320 #define IMX8MP_CLK_MEDIA_DISP2_PIX 313 321 + #define IMX8MP_CLK_CLKOUT1_SEL 314 322 + #define IMX8MP_CLK_CLKOUT1_DIV 315 323 + #define IMX8MP_CLK_CLKOUT1 316 324 + #define IMX8MP_CLK_CLKOUT2_SEL 317 325 + #define IMX8MP_CLK_CLKOUT2_DIV 318 326 + #define IMX8MP_CLK_CLKOUT2 319 322 327 323 - #define IMX8MP_CLK_END 314 328 + #define IMX8MP_CLK_END 320 324 329 325 330 #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 326 331 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1