[MIPS] Ocelot: remove remaining bits

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by Yoichi Yuasa and committed by Ralf Baechle 43863074 603c338b

-44
-14
arch/mips/Kconfig
··· 818 config SERIAL_RM9000 819 bool 820 821 - # 822 - # Unfortunately not all GT64120 systems run the chip at the same clock. 823 - # As the user for the clock rate and try to minimize the available options. 824 - # 825 - choice 826 - prompt "Galileo Chip Clock" 827 - depends on MOMENCO_OCELOT 828 - default SYSCLK_100 if MOMENCO_OCELOT 829 - 830 - config SYSCLK_100 831 - bool "100" if MOMENCO_OCELOT 832 - 833 - endchoice 834 - 835 config ARC32 836 bool 837
··· 818 config SERIAL_RM9000 819 bool 820 821 config ARC32 822 bool 823
-30
include/asm-mips/mach-ocelot/mach-gt64120.h
··· 1 - /* 2 - * Copyright 2001 MontaVista Software Inc. 3 - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 4 - * 5 - * This program is free software; you can redistribute it and/or modify it 6 - * under the terms of the GNU General Public License as published by the 7 - * Free Software Foundation; either version 2 of the License, or (at your 8 - * option) any later version. 9 - */ 10 - #ifndef _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H 11 - #define _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H 12 - 13 - /* 14 - * PCI address allocation 15 - */ 16 - #define GT_PCI_MEM_BASE (0x22000000UL) 17 - #define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE 18 - #define GT_PCI_IO_BASE (0x20000000UL) 19 - #define GT_PCI_IO_SIZE GT_DEF_PCI0_IO_SIZE 20 - 21 - extern unsigned long gt64120_base; 22 - 23 - #define GT64120_BASE (gt64120_base) 24 - 25 - /* 26 - * GT timer irq 27 - */ 28 - #define GT_TIMER 6 29 - 30 - #endif /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */
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