tjh.dev / kernel
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[media] mx2_camera: fix pixel clock polarity configuration

When SOCAM_PCLK_SAMPLE_FALLING, just leave CSICR1_REDGE unset, otherwise we get
the inverted behaviour.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

authored by Baruch Siach and committed by Mauro Carvalho Chehab 42cc37fe 0e4d413a

-2
unified split
-2
drivers/media/video/mx2_camera.c
··· 807 808 if (common_flags & SOCAM_PCLK_SAMPLE_RISING) 809 csicr1 |= CSICR1_REDGE; 810 - if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) 811 - csicr1 |= CSICR1_INV_PCLK; 812 if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH) 813 csicr1 |= CSICR1_SOF_POL; 814 if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH)
··· 807 808 if (common_flags & SOCAM_PCLK_SAMPLE_RISING) 809 csicr1 |= CSICR1_REDGE; 810 if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH) 811 csicr1 |= CSICR1_SOF_POL; 812 if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH)