Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/display: Remove nv12 work around

[Why]
dal side nv12 wa has a lot of side effects.
KMD side wa is used, so this should be remove.

[How]
Removed wa from dal side.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Yongqiang Sun and committed by
Alex Deucher
429b9db8 4d693953

+2 -130
-3
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
··· 47 47 */ 48 48 memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config)); 49 49 dc->vm_pa_config.valid = true; 50 - 51 - if (pa_config->is_hvm_enabled == 0) 52 - dc->debug.nv12_iflip_vm_wa = false; 53 50 } 54 51 55 52 return num_vmids;
-1
drivers/gpu/drm/amd/display/dc/dc.h
··· 471 471 bool cm_in_bypass; 472 472 int force_clock_mode;/*every mode change.*/ 473 473 474 - bool nv12_iflip_vm_wa; 475 474 bool disable_dram_clock_change_vactive_support; 476 475 bool validate_dml_output; 477 476 bool enable_dmcub_surface_flip;
-3
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
··· 1435 1435 hubp->power_gated = false; 1436 1436 } 1437 1437 1438 - if (hubp->funcs->apply_PLAT_54186_wa && viewport_changed) 1439 - hubp->funcs->apply_PLAT_54186_wa(hubp, &plane_state->address); 1440 - 1441 1438 if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update) 1442 1439 hws->funcs.update_plane_addr(dc, pipe_ctx); 1443 1440
+2 -119
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
··· 225 225 SEC_VIEWPORT_Y_START_C, viewport_c->y); 226 226 } 227 227 228 - static void hubp21_apply_PLAT_54186_wa( 229 - struct hubp *hubp, 230 - const struct dc_plane_address *address) 231 - { 232 - struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 233 - struct dc_debug_options *debug = &hubp->ctx->dc->debug; 234 - unsigned int chroma_bpe = 2; 235 - unsigned int luma_addr_high_part = 0; 236 - unsigned int row_height = 0; 237 - unsigned int chroma_pitch = 0; 238 - unsigned int viewport_c_height = 0; 239 - unsigned int viewport_c_width = 0; 240 - unsigned int patched_viewport_height = 0; 241 - unsigned int patched_viewport_width = 0; 242 - unsigned int rotation_angle = 0; 243 - unsigned int pix_format = 0; 244 - unsigned int h_mirror_en = 0; 245 - unsigned int tile_blk_size = 64 * 1024; /* 64KB for 64KB SW, 4KB for 4KB SW */ 246 - 247 - 248 - if (!debug->nv12_iflip_vm_wa) 249 - return; 250 - 251 - REG_GET(DCHUBP_REQ_SIZE_CONFIG_C, 252 - PTE_ROW_HEIGHT_LINEAR_C, &row_height); 253 - 254 - REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 255 - PRI_VIEWPORT_WIDTH_C, &viewport_c_width, 256 - PRI_VIEWPORT_HEIGHT_C, &viewport_c_height); 257 - 258 - REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 259 - PRIMARY_SURFACE_ADDRESS_HIGH_C, &luma_addr_high_part); 260 - 261 - REG_GET(DCSURF_SURFACE_PITCH_C, 262 - PITCH_C, &chroma_pitch); 263 - 264 - chroma_pitch += 1; 265 - 266 - REG_GET_3(DCSURF_SURFACE_CONFIG, 267 - SURFACE_PIXEL_FORMAT, &pix_format, 268 - ROTATION_ANGLE, &rotation_angle, 269 - H_MIRROR_EN, &h_mirror_en); 270 - 271 - /* reset persistent cached data */ 272 - hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 273 - /* apply wa only for NV12 surface with scatter gather enabled with viewport > 512 along 274 - * the vertical direction*/ 275 - if (address->type != PLN_ADDR_TYPE_VIDEO_PROGRESSIVE || 276 - address->video_progressive.luma_addr.high_part == 0xf4) 277 - return; 278 - 279 - if ((rotation_angle == ROTATION_ANGLE_0 || rotation_angle == ROTATION_ANGLE_180) 280 - && viewport_c_height <= 512) 281 - return; 282 - 283 - if ((rotation_angle == ROTATION_ANGLE_90 || rotation_angle == ROTATION_ANGLE_270) 284 - && viewport_c_width <= 512) 285 - return; 286 - 287 - switch (rotation_angle) { 288 - case ROTATION_ANGLE_0: /* 0 degree rotation */ 289 - row_height = 128; 290 - patched_viewport_height = (viewport_c_height / row_height + 1) * row_height + 1; 291 - patched_viewport_width = viewport_c_width; 292 - hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 293 - break; 294 - case ROTATION_ANGLE_180: /* 180 degree rotation */ 295 - row_height = 128; 296 - patched_viewport_height = viewport_c_height + row_height; 297 - patched_viewport_width = viewport_c_width; 298 - hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - chroma_pitch * row_height * chroma_bpe; 299 - break; 300 - case ROTATION_ANGLE_90: /* 90 degree rotation */ 301 - row_height = 256; 302 - if (h_mirror_en) { 303 - patched_viewport_height = viewport_c_height; 304 - patched_viewport_width = viewport_c_width + row_height; 305 - hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 306 - } else { 307 - patched_viewport_height = viewport_c_height; 308 - patched_viewport_width = viewport_c_width + row_height; 309 - hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - tile_blk_size; 310 - } 311 - break; 312 - case ROTATION_ANGLE_270: /* 270 degree rotation */ 313 - row_height = 256; 314 - if (h_mirror_en) { 315 - patched_viewport_height = viewport_c_height; 316 - patched_viewport_width = viewport_c_width + row_height; 317 - hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - tile_blk_size; 318 - } else { 319 - patched_viewport_height = viewport_c_height; 320 - patched_viewport_width = viewport_c_width + row_height; 321 - hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 322 - } 323 - break; 324 - default: 325 - ASSERT(0); 326 - break; 327 - } 328 - 329 - /* catch cases where viewport keep growing */ 330 - ASSERT(patched_viewport_height && patched_viewport_height < 5000); 331 - ASSERT(patched_viewport_width && patched_viewport_width < 5000); 332 - 333 - REG_UPDATE_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 334 - PRI_VIEWPORT_WIDTH_C, patched_viewport_width, 335 - PRI_VIEWPORT_HEIGHT_C, patched_viewport_height); 336 - } 337 - 338 228 void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, 339 229 struct vm_system_aperture_param *apt) 340 230 { ··· 702 812 const struct dc_plane_address *address, 703 813 bool flip_immediate) 704 814 { 705 - struct dc_debug_options *debug = &hubp->ctx->dc->debug; 706 - struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 707 815 struct surface_flip_registers flip_regs = { 0 }; 708 816 709 817 flip_regs.vmid = address->vmid; ··· 747 859 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 748 860 address->video_progressive.luma_addr.high_part; 749 861 750 - if (debug->nv12_iflip_vm_wa) { 751 - flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 752 - address->video_progressive.chroma_addr.low_part + hubp21->PLAT_54186_wa_chroma_addr_offset; 753 - } else 754 - flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 755 - address->video_progressive.chroma_addr.low_part; 862 + flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 863 + address->video_progressive.chroma_addr.low_part; 756 864 757 865 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 758 866 address->video_progressive.chroma_addr.high_part; ··· 826 942 .set_blank = hubp1_set_blank, 827 943 .dcc_control = hubp1_dcc_control, 828 944 .mem_program_viewport = hubp21_set_viewport, 829 - .apply_PLAT_54186_wa = hubp21_apply_PLAT_54186_wa, 830 945 .set_cursor_attributes = hubp2_cursor_set_attributes, 831 946 .set_cursor_position = hubp1_cursor_set_position, 832 947 .hubp_clk_cntl = hubp1_clk_cntl,
-1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
··· 878 878 .scl_reset_length10 = true, 879 879 .sanity_checks = true, 880 880 .disable_48mhz_pwrdwn = false, 881 - .nv12_iflip_vm_wa = true, 882 881 .usbc_combo_phy_reset_wa = true 883 882 }; 884 883
-3
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
··· 104 104 const struct rect *viewport, 105 105 const struct rect *viewport_c); 106 106 107 - void (*apply_PLAT_54186_wa)(struct hubp *hubp, 108 - const struct dc_plane_address *address); 109 - 110 107 bool (*hubp_program_surface_flip_and_addr)( 111 108 struct hubp *hubp, 112 109 const struct dc_plane_address *address,