Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/display: OVT Update on InfoFrame and Mode Management

[Why]
Integrate OVT timing from DM to DC logic to update info frame
and mode management to report the resolution to the OS.

[How]
Reflect RID and Frame Rate to AVI InfoFrame Version 5.
Define new Timing Standard for OVT timing.

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Chris Park <Chris.Park@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Chris Park and committed by
Alex Deucher
427a60c1 7acd7ab0

+21 -2
+11
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
··· 2514 2514 union hdmi_info_packet hdmi_info; 2515 2515 union display_content_support support = {0}; 2516 2516 unsigned int vic = pipe_ctx->stream->timing.vic; 2517 + unsigned int rid = pipe_ctx->stream->timing.rid; 2518 + unsigned int fr_ind = pipe_ctx->stream->timing.fr_index; 2517 2519 enum dc_timing_3d_format format; 2518 2520 2519 2521 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet)); ··· 2706 2704 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) { 2707 2705 hdmi_info.bits.header.version = 4; 2708 2706 hdmi_info.bits.header.length = 14; 2707 + } 2708 + 2709 + if (rid != 0 && fr_ind != 0) { 2710 + hdmi_info.bits.header.version = 5; 2711 + hdmi_info.bits.header.length = 15; 2712 + 2713 + hdmi_info.bits.FR0_FR3 = fr_ind & 0xF; 2714 + hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1; 2715 + hdmi_info.bits.RID0_RID5 = rid; 2709 2716 } 2710 2717 2711 2718 /* pixel repetition
+2
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
··· 784 784 785 785 uint32_t vic; 786 786 uint32_t hdmi_vic; 787 + uint32_t rid; 788 + uint32_t fr_index; 787 789 enum dc_timing_3d_format timing_3d_format; 788 790 enum dc_color_depth display_color_depth; 789 791 enum dc_pixel_encoding pixel_encoding;
+2
drivers/gpu/drm/amd/display/dc/dc_types.h
··· 280 280 TIMING_SOURCE_EDID_CEA_SVD, 281 281 TIMING_SOURCE_EDID_CVT_3BYTE, 282 282 TIMING_SOURCE_EDID_4BYTE, 283 + TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB, 284 + TIMING_SOURCE_EDID_CEA_RID, 283 285 TIMING_SOURCE_VBIOS, 284 286 TIMING_SOURCE_CV, 285 287 TIMING_SOURCE_TV,
+6 -2
drivers/gpu/drm/amd/display/include/set_mode_types.h
··· 84 84 uint16_t bar_left; 85 85 uint16_t bar_right; 86 86 87 - uint8_t F140_F143:4; 87 + uint8_t FR0_FR3:4; 88 88 uint8_t ACE0_ACE3:4; 89 89 90 - uint8_t reserved[13]; 90 + uint8_t RID0_RID5:6; 91 + uint8_t FR4:1; 92 + uint8_t F157:1; 93 + 94 + uint8_t reserved[12]; 91 95 } bits; 92 96 93 97 struct info_packet_raw_data packet_raw_data;