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kernel os linux

dt-bindings: phy: Fix node descriptions in uniphier-phy example

Prior to adding dt-bindings for SoC-dependent controllers, rename the
phy nodes and their parent nodes to the generic names in the example.

And drop parent nodes of each phy as they are not directly necessary here.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]
Link: https://lore.kernel.org/r/20221213082449.2721-8-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>

authored by

Kunihiko Hayashi and committed by
Rob Herring
4278eabe a1e616a5

+43 -71
+8 -16
Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml
··· 117 117 118 118 examples: 119 119 - | 120 - ahci-glue@65700000 { 121 - compatible = "socionext,uniphier-pxs3-ahci-glue", 122 - "simple-mfd"; 123 - #address-cells = <1>; 124 - #size-cells = <1>; 125 - ranges = <0 0x65700000 0x100>; 126 - 127 - ahci_phy: phy@10 { 128 - compatible = "socionext,uniphier-pxs3-ahci-phy"; 129 - reg = <0x10 0x10>; 130 - #phy-cells = <0>; 131 - clock-names = "link", "phy"; 132 - clocks = <&sys_clk 28>, <&sys_clk 30>; 133 - reset-names = "link", "phy"; 134 - resets = <&sys_rst 28>, <&sys_rst 30>; 135 - }; 120 + ahci_phy: phy@10 { 121 + compatible = "socionext,uniphier-pxs3-ahci-phy"; 122 + reg = <0x10 0x10>; 123 + #phy-cells = <0>; 124 + clock-names = "link", "phy"; 125 + clocks = <&sys_clk 28>, <&sys_clk 30>; 126 + reset-names = "link", "phy"; 127 + resets = <&sys_rst 28>, <&sys_rst 30>; 136 128 };
+15 -20
Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml
··· 61 61 - | 62 62 // The UniPhier usb2-phy should be a subnode of a "syscon" compatible node. 63 63 64 - soc-glue@5f800000 { 65 - compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon"; 66 - reg = <0x5f800000 0x2000>; 64 + usb-hub { 65 + compatible = "socionext,uniphier-ld11-usb2-phy"; 66 + #address-cells = <1>; 67 + #size-cells = <0>; 67 68 68 - usb-controller { 69 - compatible = "socionext,uniphier-ld11-usb2-phy"; 70 - #address-cells = <1>; 71 - #size-cells = <0>; 69 + usb_phy0: phy@0 { 70 + reg = <0>; 71 + #phy-cells = <0>; 72 + }; 72 73 73 - usb_phy0: phy@0 { 74 - reg = <0>; 75 - #phy-cells = <0>; 76 - }; 74 + usb_phy1: phy@1 { 75 + reg = <1>; 76 + #phy-cells = <0>; 77 + }; 77 78 78 - usb_phy1: phy@1 { 79 - reg = <1>; 80 - #phy-cells = <0>; 81 - }; 82 - 83 - usb_phy2: phy@2 { 84 - reg = <2>; 85 - #phy-cells = <0>; 86 - }; 79 + usb_phy2: phy@2 { 80 + reg = <2>; 81 + #phy-cells = <0>; 87 82 }; 88 83 };
+11 -18
Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml
··· 146 146 147 147 examples: 148 148 - | 149 - usb-glue@65b00000 { 150 - compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd"; 151 - #address-cells = <1>; 152 - #size-cells = <1>; 153 - ranges = <0 0x65b00000 0x400>; 154 - 155 - usb_hsphy0: hs-phy@200 { 156 - compatible = "socionext,uniphier-ld20-usb3-hsphy"; 157 - reg = <0x200 0x10>; 158 - #phy-cells = <0>; 159 - clock-names = "link", "phy"; 160 - clocks = <&sys_clk 14>, <&sys_clk 16>; 161 - reset-names = "link", "phy"; 162 - resets = <&sys_rst 14>, <&sys_rst 16>; 163 - vbus-supply = <&usb_vbus0>; 164 - nvmem-cell-names = "rterm", "sel_t", "hs_i"; 165 - nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>; 166 - }; 149 + usb_hsphy0: phy@200 { 150 + compatible = "socionext,uniphier-ld20-usb3-hsphy"; 151 + reg = <0x200 0x10>; 152 + #phy-cells = <0>; 153 + clock-names = "link", "phy"; 154 + clocks = <&sys_clk 14>, <&sys_clk 16>; 155 + reset-names = "link", "phy"; 156 + resets = <&sys_rst 14>, <&sys_rst 16>; 157 + vbus-supply = <&usb_vbus0>; 158 + nvmem-cell-names = "rterm", "sel_t", "hs_i"; 159 + nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>; 167 160 };
+9 -17
Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml
··· 131 131 132 132 examples: 133 133 - | 134 - usb-glue@65b00000 { 135 - compatible = "socionext,uniphier-ld20-dwc3-glue", 136 - "simple-mfd"; 137 - #address-cells = <1>; 138 - #size-cells = <1>; 139 - ranges = <0 0x65b00000 0x400>; 140 - 141 - usb_ssphy0: ss-phy@300 { 142 - compatible = "socionext,uniphier-ld20-usb3-ssphy"; 143 - reg = <0x300 0x10>; 144 - #phy-cells = <0>; 145 - clock-names = "link", "phy"; 146 - clocks = <&sys_clk 14>, <&sys_clk 16>; 147 - reset-names = "link", "phy"; 148 - resets = <&sys_rst 14>, <&sys_rst 16>; 149 - vbus-supply = <&usb_vbus0>; 150 - }; 134 + usb_ssphy0: phy@300 { 135 + compatible = "socionext,uniphier-ld20-usb3-ssphy"; 136 + reg = <0x300 0x10>; 137 + #phy-cells = <0>; 138 + clock-names = "link", "phy"; 139 + clocks = <&sys_clk 14>, <&sys_clk 16>; 140 + reset-names = "link", "phy"; 141 + resets = <&sys_rst 14>, <&sys_rst 16>; 142 + vbus-supply = <&usb_vbus0>; 151 143 };