tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge tag 'hisi-arm64-dt-for-4.20' of git://github.com/hisilicon/linux-hisi into next/dt
ARM64: DT: Hisilicon SoC DT updates for 4.20
- Add missing clocks for Hi6220
- Switch to updated coresight bindings for Hi6220
- Add DT bindings and support for Hi3670 SoC and HiKey970 board
* tag 'hisi-arm64-dt-for-4.20' of git://github.com/hisilicon/linux-hisi:
arm64: dts: Add devicetree support for HiKey970 board
dt-bindings: arm: hisilicon: Add binding for HiKey970 board
arm64: dts: Add devicetree for Hisilicon Hi3670 SoC
dt-bindings: arm: hisilicon: Add binding for Hi3670 SoC
arm64: dts: hi6220: Update coresight bindings for hardware ports
arm64: dts: hisilicon: Add missing clocks property for CPUs
Signed-off-by: Olof Johansson <olof@lixom.net>
+299
-95
+8
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+8
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
···
8
8
Required root node properties:
9
9
- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
10
10
11
+
Hi3670 SoC
12
+
Required root node properties:
13
+
- compatible = "hisilicon,hi3670";
14
+
15
+
HiKey970 Board
16
+
Required root node properties:
17
+
- compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
18
+
11
19
Hi3798cv200 SoC
12
20
Required root node properties:
13
21
- compatible = "hisilicon,hi3798cv200";
+1
arch/arm64/boot/dts/hisilicon/Makefile
+1
arch/arm64/boot/dts/hisilicon/Makefile
+35
arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
+35
arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* dts file for Hisilicon HiKey970 Development Board
4
+
*
5
+
* Copyright (C) 2016, Hisilicon Ltd.
6
+
* Copyright (C) 2018, Linaro Ltd.
7
+
*
8
+
*/
9
+
10
+
/dts-v1/;
11
+
12
+
#include "hi3670.dtsi"
13
+
14
+
/ {
15
+
model = "HiKey970";
16
+
compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
17
+
18
+
aliases {
19
+
serial6 = &uart6; /* console UART */
20
+
};
21
+
22
+
chosen {
23
+
stdout-path = "serial6:115200n8";
24
+
};
25
+
26
+
memory@0 {
27
+
device_type = "memory";
28
+
/* expect bootloader to fill in this region */
29
+
reg = <0x0 0x0 0x0 0x0>;
30
+
};
31
+
};
32
+
33
+
&uart6 {
34
+
status = "okay";
35
+
};
+162
arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+162
arch/arm64/boot/dts/hisilicon/hi3670.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* dts file for Hisilicon Hi3670 SoC
4
+
*
5
+
* Copyright (C) 2016, Hisilicon Ltd.
6
+
* Copyright (C) 2018, Linaro Ltd.
7
+
*/
8
+
9
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
10
+
11
+
/ {
12
+
compatible = "hisilicon,hi3670";
13
+
interrupt-parent = <&gic>;
14
+
#address-cells = <2>;
15
+
#size-cells = <2>;
16
+
17
+
psci {
18
+
compatible = "arm,psci-0.2";
19
+
method = "smc";
20
+
};
21
+
22
+
cpus {
23
+
#address-cells = <2>;
24
+
#size-cells = <0>;
25
+
26
+
cpu-map {
27
+
cluster0 {
28
+
core0 {
29
+
cpu = <&cpu0>;
30
+
};
31
+
core1 {
32
+
cpu = <&cpu1>;
33
+
};
34
+
core2 {
35
+
cpu = <&cpu2>;
36
+
};
37
+
core3 {
38
+
cpu = <&cpu3>;
39
+
};
40
+
};
41
+
cluster1 {
42
+
core0 {
43
+
cpu = <&cpu4>;
44
+
};
45
+
core1 {
46
+
cpu = <&cpu5>;
47
+
};
48
+
core2 {
49
+
cpu = <&cpu6>;
50
+
};
51
+
core3 {
52
+
cpu = <&cpu7>;
53
+
};
54
+
};
55
+
};
56
+
57
+
cpu0: cpu@0 {
58
+
compatible = "arm,cortex-a53", "arm,armv8";
59
+
device_type = "cpu";
60
+
reg = <0x0 0x0>;
61
+
enable-method = "psci";
62
+
};
63
+
64
+
cpu1: cpu@1 {
65
+
compatible = "arm,cortex-a53", "arm,armv8";
66
+
device_type = "cpu";
67
+
reg = <0x0 0x1>;
68
+
enable-method = "psci";
69
+
};
70
+
71
+
cpu2: cpu@2 {
72
+
compatible = "arm,cortex-a53", "arm,armv8";
73
+
device_type = "cpu";
74
+
reg = <0x0 0x2>;
75
+
enable-method = "psci";
76
+
};
77
+
78
+
cpu3: cpu@3 {
79
+
compatible = "arm,cortex-a53", "arm,armv8";
80
+
device_type = "cpu";
81
+
reg = <0x0 0x3>;
82
+
enable-method = "psci";
83
+
};
84
+
85
+
cpu4: cpu@100 {
86
+
compatible = "arm,cortex-a73", "arm,armv8";
87
+
device_type = "cpu";
88
+
reg = <0x0 0x100>;
89
+
enable-method = "psci";
90
+
};
91
+
92
+
cpu5: cpu@101 {
93
+
compatible = "arm,cortex-a73", "arm,armv8";
94
+
device_type = "cpu";
95
+
reg = <0x0 0x101>;
96
+
enable-method = "psci";
97
+
};
98
+
99
+
cpu6: cpu@102 {
100
+
compatible = "arm,cortex-a73", "arm,armv8";
101
+
device_type = "cpu";
102
+
reg = <0x0 0x102>;
103
+
enable-method = "psci";
104
+
};
105
+
106
+
cpu7: cpu@103 {
107
+
compatible = "arm,cortex-a73", "arm,armv8";
108
+
device_type = "cpu";
109
+
reg = <0x0 0x103>;
110
+
enable-method = "psci";
111
+
};
112
+
};
113
+
114
+
gic: interrupt-controller@e82b0000 {
115
+
compatible = "arm,gic-400";
116
+
reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
117
+
<0x0 0xe82b2000 0 0x2000>, /* GICC */
118
+
<0x0 0xe82b4000 0 0x2000>, /* GICH */
119
+
<0x0 0xe82b6000 0 0x2000>; /* GICV */
120
+
#interrupt-cells = <3>;
121
+
#address-cells = <0>;
122
+
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
123
+
IRQ_TYPE_LEVEL_HIGH)>;
124
+
interrupt-controller;
125
+
};
126
+
127
+
timer {
128
+
compatible = "arm,armv8-timer";
129
+
interrupt-parent = <&gic>;
130
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
131
+
IRQ_TYPE_LEVEL_LOW)>,
132
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
133
+
IRQ_TYPE_LEVEL_LOW)>,
134
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
135
+
IRQ_TYPE_LEVEL_LOW)>,
136
+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
137
+
IRQ_TYPE_LEVEL_LOW)>;
138
+
clock-frequency = <1920000>;
139
+
};
140
+
141
+
soc {
142
+
compatible = "simple-bus";
143
+
#address-cells = <2>;
144
+
#size-cells = <2>;
145
+
ranges;
146
+
147
+
uart6_clk: clk_19_2M {
148
+
compatible = "fixed-clock";
149
+
#clock-cells = <0>;
150
+
clock-frequency = <19200000>;
151
+
};
152
+
153
+
uart6: serial@fff32000 {
154
+
compatible = "arm,pl011", "arm,primecell";
155
+
reg = <0x0 0xfff32000 0x0 0x1000>;
156
+
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
157
+
clocks = <&uart6_clk &uart6_clk>;
158
+
clock-names = "uartclk", "apb_pclk";
159
+
status = "disabled";
160
+
};
161
+
};
162
+
};
+86
-95
arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
+86
-95
arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
···
20
20
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
21
21
clock-names = "apb_pclk";
22
22
23
-
ports {
24
-
#address-cells = <1>;
25
-
#size-cells = <0>;
26
-
27
-
port@0 {
28
-
reg = <0>;
23
+
out-ports {
24
+
port {
29
25
soc_funnel_out: endpoint {
30
26
remote-endpoint =
31
27
<&etf_in>;
32
28
};
33
29
};
30
+
};
34
31
35
-
port@1 {
36
-
reg = <0>;
32
+
in-ports {
33
+
port {
37
34
soc_funnel_in: endpoint {
38
-
slave-mode;
39
35
remote-endpoint =
40
36
<&acpu_funnel_out>;
41
37
};
···
45
49
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
46
50
clock-names = "apb_pclk";
47
51
48
-
ports {
49
-
#address-cells = <1>;
50
-
#size-cells = <0>;
51
-
52
-
port@0 {
53
-
reg = <0>;
52
+
in-ports {
53
+
port {
54
54
etf_in: endpoint {
55
-
slave-mode;
56
55
remote-endpoint =
57
56
<&soc_funnel_out>;
58
57
};
59
58
};
59
+
};
60
60
61
-
port@1 {
62
-
reg = <0>;
61
+
out-ports {
62
+
port {
63
63
etf_out: endpoint {
64
64
remote-endpoint =
65
65
<&replicator_in>;
···
69
77
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
70
78
clock-names = "apb_pclk";
71
79
72
-
ports {
73
-
#address-cells = <1>;
74
-
#size-cells = <0>;
75
-
76
-
port@0 {
77
-
reg = <0>;
80
+
in-ports {
81
+
port {
78
82
replicator_in: endpoint {
79
-
slave-mode;
80
83
remote-endpoint =
81
84
<&etf_out>;
82
85
};
83
86
};
87
+
};
84
88
85
-
port@1 {
89
+
out-ports {
90
+
#address-cells = <1>;
91
+
#size-cells = <0>;
92
+
93
+
port@0 {
86
94
reg = <0>;
87
95
replicator_out0: endpoint {
88
96
remote-endpoint =
···
90
98
};
91
99
};
92
100
93
-
port@2 {
101
+
port@1 {
94
102
reg = <1>;
95
103
replicator_out1: endpoint {
96
104
remote-endpoint =
···
106
114
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
107
115
clock-names = "apb_pclk";
108
116
109
-
ports {
110
-
#address-cells = <1>;
111
-
#size-cells = <0>;
112
-
113
-
port@0 {
114
-
reg = <0>;
117
+
in-ports {
118
+
port {
115
119
etr_in: endpoint {
116
-
slave-mode;
117
120
remote-endpoint =
118
121
<&replicator_out0>;
119
122
};
···
122
135
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
123
136
clock-names = "apb_pclk";
124
137
125
-
ports {
126
-
#address-cells = <1>;
127
-
#size-cells = <0>;
128
-
129
-
port@0 {
130
-
reg = <0>;
138
+
in-ports {
139
+
port {
131
140
tpiu_in: endpoint {
132
-
slave-mode;
133
141
remote-endpoint =
134
142
<&replicator_out1>;
135
143
};
···
138
156
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
139
157
clock-names = "apb_pclk";
140
158
141
-
ports {
142
-
#address-cells = <1>;
143
-
#size-cells = <0>;
144
-
145
-
port@0 {
146
-
reg = <0>;
159
+
out-ports {
160
+
port {
147
161
acpu_funnel_out: endpoint {
148
162
remote-endpoint =
149
163
<&soc_funnel_in>;
150
164
};
151
165
};
166
+
};
152
167
153
-
port@1 {
168
+
in-ports {
169
+
#address-cells = <1>;
170
+
#size-cells = <0>;
171
+
172
+
port@0 {
154
173
reg = <0>;
155
174
acpu_funnel_in0: endpoint {
156
-
slave-mode;
157
175
remote-endpoint =
158
176
<&etm0_out>;
159
177
};
160
178
};
161
179
162
-
port@2 {
180
+
port@1 {
163
181
reg = <1>;
164
182
acpu_funnel_in1: endpoint {
165
-
slave-mode;
166
183
remote-endpoint =
167
184
<&etm1_out>;
168
185
};
169
186
};
170
187
171
-
port@3 {
188
+
port@2 {
172
189
reg = <2>;
173
190
acpu_funnel_in2: endpoint {
174
-
slave-mode;
175
191
remote-endpoint =
176
192
<&etm2_out>;
177
193
};
178
194
};
179
195
180
-
port@4 {
196
+
port@3 {
181
197
reg = <3>;
182
198
acpu_funnel_in3: endpoint {
183
-
slave-mode;
184
199
remote-endpoint =
185
200
<&etm3_out>;
186
201
};
187
202
};
188
203
189
-
port@5 {
204
+
port@4 {
190
205
reg = <4>;
191
206
acpu_funnel_in4: endpoint {
192
-
slave-mode;
193
207
remote-endpoint =
194
208
<&etm4_out>;
195
209
};
196
210
};
197
211
198
-
port@6 {
212
+
port@5 {
199
213
reg = <5>;
200
214
acpu_funnel_in5: endpoint {
201
-
slave-mode;
202
215
remote-endpoint =
203
216
<&etm5_out>;
204
217
};
205
218
};
206
219
207
-
port@7 {
220
+
port@6 {
208
221
reg = <6>;
209
222
acpu_funnel_in6: endpoint {
210
-
slave-mode;
211
223
remote-endpoint =
212
224
<&etm6_out>;
213
225
};
214
226
};
215
227
216
-
port@8 {
228
+
port@7 {
217
229
reg = <7>;
218
230
acpu_funnel_in7: endpoint {
219
-
slave-mode;
220
231
remote-endpoint =
221
232
<&etm7_out>;
222
233
};
···
226
251
227
252
cpu = <&cpu0>;
228
253
229
-
port {
230
-
etm0_out: endpoint {
231
-
remote-endpoint =
232
-
<&acpu_funnel_in0>;
254
+
out-ports {
255
+
port {
256
+
etm0_out: endpoint {
257
+
remote-endpoint =
258
+
<&acpu_funnel_in0>;
259
+
};
233
260
};
234
261
};
235
262
};
···
245
268
246
269
cpu = <&cpu1>;
247
270
248
-
port {
249
-
etm1_out: endpoint {
250
-
remote-endpoint =
251
-
<&acpu_funnel_in1>;
271
+
out-ports {
272
+
port {
273
+
etm1_out: endpoint {
274
+
remote-endpoint =
275
+
<&acpu_funnel_in1>;
276
+
};
252
277
};
253
278
};
254
279
};
···
264
285
265
286
cpu = <&cpu2>;
266
287
267
-
port {
268
-
etm2_out: endpoint {
269
-
remote-endpoint =
270
-
<&acpu_funnel_in2>;
288
+
out-ports {
289
+
port {
290
+
etm2_out: endpoint {
291
+
remote-endpoint =
292
+
<&acpu_funnel_in2>;
293
+
};
271
294
};
272
295
};
273
296
};
···
283
302
284
303
cpu = <&cpu3>;
285
304
286
-
port {
287
-
etm3_out: endpoint {
288
-
remote-endpoint =
289
-
<&acpu_funnel_in3>;
305
+
out-ports {
306
+
port {
307
+
etm3_out: endpoint {
308
+
remote-endpoint =
309
+
<&acpu_funnel_in3>;
310
+
};
290
311
};
291
312
};
292
313
};
···
302
319
303
320
cpu = <&cpu4>;
304
321
305
-
port {
306
-
etm4_out: endpoint {
307
-
remote-endpoint =
308
-
<&acpu_funnel_in4>;
322
+
out-ports {
323
+
port {
324
+
etm4_out: endpoint {
325
+
remote-endpoint =
326
+
<&acpu_funnel_in4>;
327
+
};
309
328
};
310
329
};
311
330
};
···
321
336
322
337
cpu = <&cpu5>;
323
338
324
-
port {
325
-
etm5_out: endpoint {
326
-
remote-endpoint =
327
-
<&acpu_funnel_in5>;
339
+
out-ports {
340
+
port {
341
+
etm5_out: endpoint {
342
+
remote-endpoint =
343
+
<&acpu_funnel_in5>;
344
+
};
328
345
};
329
346
};
330
347
};
···
340
353
341
354
cpu = <&cpu6>;
342
355
343
-
port {
344
-
etm6_out: endpoint {
345
-
remote-endpoint =
346
-
<&acpu_funnel_in6>;
356
+
out-ports {
357
+
port {
358
+
etm6_out: endpoint {
359
+
remote-endpoint =
360
+
<&acpu_funnel_in6>;
361
+
};
347
362
};
348
363
};
349
364
};
···
359
370
360
371
cpu = <&cpu7>;
361
372
362
-
port {
363
-
etm7_out: endpoint {
364
-
remote-endpoint =
365
-
<&acpu_funnel_in7>;
373
+
out-ports {
374
+
port {
375
+
etm7_out: endpoint {
376
+
remote-endpoint =
377
+
<&acpu_funnel_in7>;
378
+
};
366
379
};
367
380
};
368
381
};
+7
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+7
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
···
99
99
reg = <0x0 0x1>;
100
100
enable-method = "psci";
101
101
next-level-cache = <&CLUSTER0_L2>;
102
+
clocks = <&stub_clock 0>;
102
103
operating-points-v2 = <&cpu_opp_table>;
103
104
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
104
105
#cooling-cells = <2>; /* min followed by max */
···
112
111
reg = <0x0 0x2>;
113
112
enable-method = "psci";
114
113
next-level-cache = <&CLUSTER0_L2>;
114
+
clocks = <&stub_clock 0>;
115
115
operating-points-v2 = <&cpu_opp_table>;
116
116
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
117
117
#cooling-cells = <2>; /* min followed by max */
···
125
123
reg = <0x0 0x3>;
126
124
enable-method = "psci";
127
125
next-level-cache = <&CLUSTER0_L2>;
126
+
clocks = <&stub_clock 0>;
128
127
operating-points-v2 = <&cpu_opp_table>;
129
128
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
130
129
#cooling-cells = <2>; /* min followed by max */
···
138
135
reg = <0x0 0x100>;
139
136
enable-method = "psci";
140
137
next-level-cache = <&CLUSTER1_L2>;
138
+
clocks = <&stub_clock 0>;
141
139
operating-points-v2 = <&cpu_opp_table>;
142
140
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
143
141
#cooling-cells = <2>; /* min followed by max */
···
151
147
reg = <0x0 0x101>;
152
148
enable-method = "psci";
153
149
next-level-cache = <&CLUSTER1_L2>;
150
+
clocks = <&stub_clock 0>;
154
151
operating-points-v2 = <&cpu_opp_table>;
155
152
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
156
153
#cooling-cells = <2>; /* min followed by max */
···
164
159
reg = <0x0 0x102>;
165
160
enable-method = "psci";
166
161
next-level-cache = <&CLUSTER1_L2>;
162
+
clocks = <&stub_clock 0>;
167
163
operating-points-v2 = <&cpu_opp_table>;
168
164
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
169
165
#cooling-cells = <2>; /* min followed by max */
···
177
171
reg = <0x0 0x103>;
178
172
enable-method = "psci";
179
173
next-level-cache = <&CLUSTER1_L2>;
174
+
clocks = <&stub_clock 0>;
180
175
operating-points-v2 = <&cpu_opp_table>;
181
176
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
182
177
#cooling-cells = <2>; /* min followed by max */