tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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powerpc/traps: fix machine check handlers to use pr_cont()

When printing the machine check cause, the cause appears on the
following line due to bad use of printk without \n:

[ 33.663993] Machine check in kernel mode.
[ 33.664011] Caused by (from SRR1=9032):
[ 33.664036] Data access error at address c90c8000

This patch fixes it by using pr_cont() for the second part:

[ 133.258131] Machine check in kernel mode.
[ 133.258146] Caused by (from SRR1=9032): Data access error at address c90c8000

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

authored by

Christophe Leroy and committed by
Michael Ellerman 422123cc bde1a133

+41 -41
+39 -39
arch/powerpc/kernel/traps.c
··· 535 535 printk("Caused by (from MCSR=%lx): ", reason); 536 536 537 537 if (reason & MCSR_MCP) 538 - printk("Machine Check Signal\n"); 538 + pr_cont("Machine Check Signal\n"); 539 539 540 540 if (reason & MCSR_ICPERR) { 541 - printk("Instruction Cache Parity Error\n"); 541 + pr_cont("Instruction Cache Parity Error\n"); 542 542 543 543 /* 544 544 * This is recoverable by invalidating the i-cache. ··· 556 556 } 557 557 558 558 if (reason & MCSR_DCPERR_MC) { 559 - printk("Data Cache Parity Error\n"); 559 + pr_cont("Data Cache Parity Error\n"); 560 560 561 561 /* 562 562 * In write shadow mode we auto-recover from the error, but it ··· 575 575 } 576 576 577 577 if (reason & MCSR_L2MMU_MHIT) { 578 - printk("Hit on multiple TLB entries\n"); 578 + pr_cont("Hit on multiple TLB entries\n"); 579 579 recoverable = 0; 580 580 } 581 581 582 582 if (reason & MCSR_NMI) 583 - printk("Non-maskable interrupt\n"); 583 + pr_cont("Non-maskable interrupt\n"); 584 584 585 585 if (reason & MCSR_IF) { 586 - printk("Instruction Fetch Error Report\n"); 586 + pr_cont("Instruction Fetch Error Report\n"); 587 587 recoverable = 0; 588 588 } 589 589 590 590 if (reason & MCSR_LD) { 591 - printk("Load Error Report\n"); 591 + pr_cont("Load Error Report\n"); 592 592 recoverable = 0; 593 593 } 594 594 595 595 if (reason & MCSR_ST) { 596 - printk("Store Error Report\n"); 596 + pr_cont("Store Error Report\n"); 597 597 recoverable = 0; 598 598 } 599 599 600 600 if (reason & MCSR_LDG) { 601 - printk("Guarded Load Error Report\n"); 601 + pr_cont("Guarded Load Error Report\n"); 602 602 recoverable = 0; 603 603 } 604 604 605 605 if (reason & MCSR_TLBSYNC) 606 - printk("Simultaneous tlbsync operations\n"); 606 + pr_cont("Simultaneous tlbsync operations\n"); 607 607 608 608 if (reason & MCSR_BSL2_ERR) { 609 - printk("Level 2 Cache Error\n"); 609 + pr_cont("Level 2 Cache Error\n"); 610 610 recoverable = 0; 611 611 } 612 612 ··· 616 616 addr = mfspr(SPRN_MCAR); 617 617 addr |= (u64)mfspr(SPRN_MCARU) << 32; 618 618 619 - printk("Machine Check %s Address: %#llx\n", 619 + pr_cont("Machine Check %s Address: %#llx\n", 620 620 reason & MCSR_MEA ? "Effective" : "Physical", addr); 621 621 } 622 622 ··· 640 640 printk("Caused by (from MCSR=%lx): ", reason); 641 641 642 642 if (reason & MCSR_MCP) 643 - printk("Machine Check Signal\n"); 643 + pr_cont("Machine Check Signal\n"); 644 644 if (reason & MCSR_ICPERR) 645 - printk("Instruction Cache Parity Error\n"); 645 + pr_cont("Instruction Cache Parity Error\n"); 646 646 if (reason & MCSR_DCP_PERR) 647 - printk("Data Cache Push Parity Error\n"); 647 + pr_cont("Data Cache Push Parity Error\n"); 648 648 if (reason & MCSR_DCPERR) 649 - printk("Data Cache Parity Error\n"); 649 + pr_cont("Data Cache Parity Error\n"); 650 650 if (reason & MCSR_BUS_IAERR) 651 - printk("Bus - Instruction Address Error\n"); 651 + pr_cont("Bus - Instruction Address Error\n"); 652 652 if (reason & MCSR_BUS_RAERR) 653 - printk("Bus - Read Address Error\n"); 653 + pr_cont("Bus - Read Address Error\n"); 654 654 if (reason & MCSR_BUS_WAERR) 655 - printk("Bus - Write Address Error\n"); 655 + pr_cont("Bus - Write Address Error\n"); 656 656 if (reason & MCSR_BUS_IBERR) 657 - printk("Bus - Instruction Data Error\n"); 657 + pr_cont("Bus - Instruction Data Error\n"); 658 658 if (reason & MCSR_BUS_RBERR) 659 - printk("Bus - Read Data Bus Error\n"); 659 + pr_cont("Bus - Read Data Bus Error\n"); 660 660 if (reason & MCSR_BUS_WBERR) 661 - printk("Bus - Write Data Bus Error\n"); 661 + pr_cont("Bus - Write Data Bus Error\n"); 662 662 if (reason & MCSR_BUS_IPERR) 663 - printk("Bus - Instruction Parity Error\n"); 663 + pr_cont("Bus - Instruction Parity Error\n"); 664 664 if (reason & MCSR_BUS_RPERR) 665 - printk("Bus - Read Parity Error\n"); 665 + pr_cont("Bus - Read Parity Error\n"); 666 666 667 667 return 0; 668 668 } ··· 680 680 printk("Caused by (from MCSR=%lx): ", reason); 681 681 682 682 if (reason & MCSR_MCP) 683 - printk("Machine Check Signal\n"); 683 + pr_cont("Machine Check Signal\n"); 684 684 if (reason & MCSR_CP_PERR) 685 - printk("Cache Push Parity Error\n"); 685 + pr_cont("Cache Push Parity Error\n"); 686 686 if (reason & MCSR_CPERR) 687 - printk("Cache Parity Error\n"); 687 + pr_cont("Cache Parity Error\n"); 688 688 if (reason & MCSR_EXCP_ERR) 689 - printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 689 + pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 690 690 if (reason & MCSR_BUS_IRERR) 691 - printk("Bus - Read Bus Error on instruction fetch\n"); 691 + pr_cont("Bus - Read Bus Error on instruction fetch\n"); 692 692 if (reason & MCSR_BUS_DRERR) 693 - printk("Bus - Read Bus Error on data load\n"); 693 + pr_cont("Bus - Read Bus Error on data load\n"); 694 694 if (reason & MCSR_BUS_WRERR) 695 - printk("Bus - Write Bus Error on buffered store or cache line push\n"); 695 + pr_cont("Bus - Write Bus Error on buffered store or cache line push\n"); 696 696 697 697 return 0; 698 698 } ··· 705 705 printk("Caused by (from SRR1=%lx): ", reason); 706 706 switch (reason & 0x601F0000) { 707 707 case 0x80000: 708 - printk("Machine check signal\n"); 708 + pr_cont("Machine check signal\n"); 709 709 break; 710 710 case 0: /* for 601 */ 711 711 case 0x40000: 712 712 case 0x140000: /* 7450 MSS error and TEA */ 713 - printk("Transfer error ack signal\n"); 713 + pr_cont("Transfer error ack signal\n"); 714 714 break; 715 715 case 0x20000: 716 - printk("Data parity error signal\n"); 716 + pr_cont("Data parity error signal\n"); 717 717 break; 718 718 case 0x10000: 719 - printk("Address parity error signal\n"); 719 + pr_cont("Address parity error signal\n"); 720 720 break; 721 721 case 0x20000000: 722 - printk("L1 Data Cache error\n"); 722 + pr_cont("L1 Data Cache error\n"); 723 723 break; 724 724 case 0x40000000: 725 - printk("L1 Instruction Cache error\n"); 725 + pr_cont("L1 Instruction Cache error\n"); 726 726 break; 727 727 case 0x00100000: 728 - printk("L2 data cache parity error\n"); 728 + pr_cont("L2 data cache parity error\n"); 729 729 break; 730 730 default: 731 - printk("Unknown values in msr\n"); 731 + pr_cont("Unknown values in msr\n"); 732 732 } 733 733 return 0; 734 734 }
+2 -2
arch/powerpc/platforms/8xx/machine_check.c
··· 18 18 pr_err("Machine check in kernel mode.\n"); 19 19 pr_err("Caused by (from SRR1=%lx): ", reason); 20 20 if (reason & 0x40000000) 21 - pr_err("Fetch error at address %lx\n", regs->nip); 21 + pr_cont("Fetch error at address %lx\n", regs->nip); 22 22 else 23 - pr_err("Data access error at address %lx\n", regs->dar); 23 + pr_cont("Data access error at address %lx\n", regs->dar); 24 24 25 25 #ifdef CONFIG_PCI 26 26 /* the qspan pci read routines can cause machine checks -- Cort