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Documentation: Reformat Oxford Semiconductor PCIe (Tornado) 950
Reformat Oxford Semiconductor PCIe (Tornado) 950 description in terms of
reStructuredText markup, fixing warnings with `make htmldocs'. While at
it remove typos: s/the the/the/ and s/the/then/ in lines changed anyway.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2205131721110.10656@angie.orcam.me.uk
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Maciej W. Rozycki
and committed by
Greg Kroah-Hartman
421bdf53
7b0364ea
+72
-70
+72
-70
Documentation/misc-devices/oxsemi-tornado.rst
+72
-70
Documentation/misc-devices/oxsemi-tornado.rst
···
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is unaware of the extra clock controls available.
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The oversampling rate is programmed with the TCR register and the clock
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prescaler is programmed with the CPR/CPR2 register pair[1][2][3][4].
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To switch away from the default value of 33.875 for the prescaler the
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the enhanced mode has to be explicitly enabled though, by setting bit 4
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of the EFR. In that mode setting bit 7 in the MCR enables the prescaler
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or otherwise it is bypassed as if the value of 1 was used. Additionally
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writing any value to CPR clears CPR2 for compatibility with old software
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written for older conventional PCI Oxford Semiconductor devices that do
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not have the extra prescaler's 9th bit in CPR2, so the CPR/CPR2 register
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pair has to be programmed in the right order.
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prescaler is programmed with the CPR/CPR2 register pair [OX200]_ [OX952]_
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[OX954]_ [OX958]_. To switch away from the default value of 33.875 for
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the prescaler the enhanced mode has to be explicitly enabled though, by
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setting bit 4 of the EFR. In that mode setting bit 7 in the MCR enables
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the prescaler or otherwise it is bypassed as if the value of 1 was used.
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Additionally writing any value to CPR clears CPR2 for compatibility with
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old software written for older conventional PCI Oxford Semiconductor
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devices that do not have the extra prescaler's 9th bit in CPR2, so the
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CPR/CPR2 register pair has to be programmed in the right order.
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By using these parameters rates from 15625000bps down to 1bps can be
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obtained, with either exact or highly-accurate actual bit rates for
···
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the requested rate (r), the actual rate yielded (a) and its deviation
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from the requested rate (d), and the values of the oversampling rate
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(tcr), the clock prescaler (cpr) and the divisor (div) produced by the
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new `get_divisor' handler:
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new ``get_divisor`` handler:
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r: 15625000, a: 15625000.00, d: 0.0000%, tcr: 4, cpr: 1.000, div: 1
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r: 12500000, a: 12500000.00, d: 0.0000%, tcr: 5, cpr: 1.000, div: 1
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r: 10416666, a: 10416666.67, d: 0.0000%, tcr: 6, cpr: 1.000, div: 1
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r: 8928571, a: 8928571.43, d: 0.0000%, tcr: 7, cpr: 1.000, div: 1
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r: 7812500, a: 7812500.00, d: 0.0000%, tcr: 8, cpr: 1.000, div: 1
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r: 4000000, a: 4000000.00, d: 0.0000%, tcr: 5, cpr: 3.125, div: 1
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r: 3686400, a: 3676470.59, d: -0.2694%, tcr: 8, cpr: 2.125, div: 1
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r: 3500000, a: 3496503.50, d: -0.0999%, tcr: 13, cpr: 1.375, div: 1
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r: 3000000, a: 2976190.48, d: -0.7937%, tcr: 14, cpr: 1.500, div: 1
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r: 2500000, a: 2500000.00, d: 0.0000%, tcr: 10, cpr: 2.500, div: 1
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r: 2000000, a: 2000000.00, d: 0.0000%, tcr: 10, cpr: 3.125, div: 1
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r: 1843200, a: 1838235.29, d: -0.2694%, tcr: 16, cpr: 2.125, div: 1
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r: 1500000, a: 1492537.31, d: -0.4975%, tcr: 5, cpr: 8.375, div: 1
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r: 1152000, a: 1152073.73, d: 0.0064%, tcr: 14, cpr: 3.875, div: 1
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r: 921600, a: 919117.65, d: -0.2694%, tcr: 16, cpr: 2.125, div: 2
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r: 576000, a: 576036.87, d: 0.0064%, tcr: 14, cpr: 3.875, div: 2
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r: 460800, a: 460829.49, d: 0.0064%, tcr: 7, cpr: 3.875, div: 5
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r: 230400, a: 230414.75, d: 0.0064%, tcr: 14, cpr: 3.875, div: 5
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r: 115200, a: 115207.37, d: 0.0064%, tcr: 14, cpr: 1.250, div: 31
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r: 57600, a: 57603.69, d: 0.0064%, tcr: 8, cpr: 3.875, div: 35
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r: 38400, a: 38402.46, d: 0.0064%, tcr: 14, cpr: 3.875, div: 30
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r: 19200, a: 19201.23, d: 0.0064%, tcr: 8, cpr: 3.875, div: 105
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r: 9600, a: 9600.06, d: 0.0006%, tcr: 9, cpr: 1.125, div: 643
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r: 4800, a: 4799.98, d: -0.0004%, tcr: 7, cpr: 2.875, div: 647
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r: 2400, a: 2400.02, d: 0.0008%, tcr: 9, cpr: 2.250, div: 1286
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r: 1200, a: 1200.00, d: 0.0000%, tcr: 14, cpr: 2.875, div: 1294
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r: 300, a: 300.00, d: 0.0000%, tcr: 11, cpr: 2.625, div: 7215
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r: 200, a: 200.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 15625
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r: 150, a: 150.00, d: 0.0000%, tcr: 13, cpr: 2.250, div: 14245
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r: 134, a: 134.00, d: 0.0000%, tcr: 11, cpr: 2.625, div: 16153
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r: 110, a: 110.00, d: 0.0000%, tcr: 12, cpr: 1.000, div: 47348
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r: 75, a: 75.00, d: 0.0000%, tcr: 4, cpr: 5.875, div: 35461
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r: 50, a: 50.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 62500
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r: 25, a: 25.00, d: 0.0000%, tcr: 16, cpr: 2.500, div: 62500
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r: 4, a: 4.00, d: 0.0000%, tcr: 16, cpr: 20.000, div: 48828
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r: 2, a: 2.00, d: 0.0000%, tcr: 16, cpr: 40.000, div: 48828
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r: 1, a: 1.00, d: 0.0000%, tcr: 16, cpr: 63.875, div: 61154
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::
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r: 15625000, a: 15625000.00, d: 0.0000%, tcr: 4, cpr: 1.000, div: 1
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r: 12500000, a: 12500000.00, d: 0.0000%, tcr: 5, cpr: 1.000, div: 1
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r: 10416666, a: 10416666.67, d: 0.0000%, tcr: 6, cpr: 1.000, div: 1
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r: 8928571, a: 8928571.43, d: 0.0000%, tcr: 7, cpr: 1.000, div: 1
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r: 7812500, a: 7812500.00, d: 0.0000%, tcr: 8, cpr: 1.000, div: 1
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r: 4000000, a: 4000000.00, d: 0.0000%, tcr: 5, cpr: 3.125, div: 1
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r: 3686400, a: 3676470.59, d: -0.2694%, tcr: 8, cpr: 2.125, div: 1
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r: 3500000, a: 3496503.50, d: -0.0999%, tcr: 13, cpr: 1.375, div: 1
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r: 3000000, a: 2976190.48, d: -0.7937%, tcr: 14, cpr: 1.500, div: 1
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r: 2500000, a: 2500000.00, d: 0.0000%, tcr: 10, cpr: 2.500, div: 1
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r: 2000000, a: 2000000.00, d: 0.0000%, tcr: 10, cpr: 3.125, div: 1
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r: 1843200, a: 1838235.29, d: -0.2694%, tcr: 16, cpr: 2.125, div: 1
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r: 1500000, a: 1492537.31, d: -0.4975%, tcr: 5, cpr: 8.375, div: 1
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r: 1152000, a: 1152073.73, d: 0.0064%, tcr: 14, cpr: 3.875, div: 1
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r: 921600, a: 919117.65, d: -0.2694%, tcr: 16, cpr: 2.125, div: 2
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r: 576000, a: 576036.87, d: 0.0064%, tcr: 14, cpr: 3.875, div: 2
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r: 460800, a: 460829.49, d: 0.0064%, tcr: 7, cpr: 3.875, div: 5
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r: 230400, a: 230414.75, d: 0.0064%, tcr: 14, cpr: 3.875, div: 5
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r: 115200, a: 115207.37, d: 0.0064%, tcr: 14, cpr: 1.250, div: 31
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r: 57600, a: 57603.69, d: 0.0064%, tcr: 8, cpr: 3.875, div: 35
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r: 38400, a: 38402.46, d: 0.0064%, tcr: 14, cpr: 3.875, div: 30
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r: 19200, a: 19201.23, d: 0.0064%, tcr: 8, cpr: 3.875, div: 105
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r: 9600, a: 9600.06, d: 0.0006%, tcr: 9, cpr: 1.125, div: 643
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r: 4800, a: 4799.98, d: -0.0004%, tcr: 7, cpr: 2.875, div: 647
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r: 2400, a: 2400.02, d: 0.0008%, tcr: 9, cpr: 2.250, div: 1286
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r: 1200, a: 1200.00, d: 0.0000%, tcr: 14, cpr: 2.875, div: 1294
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r: 300, a: 300.00, d: 0.0000%, tcr: 11, cpr: 2.625, div: 7215
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r: 200, a: 200.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 15625
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r: 150, a: 150.00, d: 0.0000%, tcr: 13, cpr: 2.250, div: 14245
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r: 134, a: 134.00, d: 0.0000%, tcr: 11, cpr: 2.625, div: 16153
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r: 110, a: 110.00, d: 0.0000%, tcr: 12, cpr: 1.000, div: 47348
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r: 75, a: 75.00, d: 0.0000%, tcr: 4, cpr: 5.875, div: 35461
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r: 50, a: 50.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 62500
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r: 25, a: 25.00, d: 0.0000%, tcr: 16, cpr: 2.500, div: 62500
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r: 4, a: 4.00, d: 0.0000%, tcr: 16, cpr: 20.000, div: 48828
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r: 2, a: 2.00, d: 0.0000%, tcr: 16, cpr: 40.000, div: 48828
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r: 1, a: 1.00, d: 0.0000%, tcr: 16, cpr: 63.875, div: 61154
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With the baud base set to 15625000 and the unsigned 16-bit UART_DIV_MAX
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limitation imposed by `serial8250_get_baud_rate' standard baud rates
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limitation imposed by ``serial8250_get_baud_rate`` standard baud rates
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below 300bps become unavailable in the regular way, e.g. the rate of
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200bps requires the baud base to be divided by 78125 and that is beyond
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the unsigned 16-bit range. The historic spd_cust feature can still be
···
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and the clock divisor (DLM/DLL) as follows to obtain such rates if so
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required:
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31 29 28 20 19 16 15 0
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+-----+-----------------+-------+-------------------------------+
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|0 0 0| CPR2:CPR | TCR | DLM:DLL |
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+-----+-----------------+-------+-------------------------------+
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::
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Use a value such encoded for the `custom_divisor' field along with the
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ASYNC_SPD_CUST flag set in the `flags' field in `struct serial_struct'
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31 29 28 20 19 16 15 0
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+-----+-----------------+-------+-------------------------------+
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|0 0 0| CPR2:CPR | TCR | DLM:DLL |
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+-----+-----------------+-------+-------------------------------+
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Use a value such encoded for the ``custom_divisor`` field along with the
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ASYNC_SPD_CUST flag set in the ``flags`` field in ``struct serial_struct``
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passed with the TIOCSSERIAL ioctl(2), such as with the setserial(8)
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utility and its `divisor' and `spd_cust' parameters, and the select
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utility and its ``divisor`` and ``spd_cust`` parameters, and then select
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the baud rate of 38400bps. Note that the value of 0 in TCR sets the
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oversampling rate to 16 and prescaler values below 1 in CPR2/CPR are
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clamped by the driver to 1.
···
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respectively. These parameters will set the baud rate for the serial
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port to 62500000 / 62.500 / 1250 / 16 = 50bps.
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References:
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[1] "OXPCIe200 PCI Express Multi-Port Bridge", Oxford Semiconductor,
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Inc., DS-0045, 10 Nov 2008, Section "950 Mode", pp. 64-65
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[2] "OXPCIe952 PCI Express Bridge to Dual Serial & Parallel Port",
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Oxford Semiconductor, Inc., DS-0046, Mar 06 08, Section "950 Mode",
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p. 20
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[3] "OXPCIe954 PCI Express Bridge to Quad Serial Port", Oxford
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Semiconductor, Inc., DS-0047, Feb 08, Section "950 Mode", p. 20
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[4] "OXPCIe958 PCI Express Bridge to Octal Serial Port", Oxford
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Semiconductor, Inc., DS-0048, Feb 08, Section "950 Mode", p. 20
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Maciej W. Rozycki <macro@orcam.me.uk>
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.. [OX200] "OXPCIe200 PCI Express Multi-Port Bridge", Oxford Semiconductor,
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Inc., DS-0045, 10 Nov 2008, Section "950 Mode", pp. 64-65
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.. [OX952] "OXPCIe952 PCI Express Bridge to Dual Serial & Parallel Port",
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Oxford Semiconductor, Inc., DS-0046, Mar 06 08, Section "950 Mode",
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p. 20
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.. [OX954] "OXPCIe954 PCI Express Bridge to Quad Serial Port", Oxford
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Semiconductor, Inc., DS-0047, Feb 08, Section "950 Mode", p. 20
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.. [OX958] "OXPCIe958 PCI Express Bridge to Octal Serial Port", Oxford
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Semiconductor, Inc., DS-0048, Feb 08, Section "950 Mode", p. 20