tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: starfive: Add JH7100 clock generator driver
Add a driver for the StarFive JH7100 clock generator.
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
authored by
Geert Uytterhoeven
and committed by
Emil Renner Berthing
4210be66
af35098f
+710
+7
MAINTAINERS
+7
MAINTAINERS
···
18130
18130
S: Odd Fixes
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18131
F: drivers/net/ethernet/adaptec/starfire*
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STARFIVE JH7100 CLOCK DRIVER
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M: Emil Renner Berthing <kernel@esmil.dk>
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S: Maintained
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F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
18137
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F: drivers/clk/starfive/clk-starfive-jh7100.c
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F: include/dt-bindings/clock/starfive-jh7100.h
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+
18133
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STATIC BRANCH/CALL
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M: Peter Zijlstra <peterz@infradead.org>
18135
18142
M: Josh Poimboeuf <jpoimboe@redhat.com>
+1
drivers/clk/Kconfig
+1
drivers/clk/Kconfig
···
412
412
source "drivers/clk/sifive/Kconfig"
413
413
source "drivers/clk/socfpga/Kconfig"
414
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source "drivers/clk/sprd/Kconfig"
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+
source "drivers/clk/starfive/Kconfig"
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source "drivers/clk/sunxi/Kconfig"
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source "drivers/clk/sunxi-ng/Kconfig"
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source "drivers/clk/tegra/Kconfig"
+1
drivers/clk/Makefile
+1
drivers/clk/Makefile
+9
drivers/clk/starfive/Kconfig
+9
drivers/clk/starfive/Kconfig
+3
drivers/clk/starfive/Makefile
+3
drivers/clk/starfive/Makefile
+689
drivers/clk/starfive/clk-starfive-jh7100.c
+689
drivers/clk/starfive/clk-starfive-jh7100.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
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/*
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* StarFive JH7100 Clock Generator Driver
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*
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* Copyright 2021 Ahmad Fatoum, Pengutronix
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* Copyright (C) 2021 Glider bv
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* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
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*/
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#include <linux/bits.h>
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#include <linux/clk-provider.h>
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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+
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#include <dt-bindings/clock/starfive-jh7100.h>
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+
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/* external clocks */
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#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
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#define JH7100_CLK_OSC_AUD (JH7100_CLK_END + 1)
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#define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2)
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#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
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+
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/* register fields */
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#define JH7100_CLK_ENABLE BIT(31)
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#define JH7100_CLK_INVERT BIT(30)
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#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
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#define JH7100_CLK_MUX_SHIFT 24
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#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
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+
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/* clock data */
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#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
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.name = _name, \
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.flags = CLK_SET_RATE_PARENT | (_flags), \
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.max = JH7100_CLK_ENABLE, \
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.parents = { [0] = _parent }, \
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}
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#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
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.name = _name, \
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.flags = 0, \
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.max = _max, \
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.parents = { [0] = _parent }, \
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}
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#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
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.name = _name, \
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.flags = _flags, \
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.max = JH7100_CLK_ENABLE | (_max), \
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.parents = { [0] = _parent }, \
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}
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#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
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.name = _name, \
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.flags = 0, \
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.max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
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.parents = { __VA_ARGS__ }, \
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}
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+
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#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
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.name = _name, \
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.flags = _flags, \
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.max = JH7100_CLK_ENABLE | \
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(((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
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.parents = { __VA_ARGS__ }, \
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}
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#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
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.name = _name, \
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.flags = CLK_SET_RATE_PARENT, \
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.max = JH7100_CLK_INVERT, \
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.parents = { [0] = _parent }, \
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}
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static const struct {
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const char *name;
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unsigned long flags;
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u32 max;
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u8 parents[4];
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} jh7100_clk_data[] __initconst = {
86
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JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
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JH7100_CLK_OSC_SYS,
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JH7100_CLK_PLL0_OUT,
89
+
JH7100_CLK_PLL1_OUT,
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JH7100_CLK_PLL2_OUT),
91
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JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
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JH7100_CLK_OSC_SYS,
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JH7100_CLK_PLL1_OUT,
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JH7100_CLK_PLL2_OUT),
95
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JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
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JH7100_CLK_OSC_SYS,
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JH7100_CLK_PLL0_OUT,
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JH7100_CLK_PLL1_OUT,
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JH7100_CLK_PLL2_OUT),
100
+
JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
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+
JH7100_CLK_OSC_SYS,
102
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JH7100_CLK_PLL0_OUT,
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JH7100_CLK_PLL2_OUT),
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JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
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JH7100_CLK_OSC_SYS,
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JH7100_CLK_PLL0_OUT),
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JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
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JH7100_CLK_OSC_SYS,
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JH7100_CLK_PLL2_OUT),
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JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
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JH7100_CLK_OSC_SYS,
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JH7100_CLK_PLL1_OUT,
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JH7100_CLK_PLL2_OUT),
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JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
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JH7100_CLK_OSC_AUD,
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JH7100_CLK_PLL0_OUT,
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JH7100_CLK_PLL2_OUT),
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JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
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JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
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JH7100_CLK_OSC_SYS,
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JH7100_CLK_PLL1_OUT,
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JH7100_CLK_PLL2_OUT),
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JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
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JH7100_CLK_OSC_SYS,
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JH7100_CLK_PLL0_OUT,
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JH7100_CLK_PLL1_OUT),
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JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
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JH7100_CLK_OSC_AUD,
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JH7100_CLK_PLL0_OUT,
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JH7100_CLK_PLL2_OUT),
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JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
132
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JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
133
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JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
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JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
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JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
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JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
137
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JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
138
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JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
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JH7100_CLK_OSC_SYS,
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JH7100_CLK_OSC_AUD),
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JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
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JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
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JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
144
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JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
145
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JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
146
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JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
147
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JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
148
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JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
149
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JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
150
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JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
151
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JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
152
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JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
153
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JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
154
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JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
155
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JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
156
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JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
157
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JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
158
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JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
159
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JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
160
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JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
161
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JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
162
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JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
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JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
164
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JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
165
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JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
166
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JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
167
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JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
168
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JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
169
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JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
170
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JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
171
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JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
172
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JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
173
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JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
174
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JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
175
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JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
176
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JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
177
+
JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
178
+
JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
179
+
JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
180
+
JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
181
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JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
182
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JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
183
+
JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
184
+
JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2),
185
+
JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4),
186
+
JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
187
+
JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
188
+
JH7100_CLK_DDROSC_DIV2,
189
+
JH7100_CLK_DDRPLL_DIV2,
190
+
JH7100_CLK_DDRPLL_DIV4,
191
+
JH7100_CLK_DDRPLL_DIV8),
192
+
JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
193
+
JH7100_CLK_DDROSC_DIV2,
194
+
JH7100_CLK_DDRPLL_DIV2,
195
+
JH7100_CLK_DDRPLL_DIV4,
196
+
JH7100_CLK_DDRPLL_DIV8),
197
+
JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
198
+
JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
199
+
JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
200
+
JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
201
+
JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
202
+
JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
203
+
JH7100_CLK_CPU_AXI,
204
+
JH7100_CLK_NNEBUS_SRC1),
205
+
JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
206
+
JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
207
+
JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
208
+
JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
209
+
JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
210
+
JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
211
+
JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
212
+
JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
213
+
JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
214
+
JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
215
+
JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
216
+
JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
217
+
JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
218
+
JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
219
+
JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
220
+
JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
221
+
JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
222
+
JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
223
+
JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
224
+
JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
225
+
JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
226
+
JH7100_CLK_OSC_SYS,
227
+
JH7100_CLK_USBPHY_PLLDIV25M),
228
+
JH7100__DIV(JH7100_CLK_AUDIO_DIV, "audio_div", 131072, JH7100_CLK_AUDIO_ROOT),
229
+
JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
230
+
JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
231
+
JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
232
+
JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
233
+
JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
234
+
JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
235
+
JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
236
+
JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
237
+
JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
238
+
JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
239
+
JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
240
+
JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
241
+
JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
242
+
JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
243
+
JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
244
+
JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
245
+
JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
246
+
JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
247
+
JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
248
+
JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
249
+
JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
250
+
JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
251
+
JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
252
+
JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
253
+
JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
254
+
JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
255
+
JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
256
+
JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
257
+
JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
258
+
JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
259
+
JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
260
+
JH7100_CLK_GMAC_GTX,
261
+
JH7100_CLK_GMAC_TX_INV,
262
+
JH7100_CLK_GMAC_RMII_TX),
263
+
JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
264
+
JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
265
+
JH7100_CLK_GMAC_GR_MII_RX,
266
+
JH7100_CLK_GMAC_RMII_RX),
267
+
JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
268
+
JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
269
+
JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
270
+
JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
271
+
JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
272
+
JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
273
+
JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
274
+
JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
275
+
JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
276
+
JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
277
+
JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
278
+
JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
279
+
JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
280
+
JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
281
+
JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
282
+
JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
283
+
JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
284
+
JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
285
+
JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
286
+
JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
287
+
JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
288
+
JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
289
+
JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
290
+
JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
291
+
JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
292
+
JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
293
+
JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
294
+
JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
295
+
JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
296
+
JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
297
+
JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
298
+
JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
299
+
JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
300
+
JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
301
+
JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
302
+
JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
303
+
JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
304
+
JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
305
+
JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
306
+
JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
307
+
JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
308
+
JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
309
+
JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
310
+
JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
311
+
JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
312
+
JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
313
+
JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
314
+
JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
315
+
JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
316
+
JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
317
+
JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
318
+
JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
319
+
JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
320
+
JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
321
+
JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
322
+
JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
323
+
JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
324
+
};
325
+
326
+
struct jh7100_clk {
327
+
struct clk_hw hw;
328
+
unsigned int idx;
329
+
unsigned int max_div;
330
+
};
331
+
332
+
struct jh7100_clk_priv {
333
+
/* protect clk enable and set rate/parent from happening at the same time */
334
+
spinlock_t rmw_lock;
335
+
struct device *dev;
336
+
void __iomem *base;
337
+
struct clk_hw *pll[3];
338
+
struct jh7100_clk reg[JH7100_CLK_PLL0_OUT];
339
+
};
340
+
341
+
static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
342
+
{
343
+
return container_of(hw, struct jh7100_clk, hw);
344
+
}
345
+
346
+
static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
347
+
{
348
+
return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
349
+
}
350
+
351
+
static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
352
+
{
353
+
struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
354
+
void __iomem *reg = priv->base + 4 * clk->idx;
355
+
356
+
return readl_relaxed(reg);
357
+
}
358
+
359
+
static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
360
+
{
361
+
struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
362
+
void __iomem *reg = priv->base + 4 * clk->idx;
363
+
unsigned long flags;
364
+
365
+
spin_lock_irqsave(&priv->rmw_lock, flags);
366
+
value |= readl_relaxed(reg) & ~mask;
367
+
writel_relaxed(value, reg);
368
+
spin_unlock_irqrestore(&priv->rmw_lock, flags);
369
+
}
370
+
371
+
static int jh7100_clk_enable(struct clk_hw *hw)
372
+
{
373
+
struct jh7100_clk *clk = jh7100_clk_from(hw);
374
+
375
+
jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
376
+
return 0;
377
+
}
378
+
379
+
static void jh7100_clk_disable(struct clk_hw *hw)
380
+
{
381
+
struct jh7100_clk *clk = jh7100_clk_from(hw);
382
+
383
+
jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
384
+
}
385
+
386
+
static int jh7100_clk_is_enabled(struct clk_hw *hw)
387
+
{
388
+
struct jh7100_clk *clk = jh7100_clk_from(hw);
389
+
390
+
return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
391
+
}
392
+
393
+
static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
394
+
unsigned long parent_rate)
395
+
{
396
+
struct jh7100_clk *clk = jh7100_clk_from(hw);
397
+
u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
398
+
399
+
return div ? parent_rate / div : 0;
400
+
}
401
+
402
+
static unsigned long jh7100_clk_bestdiv(struct jh7100_clk *clk,
403
+
unsigned long rate, unsigned long parent)
404
+
{
405
+
unsigned long max = clk->max_div;
406
+
unsigned long div = DIV_ROUND_UP(parent, rate);
407
+
408
+
return min(div, max);
409
+
}
410
+
411
+
static int jh7100_clk_determine_rate(struct clk_hw *hw,
412
+
struct clk_rate_request *req)
413
+
{
414
+
struct jh7100_clk *clk = jh7100_clk_from(hw);
415
+
unsigned long parent = req->best_parent_rate;
416
+
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
417
+
unsigned long div = jh7100_clk_bestdiv(clk, rate, parent);
418
+
unsigned long result = parent / div;
419
+
420
+
/*
421
+
* we want the result clamped by min_rate and max_rate if possible:
422
+
* case 1: div hits the max divider value, which means it's less than
423
+
* parent / rate, so the result is greater than rate and min_rate in
424
+
* particular. we can't do anything about result > max_rate because the
425
+
* divider doesn't go any further.
426
+
* case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
427
+
* always lower or equal to rate and max_rate. however the result may
428
+
* turn out lower than min_rate, but then the next higher rate is fine:
429
+
* div - 1 = ceil(parent / rate) - 1 < parent / rate
430
+
* and thus
431
+
* min_rate <= rate < parent / (div - 1)
432
+
*/
433
+
if (result < req->min_rate && div > 1)
434
+
result = parent / (div - 1);
435
+
436
+
req->rate = result;
437
+
return 0;
438
+
}
439
+
440
+
static int jh7100_clk_set_rate(struct clk_hw *hw,
441
+
unsigned long rate,
442
+
unsigned long parent_rate)
443
+
{
444
+
struct jh7100_clk *clk = jh7100_clk_from(hw);
445
+
unsigned long div = jh7100_clk_bestdiv(clk, rate, parent_rate);
446
+
447
+
jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
448
+
return 0;
449
+
}
450
+
451
+
static u8 jh7100_clk_get_parent(struct clk_hw *hw)
452
+
{
453
+
struct jh7100_clk *clk = jh7100_clk_from(hw);
454
+
u32 value = jh7100_clk_reg_get(clk);
455
+
456
+
return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
457
+
}
458
+
459
+
static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
460
+
{
461
+
struct jh7100_clk *clk = jh7100_clk_from(hw);
462
+
u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
463
+
464
+
jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
465
+
return 0;
466
+
}
467
+
468
+
static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
469
+
struct clk_rate_request *req)
470
+
{
471
+
return clk_mux_determine_rate_flags(hw, req, 0);
472
+
}
473
+
474
+
static int jh7100_clk_get_phase(struct clk_hw *hw)
475
+
{
476
+
struct jh7100_clk *clk = jh7100_clk_from(hw);
477
+
u32 value = jh7100_clk_reg_get(clk);
478
+
479
+
return (value & JH7100_CLK_INVERT) ? 180 : 0;
480
+
}
481
+
482
+
static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
483
+
{
484
+
struct jh7100_clk *clk = jh7100_clk_from(hw);
485
+
u32 value;
486
+
487
+
if (degrees == 0)
488
+
value = 0;
489
+
else if (degrees == 180)
490
+
value = JH7100_CLK_INVERT;
491
+
else
492
+
return -EINVAL;
493
+
494
+
jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
495
+
return 0;
496
+
}
497
+
498
+
#ifdef CONFIG_DEBUG_FS
499
+
static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
500
+
{
501
+
static const struct debugfs_reg32 jh7100_clk_reg = {
502
+
.name = "CTRL",
503
+
.offset = 0,
504
+
};
505
+
struct jh7100_clk *clk = jh7100_clk_from(hw);
506
+
struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
507
+
struct debugfs_regset32 *regset;
508
+
509
+
regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
510
+
if (!regset)
511
+
return;
512
+
513
+
regset->regs = &jh7100_clk_reg;
514
+
regset->nregs = 1;
515
+
regset->base = priv->base + 4 * clk->idx;
516
+
517
+
debugfs_create_regset32("registers", 0400, dentry, regset);
518
+
}
519
+
#else
520
+
#define jh7100_clk_debug_init NULL
521
+
#endif
522
+
523
+
static const struct clk_ops jh7100_clk_gate_ops = {
524
+
.enable = jh7100_clk_enable,
525
+
.disable = jh7100_clk_disable,
526
+
.is_enabled = jh7100_clk_is_enabled,
527
+
.debug_init = jh7100_clk_debug_init,
528
+
};
529
+
530
+
static const struct clk_ops jh7100_clk_div_ops = {
531
+
.recalc_rate = jh7100_clk_recalc_rate,
532
+
.determine_rate = jh7100_clk_determine_rate,
533
+
.set_rate = jh7100_clk_set_rate,
534
+
.debug_init = jh7100_clk_debug_init,
535
+
};
536
+
537
+
static const struct clk_ops jh7100_clk_gdiv_ops = {
538
+
.enable = jh7100_clk_enable,
539
+
.disable = jh7100_clk_disable,
540
+
.is_enabled = jh7100_clk_is_enabled,
541
+
.recalc_rate = jh7100_clk_recalc_rate,
542
+
.determine_rate = jh7100_clk_determine_rate,
543
+
.set_rate = jh7100_clk_set_rate,
544
+
.debug_init = jh7100_clk_debug_init,
545
+
};
546
+
547
+
static const struct clk_ops jh7100_clk_mux_ops = {
548
+
.determine_rate = jh7100_clk_mux_determine_rate,
549
+
.set_parent = jh7100_clk_set_parent,
550
+
.get_parent = jh7100_clk_get_parent,
551
+
.debug_init = jh7100_clk_debug_init,
552
+
};
553
+
554
+
static const struct clk_ops jh7100_clk_gmux_ops = {
555
+
.enable = jh7100_clk_enable,
556
+
.disable = jh7100_clk_disable,
557
+
.is_enabled = jh7100_clk_is_enabled,
558
+
.determine_rate = jh7100_clk_mux_determine_rate,
559
+
.set_parent = jh7100_clk_set_parent,
560
+
.get_parent = jh7100_clk_get_parent,
561
+
.debug_init = jh7100_clk_debug_init,
562
+
};
563
+
564
+
static const struct clk_ops jh7100_clk_inv_ops = {
565
+
.get_phase = jh7100_clk_get_phase,
566
+
.set_phase = jh7100_clk_set_phase,
567
+
.debug_init = jh7100_clk_debug_init,
568
+
};
569
+
570
+
static const struct clk_ops *__init jh7100_clk_ops(u32 max)
571
+
{
572
+
if (max & JH7100_CLK_DIV_MASK) {
573
+
if (max & JH7100_CLK_ENABLE)
574
+
return &jh7100_clk_gdiv_ops;
575
+
return &jh7100_clk_div_ops;
576
+
}
577
+
578
+
if (max & JH7100_CLK_MUX_MASK) {
579
+
if (max & JH7100_CLK_ENABLE)
580
+
return &jh7100_clk_gmux_ops;
581
+
return &jh7100_clk_mux_ops;
582
+
}
583
+
584
+
if (max & JH7100_CLK_ENABLE)
585
+
return &jh7100_clk_gate_ops;
586
+
587
+
return &jh7100_clk_inv_ops;
588
+
}
589
+
590
+
static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
591
+
{
592
+
struct jh7100_clk_priv *priv = data;
593
+
unsigned int idx = clkspec->args[0];
594
+
595
+
if (idx < JH7100_CLK_PLL0_OUT)
596
+
return &priv->reg[idx].hw;
597
+
598
+
if (idx < JH7100_CLK_END)
599
+
return priv->pll[idx - JH7100_CLK_PLL0_OUT];
600
+
601
+
return ERR_PTR(-EINVAL);
602
+
}
603
+
604
+
static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
605
+
{
606
+
struct jh7100_clk_priv *priv;
607
+
unsigned int idx;
608
+
int ret;
609
+
610
+
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
611
+
if (!priv)
612
+
return -ENOMEM;
613
+
614
+
spin_lock_init(&priv->rmw_lock);
615
+
priv->dev = &pdev->dev;
616
+
priv->base = devm_platform_ioremap_resource(pdev, 0);
617
+
if (IS_ERR(priv->base))
618
+
return PTR_ERR(priv->base);
619
+
620
+
priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
621
+
"osc_sys", 0, 40, 1);
622
+
if (IS_ERR(priv->pll[0]))
623
+
return PTR_ERR(priv->pll[0]);
624
+
625
+
priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
626
+
"osc_sys", 0, 64, 1);
627
+
if (IS_ERR(priv->pll[1]))
628
+
return PTR_ERR(priv->pll[1]);
629
+
630
+
priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
631
+
"pll2_refclk", 0, 55, 1);
632
+
if (IS_ERR(priv->pll[2]))
633
+
return PTR_ERR(priv->pll[2]);
634
+
635
+
for (idx = 0; idx < JH7100_CLK_PLL0_OUT; idx++) {
636
+
u32 max = jh7100_clk_data[idx].max;
637
+
struct clk_parent_data parents[4] = {};
638
+
struct clk_init_data init = {
639
+
.name = jh7100_clk_data[idx].name,
640
+
.ops = jh7100_clk_ops(max),
641
+
.parent_data = parents,
642
+
.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
643
+
.flags = jh7100_clk_data[idx].flags,
644
+
};
645
+
struct jh7100_clk *clk = &priv->reg[idx];
646
+
unsigned int i;
647
+
648
+
for (i = 0; i < init.num_parents; i++) {
649
+
unsigned int pidx = jh7100_clk_data[idx].parents[i];
650
+
651
+
if (pidx < JH7100_CLK_PLL0_OUT)
652
+
parents[i].hw = &priv->reg[pidx].hw;
653
+
else if (pidx < JH7100_CLK_END)
654
+
parents[i].hw = priv->pll[pidx - JH7100_CLK_PLL0_OUT];
655
+
else if (pidx == JH7100_CLK_OSC_SYS)
656
+
parents[i].fw_name = "osc_sys";
657
+
else if (pidx == JH7100_CLK_OSC_AUD)
658
+
parents[i].fw_name = "osc_aud";
659
+
else if (pidx == JH7100_CLK_GMAC_RMII_REF)
660
+
parents[i].fw_name = "gmac_rmii_ref";
661
+
else if (pidx == JH7100_CLK_GMAC_GR_MII_RX)
662
+
parents[i].fw_name = "gmac_gr_mii_rxclk";
663
+
}
664
+
665
+
clk->hw.init = &init;
666
+
clk->idx = idx;
667
+
clk->max_div = max & JH7100_CLK_DIV_MASK;
668
+
669
+
ret = devm_clk_hw_register(priv->dev, &clk->hw);
670
+
if (ret)
671
+
return ret;
672
+
}
673
+
674
+
return devm_of_clk_add_hw_provider(priv->dev, jh7100_clk_get, priv);
675
+
}
676
+
677
+
static const struct of_device_id clk_starfive_jh7100_match[] = {
678
+
{ .compatible = "starfive,jh7100-clkgen" },
679
+
{ /* sentinel */ }
680
+
};
681
+
682
+
static struct platform_driver clk_starfive_jh7100_driver = {
683
+
.driver = {
684
+
.name = "clk-starfive-jh7100",
685
+
.of_match_table = clk_starfive_jh7100_match,
686
+
.suppress_bind_attrs = true,
687
+
},
688
+
};
689
+
builtin_platform_driver_probe(clk_starfive_jh7100_driver, clk_starfive_jh7100_probe);