···99#include <asm/memory.h>1010#include <asm/param.h> /* HZ */11111212+/*1313+ * Loop (or tick) based delay:1414+ *1515+ * loops = loops_per_jiffy * jiffies_per_sec * delay_us / us_per_sec1616+ *1717+ * where:1818+ *1919+ * jiffies_per_sec = HZ2020+ * us_per_sec = 10000002121+ *2222+ * Therefore the constant part is HZ / 1000000 which is a small2323+ * fractional number. To make this usable with integer math, we2424+ * scale up this constant by 2^31, perform the actual multiplication,2525+ * and scale the result back down by 2^31 with a simple shift:2626+ *2727+ * loops = (loops_per_jiffy * delay_us * UDELAY_MULT) >> 312828+ *2929+ * where:3030+ *3131+ * UDELAY_MULT = 2^31 * HZ / 10000003232+ * = (2^31 / 1000000) * HZ3333+ * = 2147.483648 * HZ3434+ * = 2147 * HZ + 483648 * HZ / 10000003535+ *3636+ * 31 is the biggest scale shift value that won't overflow 32 bits for3737+ * delay_us * UDELAY_MULT assuming HZ <= 1000 and delay_us <= 2000.3838+ */1239#define MAX_UDELAY_MS 21340#define UDELAY_MULT UL(2147 * HZ + 483648 * HZ / 1000000)1441#define UDELAY_SHIFT 31
+1-1
arch/arm/include/asm/unistd.h
···1919 * This may need to be greater than __NR_last_syscall+1 in order to2020 * account for the padding in the syscall table2121 */2222-#define __NR_syscalls (396)2222+#define __NR_syscalls (400)23232424#define __ARCH_WANT_STAT642525#define __ARCH_WANT_SYS_GETHOSTNAME
+3
arch/arm/include/uapi/asm/unistd.h
···420420#define __NR_copy_file_range (__NR_SYSCALL_BASE+391)421421#define __NR_preadv2 (__NR_SYSCALL_BASE+392)422422#define __NR_pwritev2 (__NR_SYSCALL_BASE+393)423423+#define __NR_pkey_mprotect (__NR_SYSCALL_BASE+394)424424+#define __NR_pkey_alloc (__NR_SYSCALL_BASE+395)425425+#define __NR_pkey_free (__NR_SYSCALL_BASE+396)423426424427/*425428 * The following SWIs are ARM private.
···1616#include <asm/opcodes-sec.h>1717#include <asm/opcodes-virt.h>1818#include <asm/unwind.h>1919-#include <asm/export.h>20192120 /*2221 * Wrap c macros in asm macros to delay expansion until after the···5152ENTRY(arm_smccc_smc)5253 SMCCC SMCCC_SMC5354ENDPROC(arm_smccc_smc)5454-EXPORT_SYMBOL(arm_smccc_smc)55555656/*5757 * void smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,···6062ENTRY(arm_smccc_hvc)6163 SMCCC SMCCC_HVC6264ENDPROC(arm_smccc_hvc)6363-EXPORT_SYMBOL(arm_smccc_hvc)
+219-1
arch/arm/kernel/topology.c
···1212 */13131414#include <linux/cpu.h>1515+#include <linux/cpufreq.h>1516#include <linux/cpumask.h>1617#include <linux/export.h>1718#include <linux/init.h>···2221#include <linux/of.h>2322#include <linux/sched.h>2423#include <linux/slab.h>2424+#include <linux/string.h>25252626+#include <asm/cpu.h>2627#include <asm/cputype.h>2728#include <asm/topology.h>2829···4441 * updated during this sequence.4542 */4643static DEFINE_PER_CPU(unsigned long, cpu_scale) = SCHED_CAPACITY_SCALE;4444+static DEFINE_MUTEX(cpu_scale_mutex);47454846unsigned long arch_scale_cpu_capacity(struct sched_domain *sd, int cpu)4947{···5551{5652 per_cpu(cpu_scale, cpu) = capacity;5753}5454+5555+#ifdef CONFIG_PROC_SYSCTL5656+static ssize_t cpu_capacity_show(struct device *dev,5757+ struct device_attribute *attr,5858+ char *buf)5959+{6060+ struct cpu *cpu = container_of(dev, struct cpu, dev);6161+6262+ return sprintf(buf, "%lu\n",6363+ arch_scale_cpu_capacity(NULL, cpu->dev.id));6464+}6565+6666+static ssize_t cpu_capacity_store(struct device *dev,6767+ struct device_attribute *attr,6868+ const char *buf,6969+ size_t count)7070+{7171+ struct cpu *cpu = container_of(dev, struct cpu, dev);7272+ int this_cpu = cpu->dev.id, i;7373+ unsigned long new_capacity;7474+ ssize_t ret;7575+7676+ if (count) {7777+ ret = kstrtoul(buf, 0, &new_capacity);7878+ if (ret)7979+ return ret;8080+ if (new_capacity > SCHED_CAPACITY_SCALE)8181+ return -EINVAL;8282+8383+ mutex_lock(&cpu_scale_mutex);8484+ for_each_cpu(i, &cpu_topology[this_cpu].core_sibling)8585+ set_capacity_scale(i, new_capacity);8686+ mutex_unlock(&cpu_scale_mutex);8787+ }8888+8989+ return count;9090+}9191+9292+static DEVICE_ATTR_RW(cpu_capacity);9393+9494+static int register_cpu_capacity_sysctl(void)9595+{9696+ int i;9797+ struct device *cpu;9898+9999+ for_each_possible_cpu(i) {100100+ cpu = get_cpu_device(i);101101+ if (!cpu) {102102+ pr_err("%s: too early to get CPU%d device!\n",103103+ __func__, i);104104+ continue;105105+ }106106+ device_create_file(cpu, &dev_attr_cpu_capacity);107107+ }108108+109109+ return 0;110110+}111111+subsys_initcall(register_cpu_capacity_sysctl);112112+#endif5811359114#ifdef CONFIG_OF60115struct cpu_efficiency {···14178#define cpu_capacity(cpu) __cpu_capacity[cpu]1427914380static unsigned long middle_capacity = 1;8181+static bool cap_from_dt = true;8282+static u32 *raw_capacity;8383+static bool cap_parsing_failed;8484+static u32 capacity_scale;8585+8686+static int __init parse_cpu_capacity(struct device_node *cpu_node, int cpu)8787+{8888+ int ret = 1;8989+ u32 cpu_capacity;9090+9191+ if (cap_parsing_failed)9292+ return !ret;9393+9494+ ret = of_property_read_u32(cpu_node,9595+ "capacity-dmips-mhz",9696+ &cpu_capacity);9797+ if (!ret) {9898+ if (!raw_capacity) {9999+ raw_capacity = kcalloc(num_possible_cpus(),100100+ sizeof(*raw_capacity),101101+ GFP_KERNEL);102102+ if (!raw_capacity) {103103+ pr_err("cpu_capacity: failed to allocate memory for raw capacities\n");104104+ cap_parsing_failed = true;105105+ return !ret;106106+ }107107+ }108108+ capacity_scale = max(cpu_capacity, capacity_scale);109109+ raw_capacity[cpu] = cpu_capacity;110110+ pr_debug("cpu_capacity: %s cpu_capacity=%u (raw)\n",111111+ cpu_node->full_name, raw_capacity[cpu]);112112+ } else {113113+ if (raw_capacity) {114114+ pr_err("cpu_capacity: missing %s raw capacity\n",115115+ cpu_node->full_name);116116+ pr_err("cpu_capacity: partial information: fallback to 1024 for all CPUs\n");117117+ }118118+ cap_parsing_failed = true;119119+ kfree(raw_capacity);120120+ }121121+122122+ return !ret;123123+}124124+125125+static void normalize_cpu_capacity(void)126126+{127127+ u64 capacity;128128+ int cpu;129129+130130+ if (!raw_capacity || cap_parsing_failed)131131+ return;132132+133133+ pr_debug("cpu_capacity: capacity_scale=%u\n", capacity_scale);134134+ mutex_lock(&cpu_scale_mutex);135135+ for_each_possible_cpu(cpu) {136136+ capacity = (raw_capacity[cpu] << SCHED_CAPACITY_SHIFT)137137+ / capacity_scale;138138+ set_capacity_scale(cpu, capacity);139139+ pr_debug("cpu_capacity: CPU%d cpu_capacity=%lu\n",140140+ cpu, arch_scale_cpu_capacity(NULL, cpu));141141+ }142142+ mutex_unlock(&cpu_scale_mutex);143143+}144144+145145+#ifdef CONFIG_CPU_FREQ146146+static cpumask_var_t cpus_to_visit;147147+static bool cap_parsing_done;148148+static void parsing_done_workfn(struct work_struct *work);149149+static DECLARE_WORK(parsing_done_work, parsing_done_workfn);150150+151151+static int152152+init_cpu_capacity_callback(struct notifier_block *nb,153153+ unsigned long val,154154+ void *data)155155+{156156+ struct cpufreq_policy *policy = data;157157+ int cpu;158158+159159+ if (cap_parsing_failed || cap_parsing_done)160160+ return 0;161161+162162+ switch (val) {163163+ case CPUFREQ_NOTIFY:164164+ pr_debug("cpu_capacity: init cpu capacity for CPUs [%*pbl] (to_visit=%*pbl)\n",165165+ cpumask_pr_args(policy->related_cpus),166166+ cpumask_pr_args(cpus_to_visit));167167+ cpumask_andnot(cpus_to_visit,168168+ cpus_to_visit,169169+ policy->related_cpus);170170+ for_each_cpu(cpu, policy->related_cpus) {171171+ raw_capacity[cpu] = arch_scale_cpu_capacity(NULL, cpu) *172172+ policy->cpuinfo.max_freq / 1000UL;173173+ capacity_scale = max(raw_capacity[cpu], capacity_scale);174174+ }175175+ if (cpumask_empty(cpus_to_visit)) {176176+ normalize_cpu_capacity();177177+ kfree(raw_capacity);178178+ pr_debug("cpu_capacity: parsing done\n");179179+ cap_parsing_done = true;180180+ schedule_work(&parsing_done_work);181181+ }182182+ }183183+ return 0;184184+}185185+186186+static struct notifier_block init_cpu_capacity_notifier = {187187+ .notifier_call = init_cpu_capacity_callback,188188+};189189+190190+static int __init register_cpufreq_notifier(void)191191+{192192+ if (cap_parsing_failed)193193+ return -EINVAL;194194+195195+ if (!alloc_cpumask_var(&cpus_to_visit, GFP_KERNEL)) {196196+ pr_err("cpu_capacity: failed to allocate memory for cpus_to_visit\n");197197+ return -ENOMEM;198198+ }199199+ cpumask_copy(cpus_to_visit, cpu_possible_mask);200200+201201+ return cpufreq_register_notifier(&init_cpu_capacity_notifier,202202+ CPUFREQ_POLICY_NOTIFIER);203203+}204204+core_initcall(register_cpufreq_notifier);205205+206206+static void parsing_done_workfn(struct work_struct *work)207207+{208208+ cpufreq_unregister_notifier(&init_cpu_capacity_notifier,209209+ CPUFREQ_POLICY_NOTIFIER);210210+}211211+212212+#else213213+static int __init free_raw_capacity(void)214214+{215215+ kfree(raw_capacity);216216+217217+ return 0;218218+}219219+core_initcall(free_raw_capacity);220220+#endif144221145222/*146223 * Iterate all CPUs' descriptor in DT and compute the efficiency···30299 __cpu_capacity = kcalloc(nr_cpu_ids, sizeof(*__cpu_capacity),303100 GFP_NOWAIT);304101102102+ cn = of_find_node_by_path("/cpus");103103+ if (!cn) {104104+ pr_err("No CPU information found in DT\n");105105+ return;106106+ }107107+305108 for_each_possible_cpu(cpu) {306109 const u32 *rate;307110 int len;···318109 pr_err("missing device node for CPU %d\n", cpu);319110 continue;320111 }112112+113113+ if (parse_cpu_capacity(cn, cpu)) {114114+ of_node_put(cn);115115+ continue;116116+ }117117+118118+ cap_from_dt = false;321119322120 for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++)323121 if (of_device_is_compatible(cn, cpu_eff->compatible))···367151 middle_capacity = ((max_capacity / 3)368152 >> (SCHED_CAPACITY_SHIFT-1)) + 1;369153154154+ if (cap_from_dt && !cap_parsing_failed)155155+ normalize_cpu_capacity();370156}371157372158/*···378160 */379161static void update_cpu_capacity(unsigned int cpu)380162{381381- if (!cpu_capacity(cpu))163163+ if (!cpu_capacity(cpu) || cap_from_dt)382164 return;383165384166 set_capacity_scale(cpu, cpu_capacity(cpu) / middle_capacity);
+20
arch/arm/kernel/traps.c
···7474 dump_mem("", "Exception stack", frame + 4, frame + 4 + sizeof(struct pt_regs));7575}76767777+void dump_backtrace_stm(u32 *stack, u32 instruction)7878+{7979+ char str[80], *p;8080+ unsigned int x;8181+ int reg;8282+8383+ for (reg = 10, x = 0, p = str; reg >= 0; reg--) {8484+ if (instruction & BIT(reg)) {8585+ p += sprintf(p, " r%d:%08x", reg, *stack--);8686+ if (++x == 6) {8787+ x = 0;8888+ p = str;8989+ printk("%s\n", str);9090+ }9191+ }9292+ }9393+ if (p != str)9494+ printk("%s\n", str);9595+}9696+7797#ifndef CONFIG_ARM_UNWIND7898/*7999 * Stack pointers should always be within the kernels view of
+5
arch/arm/kernel/vmlinux-xip.lds.S
···33 * Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>44 */5566+/* No __ro_after_init data in the .rodata section - which will always be ro */77+#define RO_AFTER_INIT_DATA88+69#include <asm-generic/vmlinux.lds.h>710#include <asm/cache.h>811#include <asm/thread_info.h>···225222 ARM_EXIT_KEEP(EXIT_DATA)226223 . = ALIGN(PAGE_SIZE);227224 __init_end = .;225225+226226+ *(.data..ro_after_init)228227229228 NOSAVE_DATA230229 CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
-3
arch/arm/lib/ashldi3.S
···28282929#include <linux/linkage.h>3030#include <asm/assembler.h>3131-#include <asm/export.h>32313332#ifdef __ARMEB__3433#define al r1···52535354ENDPROC(__ashldi3)5455ENDPROC(__aeabi_llsl)5555-EXPORT_SYMBOL(__ashldi3)5656-EXPORT_SYMBOL(__aeabi_llsl)
-3
arch/arm/lib/ashrdi3.S
···28282929#include <linux/linkage.h>3030#include <asm/assembler.h>3131-#include <asm/export.h>32313332#ifdef __ARMEB__3433#define al r1···52535354ENDPROC(__ashrdi3)5455ENDPROC(__aeabi_lasr)5555-EXPORT_SYMBOL(__ashrdi3)5656-EXPORT_SYMBOL(__aeabi_lasr)
···88 * published by the Free Software Foundation.99 */1010#include <asm/assembler.h>1111-#include <asm/export.h>12111312/*1413 * unsigned int···331332 mov r5, r4, get_byte_1332333 b .Lexit333334FN_EXIT334334-FN_EXPORT
···1515 */1616#include <linux/linkage.h>1717#include <asm/assembler.h>1818-#include <asm/export.h>1918 .text20192120/*···37383: mov r0, r1 @ no free bits3839 ret lr3940ENDPROC(_find_first_zero_bit_le)4040-EXPORT_SYMBOL(_find_first_zero_bit_le)41414242/*4343 * Purpose : Find next 'zero' bit···5759 add r2, r2, #1 @ align bit pointer5860 b 2b @ loop for next bit5961ENDPROC(_find_next_zero_bit_le)6060-EXPORT_SYMBOL(_find_next_zero_bit_le)61626263/*6364 * Purpose : Find a 'one' bit···78813: mov r0, r1 @ no free bits7982 ret lr8083ENDPROC(_find_first_bit_le)8181-EXPORT_SYMBOL(_find_first_bit_le)82848385/*8486 * Purpose : Find next 'one' bit···97101 add r2, r2, #1 @ align bit pointer98102 b 2b @ loop for next bit99103ENDPROC(_find_next_bit_le)100100-EXPORT_SYMBOL(_find_next_bit_le)101104102105#ifdef __ARMEB__103106···1161213: mov r0, r1 @ no free bits117122 ret lr118123ENDPROC(_find_first_zero_bit_be)119119-EXPORT_SYMBOL(_find_first_zero_bit_be)120124121125ENTRY(_find_next_zero_bit_be)122126 teq r1, #0···133139 add r2, r2, #1 @ align bit pointer134140 b 2b @ loop for next bit135141ENDPROC(_find_next_zero_bit_be)136136-EXPORT_SYMBOL(_find_next_zero_bit_be)137142138143ENTRY(_find_first_bit_be)139144 teq r1, #0···1501573: mov r0, r1 @ no free bits151158 ret lr152159ENDPROC(_find_first_bit_be)153153-EXPORT_SYMBOL(_find_first_bit_be)154160155161ENTRY(_find_next_bit_be)156162 teq r1, #0···166174 add r2, r2, #1 @ align bit pointer167175 b 2b @ loop for next bit168176ENDPROC(_find_next_bit_be)169169-EXPORT_SYMBOL(_find_next_bit_be)170177171178#endif172179
···99 */1010#include <linux/linkage.h>1111#include <asm/assembler.h>1212-#include <asm/export.h>13121413ENTRY(__raw_readsl)1514 teq r2, #0 @ do we have to check for the zero len?···7778 strb r3, [r1, #0]7879 ret lr7980ENDPROC(__raw_readsl)8080-EXPORT_SYMBOL(__raw_readsl)
···99 */1010#include <linux/linkage.h>1111#include <asm/assembler.h>1212-#include <asm/export.h>13121413ENTRY(__raw_writesl)1514 teq r2, #0 @ do we have to check for the zero len?···6566 bne 6b6667 ret lr6768ENDPROC(__raw_writesl)6868-EXPORT_SYMBOL(__raw_writesl)
···12121313#include <linux/linkage.h>1414#include <asm/assembler.h>1515-#include <asm/export.h>16151716#ifdef __ARMEB__1817#define xh r0···3536 ret lr36373738ENDPROC(__ucmpdi2)3838-EXPORT_SYMBOL(__ucmpdi2)39394040#ifdef CONFIG_AEABI4141···4850 ret lr49515052ENDPROC(__aeabi_ulcmp)5151-EXPORT_SYMBOL(__aeabi_ulcmp)52535354#endif5455
+1
arch/arm/mach-imx/Makefile
···32323333ifdef CONFIG_SND_IMX_SOC3434obj-y += ssi-fiq.o3535+obj-y += ssi-fiq-ksym.o3536endif36373738# i.MX21 based machines
+20
arch/arm/mach-imx/ssi-fiq-ksym.c
···11+/*22+ * Exported ksyms for the SSI FIQ handler33+ *44+ * Copyright (C) 2009, Sascha Hauer <s.hauer@pengutronix.de>55+ *66+ * This program is free software; you can redistribute it and/or modify77+ * it under the terms of the GNU General Public License version 2 as88+ * published by the Free Software Foundation.99+ */1010+1111+#include <linux/module.h>1212+1313+#include <linux/platform_data/asoc-imx-ssi.h>1414+1515+EXPORT_SYMBOL(imx_ssi_fiq_tx_buffer);1616+EXPORT_SYMBOL(imx_ssi_fiq_rx_buffer);1717+EXPORT_SYMBOL(imx_ssi_fiq_start);1818+EXPORT_SYMBOL(imx_ssi_fiq_end);1919+EXPORT_SYMBOL(imx_ssi_fiq_base);2020+
+1-6
arch/arm/mach-imx/ssi-fiq.S
···8899#include <linux/linkage.h>1010#include <asm/assembler.h>1111-#include <asm/export.h>12111312/*1413 * r8 = bit 0-15: tx offset, bit 16-31: tx buffer size···144145 .word 0x0145146.L_imx_ssi_fiq_end:146147imx_ssi_fiq_end:147147-EXPORT_SYMBOL(imx_ssi_fiq_tx_buffer)148148-EXPORT_SYMBOL(imx_ssi_fiq_rx_buffer)149149-EXPORT_SYMBOL(imx_ssi_fiq_start)150150-EXPORT_SYMBOL(imx_ssi_fiq_end)151151-EXPORT_SYMBOL(imx_ssi_fiq_base)148148+
-925
arch/arm/mach-sa1100/include/mach/SA-1101.h
···11-/*22- * SA-1101.h33- *44- * Copyright (c) Peter Danielsson 199955- *66- * Definition of constants related to the sa110177- * support chip for the sa110088- *99- */1010-1111-1212-/* Be sure that virtual mapping is defined right */1313-#ifndef __ASM_ARCH_HARDWARE_H1414-#error You must include hardware.h not SA-1101.h1515-#endif1616-1717-#ifndef SA1101_BASE1818-#error You must define SA-1101 physical base address1919-#endif2020-2121-#ifndef LANGUAGE2222-# ifdef __ASSEMBLY__2323-# define LANGUAGE Assembly2424-# else2525-# define LANGUAGE C2626-# endif2727-#endif2828-2929-/*3030- * We have mapped the sa1101 depending on the value of SA1101_BASE.3131- * It then appears from 0xf4000000.3232- */3333-3434-#define SA1101_p2v( x ) ((x) - SA1101_BASE + 0xf4000000)3535-#define SA1101_v2p( x ) ((x) - 0xf4000000 + SA1101_BASE)3636-3737-#ifndef SA1101_p2v3838-#define SA1101_p2v(PhAdd) (PhAdd)3939-#endif4040-4141-#include <mach/bitfield.h>4242-4343-#define C 04444-#define Assembly 14545-4646-4747-/*4848- * Memory map4949- */5050-5151-#define __SHMEM_CONTROL0 0x000000005252-#define __SYSTEM_CONTROL1 0x000004005353-#define __ARBITER 0x000200005454-#define __SYSTEM_CONTROL2 0x000400005555-#define __SYSTEM_CONTROL3 0x000600005656-#define __PARALLEL_PORT 0x000800005757-#define __VIDMEM_CONTROL 0x001000005858-#define __UPDATE_FIFO 0x001200005959-#define __SHMEM_CONTROL1 0x001400006060-#define __INTERRUPT_CONTROL 0x001600006161-#define __USB_CONTROL 0x001800006262-#define __TRACK_INTERFACE 0x001a00006363-#define __MOUSE_INTERFACE 0x001b00006464-#define __KEYPAD_INTERFACE 0x001c00006565-#define __PCMCIA_INTERFACE 0x001e00006666-#define __VGA_CONTROL 0x002000006767-#define __GPIO_INTERFACE 0x003000006868-6969-/*7070- * Macro that calculates real address for registers in the SA-11017171- */7272-7373-#define _SA1101( x ) ((x) + SA1101_BASE)7474-7575-/*7676- * Interface and shared memory controller registers7777- *7878- * Registers7979- * SKCR SA-1101 control register (read/write)8080- * SMCR Shared Memory Controller Register8181- * SNPR Snoop Register8282- */8383-8484-#define _SKCR _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */8585-#define _SMCR _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */8686-#define _SNPR _SA1101( 0x00140400 ) /* Snoop Reg. */8787-8888-#if LANGUAGE == C8989-#define SKCR (*((volatile Word *) SA1101_p2v (_SKCR)))9090-#define SMCR (*((volatile Word *) SA1101_p2v (_SMCR)))9191-#define SNPR (*((volatile Word *) SA1101_p2v (_SNPR)))9292-9393-#define SKCR_PLLEn 0x0001 /* Enable On-Chip PLL */9494-#define SKCR_BCLKEn 0x0002 /* Enables BCLK */9595-#define SKCR_Sleep 0x0004 /* Sleep Mode */9696-#define SKCR_IRefEn 0x0008 /* DAC Iref input enable */9797-#define SKCR_VCOON 0x0010 /* VCO bias */9898-#define SKCR_ScanTestEn 0x0020 /* Enables scan test */9999-#define SKCR_ClockTestEn 0x0040 /* Enables clock test */100100-101101-#define SMCR_DCAC Fld(2,0) /* Number of column address bits */102102-#define SMCR_DRAC Fld(2,2) /* Number of row address bits */103103-#define SMCR_ArbiterBias 0x0008 /* favor video or USB */104104-#define SMCR_TopVidMem Fld(4,5) /* Top 4 bits of vidmem addr. */105105-106106-#define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \107107- (( (x) - 8 ) << FShft (SMCR_DCAC))108108-#define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\109109- (( (x) - 9 ) << FShft (SMCR_DRAC))110110-111111-#define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */112112-#define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */113113-#define SNPR_WholeBank (1 << 23) /* Whole bank bit */114114-#define SNPR_BankSelect Fld(2,27) /* Bank select */115115-#define SNPR_SnoopEn (1 << 31) /* Enable snoop operation */116116-117117-#define SNPR_Set_VFBsize( x ) /* set frame buffer size (in kb) */ \118118- ( (x) << FShft (SNPR_VFBsize))119119-#define SNPR_Select_Bank(x) /* select bank 0 or 1 */ \120120- (( (x) + 1 ) << FShft (SNPR_BankSelect ))121121-122122-#endif /* LANGUAGE == C */123123-124124-/*125125- * Video Memory Controller126126- *127127- * Registers128128- * VMCCR Configuration register129129- * VMCAR VMC address register130130- * VMCDR VMC data register131131- *132132- */133133-134134-#define _VMCCR _SA1101( 0x00100000 ) /* Configuration register */135135-#define _VMCAR _SA1101( 0x00101000 ) /* VMC address register */136136-#define _VMCDR _SA1101( 0x00101400 ) /* VMC data register */137137-138138-#if LANGUAGE == C139139-#define VMCCR (*((volatile Word *) SA1101_p2v (_VMCCR)))140140-#define VMCAR (*((volatile Word *) SA1101_p2v (_VMCAR)))141141-#define VMCDR (*((volatile Word *) SA1101_p2v (_VMCDR)))142142-143143-#define VMCCR_RefreshEn 0x0000 /* Enable memory refresh */144144-#define VMCCR_Config 0x0001 /* DRAM size */145145-#define VMCCR_RefPeriod Fld(2,3) /* Refresh period */146146-#define VMCCR_StaleDataWait Fld(4,5) /* Stale FIFO data timeout counter */147147-#define VMCCR_SleepState (1<<9) /* State of interface pins in sleep*/148148-#define VMCCR_RefTest (1<<10) /* refresh test */149149-#define VMCCR_RefLow Fld(6,11) /* refresh low counter */150150-#define VMCCR_RefHigh Fld(7,17) /* refresh high counter */151151-#define VMCCR_SDTCTest Fld(7,24) /* stale data timeout counter */152152-#define VMCCR_ForceSelfRef (1<<31) /* Force self refresh */153153-154154-#endif LANGUAGE == C155155-156156-157157-/* Update FIFO158158- *159159- * Registers160160- * UFCR Update FIFO Control Register161161- * UFSR Update FIFO Status Register162162- * UFLVLR update FIFO level register163163- * UFDR update FIFO data register164164- */165165-166166-#define _UFCR _SA1101(0x00120000) /* Update FIFO Control Reg. */167167-#define _UFSR _SA1101(0x00120400) /* Update FIFO Status Reg. */ 168168-#define _UFLVLR _SA1101(0x00120800) /* Update FIFO level reg. */169169-#define _UFDR _SA1101(0x00120c00) /* Update FIFO data reg. */170170-171171-#if LANGUAGE == C172172-173173-#define UFCR (*((volatile Word *) SA1101_p2v (_UFCR)))174174-#define UFSR (*((volatile Word *) SA1101_p2v (_UFSR)))175175-#define UFLVLR (*((volatile Word *) SA1101_p2v (_UFLVLR))) 176176-#define UFDR (*((volatile Word *) SA1101_p2v (_UFDR)))177177-178178-179179-#define UFCR_FifoThreshhold Fld(7,0) /* Level for FifoGTn flag */180180-181181-#define UFSR_FifoGTnFlag 0x01 /* FifoGTn flag */#define UFSR_FifoEmpty 0x80 /* FIFO is empty */182182-183183-#endif /* LANGUAGE == C */184184-185185-/* System Controller186186- *187187- * Registers188188- * SKPCR Power Control Register189189- * SKCDR Clock Divider Register190190- * DACDR1 DAC1 Data register191191- * DACDR2 DAC2 Data register192192- */193193-194194-#define _SKPCR _SA1101(0x00000400)195195-#define _SKCDR _SA1101(0x00040000)196196-#define _DACDR1 _SA1101(0x00060000)197197-#define _DACDR2 _SA1101(0x00060400)198198-199199-#if LANGUAGE == C200200-#define SKPCR (*((volatile Word *) SA1101_p2v (_SKPCR)))201201-#define SKCDR (*((volatile Word *) SA1101_p2v (_SKCDR)))202202-#define DACDR1 (*((volatile Word *) SA1101_p2v (_DACDR1)))203203-#define DACDR2 (*((volatile Word *) SA1101_p2v (_DACDR2)))204204-205205-#define SKPCR_UCLKEn 0x01 /* USB Enable */206206-#define SKPCR_PCLKEn 0x02 /* PS/2 Enable */207207-#define SKPCR_ICLKEn 0x04 /* Interrupt Controller Enable */208208-#define SKPCR_VCLKEn 0x08 /* Video Controller Enable */209209-#define SKPCR_PICLKEn 0x10 /* parallel port Enable */210210-#define SKPCR_DCLKEn 0x20 /* DACs Enable */211211-#define SKPCR_nKPADEn 0x40 /* Multiplexer */212212-213213-#define SKCDR_PLLMul Fld(7,0) /* PLL Multiplier */214214-#define SKCDR_VCLKEn Fld(2,7) /* Video controller clock divider */215215-#define SKDCR_BCLKEn (1<<9) /* BCLK Divider */216216-#define SKDCR_UTESTCLKEn (1<<10) /* Route USB clock during test mode */217217-#define SKDCR_DivRValue Fld(6,11) /* Input clock divider for PLL */218218-#define SKDCR_DivNValue Fld(5,17) /* Output clock divider for PLL */219219-#define SKDCR_PLLRSH Fld(3,22) /* PLL bandwidth control */220220-#define SKDCR_ChargePump (1<<25) /* Charge pump control */221221-#define SKDCR_ClkTestMode (1<<26) /* Clock output test mode */222222-#define SKDCR_ClkTestEn (1<<27) /* Test clock generator */223223-#define SKDCR_ClkJitterCntl Fld(3,28) /* video clock jitter compensation */224224-225225-#define DACDR_DACCount Fld(8,0) /* Count value */226226-#define DACDR1_DACCount DACDR_DACCount227227-#define DACDR2_DACCount DACDR_DACCount228228-229229-#endif /* LANGUAGE == C */230230-231231-/*232232- * Parallel Port Interface233233- *234234- * Registers235235- * IEEE_Config IEEE mode selection and programmable attributes236236- * IEEE_Control Controls the states of IEEE port control outputs237237- * IEEE_Data Forward transfer data register238238- * IEEE_Addr Forward transfer address register239239- * IEEE_Status Port IO signal status register240240- * IEEE_IntStatus Port interrupts status register241241- * IEEE_FifoLevels Rx and Tx FIFO interrupt generation levels242242- * IEEE_InitTime Forward timeout counter initial value243243- * IEEE_TimerStatus Forward timeout counter current value244244- * IEEE_FifoReset Reset forward transfer FIFO245245- * IEEE_ReloadValue Counter reload value246246- * IEEE_TestControl Control testmode247247- * IEEE_TestDataIn Test data register248248- * IEEE_TestDataInEn Enable test data249249- * IEEE_TestCtrlIn Test control signals250250- * IEEE_TestCtrlInEn Enable test control signals251251- * IEEE_TestDataStat Current data bus value252252- *253253- */254254-255255-/*256256- * The control registers are defined as offsets from a base address 257257- */258258-259259-#define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT )260260-261261-#define _IEEE_Config _IEEE( 0x0000 )262262-#define _IEEE_Control _IEEE( 0x0400 )263263-#define _IEEE_Data _IEEE( 0x4000 )264264-#define _IEEE_Addr _IEEE( 0x0800 )265265-#define _IEEE_Status _IEEE( 0x0c00 )266266-#define _IEEE_IntStatus _IEEE( 0x1000 )267267-#define _IEEE_FifoLevels _IEEE( 0x1400 )268268-#define _IEEE_InitTime _IEEE( 0x1800 )269269-#define _IEEE_TimerStatus _IEEE( 0x1c00 )270270-#define _IEEE_FifoReset _IEEE( 0x2000 )271271-#define _IEEE_ReloadValue _IEEE( 0x3c00 )272272-#define _IEEE_TestControl _IEEE( 0x2400 )273273-#define _IEEE_TestDataIn _IEEE( 0x2800 )274274-#define _IEEE_TestDataInEn _IEEE( 0x2c00 )275275-#define _IEEE_TestCtrlIn _IEEE( 0x3000 )276276-#define _IEEE_TestCtrlInEn _IEEE( 0x3400 )277277-#define _IEEE_TestDataStat _IEEE( 0x3800 )278278-279279-280280-#if LANGUAGE == C281281-#define IEEE_Config (*((volatile Word *) SA1101_p2v (_IEEE_Config)))282282-#define IEEE_Control (*((volatile Word *) SA1101_p2v (_IEEE_Control)))283283-#define IEEE_Data (*((volatile Word *) SA1101_p2v (_IEEE_Data)))284284-#define IEEE_Addr (*((volatile Word *) SA1101_p2v (_IEEE_Addr)))285285-#define IEEE_Status (*((volatile Word *) SA1101_p2v (_IEEE_Status)))286286-#define IEEE_IntStatus (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus)))287287-#define IEEE_FifoLevels (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels)))288288-#define IEEE_InitTime (*((volatile Word *) SA1101_p2v (_IEEE_InitTime)))289289-#define IEEE_TimerStatus (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus)))290290-#define IEEE_FifoReset (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset)))291291-#define IEEE_ReloadValue (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue)))292292-#define IEEE_TestControl (*((volatile Word *) SA1101_p2v (_IEEE_TestControl)))293293-#define IEEE_TestDataIn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn)))294294-#define IEEE_TestDataInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn)))295295-#define IEEE_TestCtrlIn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn)))296296-#define IEEE_TestCtrlInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn)))297297-#define IEEE_TestDataStat (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat)))298298-299299-300300-#define IEEE_Config_M Fld(3,0) /* Mode select */301301-#define IEEE_Config_D 0x04 /* FIFO access enable */302302-#define IEEE_Config_B 0x08 /* 9-bit word enable */303303-#define IEEE_Config_T 0x10 /* Data transfer enable */304304-#define IEEE_Config_A 0x20 /* Data transfer direction */305305-#define IEEE_Config_E 0x40 /* Timer enable */306306-#define IEEE_Control_A 0x08 /* AutoFd output */307307-#define IEEE_Control_E 0x04 /* Selectin output */308308-#define IEEE_Control_T 0x02 /* Strobe output */309309-#define IEEE_Control_I 0x01 /* Port init output */310310-#define IEEE_Data_C (1<<31) /* Byte count */311311-#define IEEE_Data_Db Fld(9,16) /* Data byte 2 */312312-#define IEEE_Data_Da Fld(9,0) /* Data byte 1 */313313-#define IEEE_Addr_A Fld(8,0) /* forward address transfer byte */314314-#define IEEE_Status_A 0x0100 /* nAutoFd port output status */315315-#define IEEE_Status_E 0x0080 /* nSelectIn port output status */316316-#define IEEE_Status_T 0x0040 /* nStrobe port output status */317317-#define IEEE_Status_I 0x0020 /* nInit port output status */318318-#define IEEE_Status_B 0x0010 /* Busy port inout status */319319-#define IEEE_Status_S 0x0008 /* Select port input status */320320-#define IEEE_Status_K 0x0004 /* nAck port input status */321321-#define IEEE_Status_F 0x0002 /* nFault port input status */322322-#define IEEE_Status_R 0x0001 /* pError port input status */323323-324324-#define IEEE_IntStatus_IntReqDat 0x0100325325-#define IEEE_IntStatus_IntReqEmp 0x0080326326-#define IEEE_IntStatus_IntReqInt 0x0040327327-#define IEEE_IntStatus_IntReqRav 0x0020328328-#define IEEE_IntStatus_IntReqTim 0x0010329329-#define IEEE_IntStatus_RevAddrComp 0x0008330330-#define IEEE_IntStatus_RevDataComp 0x0004331331-#define IEEE_IntStatus_FwdAddrComp 0x0002332332-#define IEEE_IntStatus_FwdDataComp 0x0001333333-#define IEEE_FifoLevels_RevFifoLevel 2334334-#define IEEE_FifoLevels_FwdFifoLevel 1335335-#define IEEE_InitTime_TimValInit Fld(22,0)336336-#define IEEE_TimerStatus_TimValStat Fld(22,0)337337-#define IEEE_ReloadValue_Reload Fld(4,0)338338-339339-#define IEEE_TestControl_RegClk 0x04340340-#define IEEE_TestControl_ClockSelect Fld(2,1)341341-#define IEEE_TestControl_TimerTestModeEn 0x01342342-#define IEEE_TestCtrlIn_PError 0x10343343-#define IEEE_TestCtrlIn_nFault 0x08344344-#define IEEE_TestCtrlIn_nAck 0x04345345-#define IEEE_TestCtrlIn_PSel 0x02346346-#define IEEE_TestCtrlIn_Busy 0x01347347-348348-#endif /* LANGUAGE == C */349349-350350-/*351351- * VGA Controller352352- *353353- * Registers354354- * VideoControl Video Control Register355355- * VgaTiming0 VGA Timing Register 0356356- * VgaTiming1 VGA Timing Register 1357357- * VgaTiming2 VGA Timing Register 2358358- * VgaTiming3 VGA Timing Register 3359359- * VgaBorder VGA Border Color Register360360- * VgaDBAR VGADMA Base Address Register361361- * VgaDCAR VGADMA Channel Current Address Register362362- * VgaStatus VGA Status Register363363- * VgaInterruptMask VGA Interrupt Mask Register364364- * VgaPalette VGA Palette Registers365365- * DacControl DAC Control Register366366- * VgaTest VGA Controller Test Register367367- */368368-369369-#define _VGA( x ) _SA1101( ( x ) + __VGA_CONTROL )370370-371371-#define _VideoControl _VGA( 0x0000 )372372-#define _VgaTiming0 _VGA( 0x0400 )373373-#define _VgaTiming1 _VGA( 0x0800 )374374-#define _VgaTiming2 _VGA( 0x0c00 )375375-#define _VgaTiming3 _VGA( 0x1000 )376376-#define _VgaBorder _VGA( 0x1400 )377377-#define _VgaDBAR _VGA( 0x1800 )378378-#define _VgaDCAR _VGA( 0x1c00 )379379-#define _VgaStatus _VGA( 0x2000 )380380-#define _VgaInterruptMask _VGA( 0x2400 )381381-#define _VgaPalette _VGA( 0x40000 )382382-#define _DacControl _VGA( 0x3000 )383383-#define _VgaTest _VGA( 0x2c00 )384384-385385-#if (LANGUAGE == C)386386-#define VideoControl (*((volatile Word *) SA1101_p2v (_VideoControl)))387387-#define VgaTiming0 (*((volatile Word *) SA1101_p2v (_VgaTiming0)))388388-#define VgaTiming1 (*((volatile Word *) SA1101_p2v (_VgaTiming1)))389389-#define VgaTiming2 (*((volatile Word *) SA1101_p2v (_VgaTiming2)))390390-#define VgaTiming3 (*((volatile Word *) SA1101_p2v (_VgaTiming3)))391391-#define VgaBorder (*((volatile Word *) SA1101_p2v (_VgaBorder)))392392-#define VgaDBAR (*((volatile Word *) SA1101_p2v (_VgaDBAR)))393393-#define VgaDCAR (*((volatile Word *) SA1101_p2v (_VgaDCAR)))394394-#define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus)))395395-#define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask)))396396-#define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette)))397397-#define DacControl (*((volatile Word *) SA1101_p2v (_DacControl)))398398-#define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest)))399399-400400-#define VideoControl_VgaEn 0x00000000401401-#define VideoControl_BGR 0x00000001402402-#define VideoControl_VCompVal Fld(2,2)403403-#define VideoControl_VgaReq Fld(4,4)404404-#define VideoControl_VBurstL Fld(4,8)405405-#define VideoControl_VMode (1<<12)406406-#define VideoControl_PalRead (1<<13)407407-408408-#define VgaTiming0_PPL Fld(6,2)409409-#define VgaTiming0_HSW Fld(8,8)410410-#define VgaTiming0_HFP Fld(8,16)411411-#define VgaTiming0_HBP Fld(8,24)412412-413413-#define VgaTiming1_LPS Fld(10,0)414414-#define VgaTiming1_VSW Fld(6,10)415415-#define VgaTiming1_VFP Fld(8,16)416416-#define VgaTiming1_VBP Fld(8,24)417417-418418-#define VgaTiming2_IVS 0x01419419-#define VgaTiming2_IHS 0x02420420-#define VgaTiming2_CVS 0x04421421-#define VgaTiming2_CHS 0x08422422-423423-#define VgaTiming3_HBS Fld(8,0)424424-#define VgaTiming3_HBE Fld(8,8)425425-#define VgaTiming3_VBS Fld(8,16)426426-#define VgaTiming3_VBE Fld(8,24)427427-428428-#define VgaBorder_BCOL Fld(24,0)429429-430430-#define VgaStatus_VFUF 0x01431431-#define VgaStatus_VNext 0x02432432-#define VgaStatus_VComp 0x04433433-434434-#define VgaInterruptMask_VFUFMask 0x00435435-#define VgaInterruptMask_VNextMask 0x01436436-#define VgaInterruptMask_VCompMask 0x02437437-438438-#define VgaPalette_R Fld(8,0)439439-#define VgaPalette_G Fld(8,8)440440-#define VgaPalette_B Fld(8,16)441441-442442-#define DacControl_DACON 0x0001443443-#define DacControl_COMPON 0x0002444444-#define DacControl_PEDON 0x0004445445-#define DacControl_RTrim Fld(5,4)446446-#define DacControl_GTrim Fld(5,9)447447-#define DacControl_BTrim Fld(5,14)448448-449449-#define VgaTest_TDAC 0x00450450-#define VgaTest_Datatest Fld(4,1)451451-#define VgaTest_DACTESTDAC 0x10452452-#define VgaTest_DACTESTOUT Fld(3,5)453453-454454-#endif /* LANGUAGE == C */455455-456456-/*457457- * USB Host Interface Controller458458- *459459- * Registers460460- * Revision461461- * Control462462- * CommandStatus463463- * InterruptStatus464464- * InterruptEnable465465- * HCCA466466- * PeriodCurrentED467467- * ControlHeadED468468- * BulkHeadED469469- * BulkCurrentED470470- * DoneHead471471- * FmInterval472472- * FmRemaining473473- * FmNumber474474- * PeriodicStart475475- * LSThreshold476476- * RhDescriptorA477477- * RhDescriptorB478478- * RhStatus479479- * RhPortStatus480480- * USBStatus481481- * USBReset482482- * USTAR483483- * USWER484484- * USRFR485485- * USNFR486486- * USTCSR487487- * USSR488488- * 489489- */490490-491491-#define _USB( x ) _SA1101( ( x ) + __USB_CONTROL )492492-493493-494494-#define _Revision _USB( 0x0000 )495495-#define _Control _USB( 0x0888 )496496-#define _CommandStatus _USB( 0x0c00 )497497-#define _InterruptStatus _USB( 0x1000 )498498-#define _InterruptEnable _USB( 0x1400 )499499-#define _HCCA _USB( 0x1800 )500500-#define _PeriodCurrentED _USB( 0x1c00 )501501-#define _ControlHeadED _USB( 0x2000 )502502-#define _BulkHeadED _USB( 0x2800 )503503-#define _BulkCurrentED _USB( 0x2c00 )504504-#define _DoneHead _USB( 0x3000 )505505-#define _FmInterval _USB( 0x3400 )506506-#define _FmRemaining _USB( 0x3800 )507507-#define _FmNumber _USB( 0x3c00 )508508-#define _PeriodicStart _USB( 0x4000 )509509-#define _LSThreshold _USB( 0x4400 )510510-#define _RhDescriptorA _USB( 0x4800 )511511-#define _RhDescriptorB _USB( 0x4c00 )512512-#define _RhStatus _USB( 0x5000 )513513-#define _RhPortStatus _USB( 0x5400 )514514-#define _USBStatus _USB( 0x11800 )515515-#define _USBReset _USB( 0x11c00 )516516-517517-#define _USTAR _USB( 0x10400 )518518-#define _USWER _USB( 0x10800 )519519-#define _USRFR _USB( 0x10c00 )520520-#define _USNFR _USB( 0x11000 )521521-#define _USTCSR _USB( 0x11400 )522522-#define _USSR _USB( 0x11800 )523523-524524-525525-#if (LANGUAGE == C)526526-527527-#define Revision (*((volatile Word *) SA1101_p2v (_Revision)))528528-#define Control (*((volatile Word *) SA1101_p2v (_Control)))529529-#define CommandStatus (*((volatile Word *) SA1101_p2v (_CommandStatus)))530530-#define InterruptStatus (*((volatile Word *) SA1101_p2v (_InterruptStatus)))531531-#define InterruptEnable (*((volatile Word *) SA1101_p2v (_InterruptEnable)))532532-#define HCCA (*((volatile Word *) SA1101_p2v (_HCCA)))533533-#define PeriodCurrentED (*((volatile Word *) SA1101_p2v (_PeriodCurrentED)))534534-#define ControlHeadED (*((volatile Word *) SA1101_p2v (_ControlHeadED)))535535-#define BulkHeadED (*((volatile Word *) SA1101_p2v (_BulkHeadED)))536536-#define BulkCurrentED (*((volatile Word *) SA1101_p2v (_BulkCurrentED)))537537-#define DoneHead (*((volatile Word *) SA1101_p2v (_DoneHead)))538538-#define FmInterval (*((volatile Word *) SA1101_p2v (_FmInterval)))539539-#define FmRemaining (*((volatile Word *) SA1101_p2v (_FmRemaining)))540540-#define FmNumber (*((volatile Word *) SA1101_p2v (_FmNumber)))541541-#define PeriodicStart (*((volatile Word *) SA1101_p2v (_PeriodicStart)))542542-#define LSThreshold (*((volatile Word *) SA1101_p2v (_LSThreshold)))543543-#define RhDescriptorA (*((volatile Word *) SA1101_p2v (_RhDescriptorA)))544544-#define RhDescriptorB (*((volatile Word *) SA1101_p2v (_RhDescriptorB)))545545-#define RhStatus (*((volatile Word *) SA1101_p2v (_RhStatus)))546546-#define RhPortStatus (*((volatile Word *) SA1101_p2v (_RhPortStatus)))547547-#define USBStatus (*((volatile Word *) SA1101_p2v (_USBStatus)))548548-#define USBReset (*((volatile Word *) SA1101_p2v (_USBReset)))549549-#define USTAR (*((volatile Word *) SA1101_p2v (_USTAR)))550550-#define USWER (*((volatile Word *) SA1101_p2v (_USWER)))551551-#define USRFR (*((volatile Word *) SA1101_p2v (_USRFR)))552552-#define USNFR (*((volatile Word *) SA1101_p2v (_USNFR)))553553-#define USTCSR (*((volatile Word *) SA1101_p2v (_USTCSR)))554554-#define USSR (*((volatile Word *) SA1101_p2v (_USSR)))555555-556556-557557-#define USBStatus_IrqHciRmtWkp (1<<7)558558-#define USBStatus_IrqHciBuffAcc (1<<8)559559-#define USBStatus_nIrqHciM (1<<9)560560-#define USBStatus_nHciMFClr (1<<10)561561-562562-#define USBReset_ForceIfReset 0x01563563-#define USBReset_ForceHcReset 0x02564564-#define USBReset_ClkGenReset 0x04565565-566566-#define USTCR_RdBstCntrl Fld(3,0)567567-#define USTCR_ByteEnable Fld(4,3)568568-#define USTCR_WriteEn (1<<7)569569-#define USTCR_FifoCir (1<<8)570570-#define USTCR_TestXferSel (1<<9)571571-#define USTCR_FifoCirAtEnd (1<<10)572572-#define USTCR_nSimScaleDownClk (1<<11)573573-574574-#define USSR_nAppMDEmpty 0x01575575-#define USSR_nAppMDFirst 0x02576576-#define USSR_nAppMDLast 0x04577577-#define USSR_nAppMDFull 0x08578578-#define USSR_nAppMAFull 0x10579579-#define USSR_XferReq 0x20580580-#define USSR_XferEnd 0x40581581-582582-#endif /* LANGUAGE == C */583583-584584-585585-/*586586- * Interrupt Controller587587- *588588- * Registers589589- * INTTEST0 Test register 0590590- * INTTEST1 Test register 1591591- * INTENABLE0 Interrupt Enable register 0592592- * INTENABLE1 Interrupt Enable register 1593593- * INTPOL0 Interrupt Polarity selection 0594594- * INTPOL1 Interrupt Polarity selection 1595595- * INTTSTSEL Interrupt source selection596596- * INTSTATCLR0 Interrupt Status 0597597- * INTSTATCLR1 Interrupt Status 1598598- * INTSET0 Interrupt Set 0599599- * INTSET1 Interrupt Set 1600600- */601601-602602-#define _INT( x ) _SA1101( ( x ) + __INTERRUPT_CONTROL)603603-604604-#define _INTTEST0 _INT( 0x1000 )605605-#define _INTTEST1 _INT( 0x1400 )606606-#define _INTENABLE0 _INT( 0x2000 )607607-#define _INTENABLE1 _INT( 0x2400 )608608-#define _INTPOL0 _INT( 0x3000 )609609-#define _INTPOL1 _INT( 0x3400 )610610-#define _INTTSTSEL _INT( 0x5000 )611611-#define _INTSTATCLR0 _INT( 0x6000 )612612-#define _INTSTATCLR1 _INT( 0x6400 )613613-#define _INTSET0 _INT( 0x7000 )614614-#define _INTSET1 _INT( 0x7400 )615615-616616-#if ( LANGUAGE == C )617617-#define INTTEST0 (*((volatile Word *) SA1101_p2v (_INTTEST0)))618618-#define INTTEST1 (*((volatile Word *) SA1101_p2v (_INTTEST1)))619619-#define INTENABLE0 (*((volatile Word *) SA1101_p2v (_INTENABLE0)))620620-#define INTENABLE1 (*((volatile Word *) SA1101_p2v (_INTENABLE1)))621621-#define INTPOL0 (*((volatile Word *) SA1101_p2v (_INTPOL0)))622622-#define INTPOL1 (*((volatile Word *) SA1101_p2v (_INTPOL1)))623623-#define INTTSTSEL (*((volatile Word *) SA1101_p2v (_INTTSTSEL)))624624-#define INTSTATCLR0 (*((volatile Word *) SA1101_p2v (_INTSTATCLR0)))625625-#define INTSTATCLR1 (*((volatile Word *) SA1101_p2v (_INTSTATCLR1)))626626-#define INTSET0 (*((volatile Word *) SA1101_p2v (_INTSET0)))627627-#define INTSET1 (*((volatile Word *) SA1101_p2v (_INTSET1)))628628-629629-#endif /* LANGUAGE == C */630630-631631-/*632632- * PS/2 Trackpad and Mouse Interfaces633633- *634634- * Registers (prefix kbd applies to trackpad interface, mse to mouse)635635- * KBDCR Control Register636636- * KBDSTAT Status Register637637- * KBDDATA Transmit/Receive Data register638638- * KBDCLKDIV Clock Division Register639639- * KBDPRECNT Clock Precount Register640640- * KBDTEST1 Test register 1641641- * KBDTEST2 Test register 2642642- * KBDTEST3 Test register 3643643- * KBDTEST4 Test register 4644644- * MSECR 645645- * MSESTAT646646- * MSEDATA647647- * MSECLKDIV648648- * MSEPRECNT649649- * MSETEST1650650- * MSETEST2651651- * MSETEST3652652- * MSETEST4653653- * 654654- */655655-656656-#define _KBD( x ) _SA1101( ( x ) + __TRACK_INTERFACE )657657-#define _MSE( x ) _SA1101( ( x ) + __MOUSE_INTERFACE )658658-659659-#define _KBDCR _KBD( 0x0000 )660660-#define _KBDSTAT _KBD( 0x0400 )661661-#define _KBDDATA _KBD( 0x0800 )662662-#define _KBDCLKDIV _KBD( 0x0c00 )663663-#define _KBDPRECNT _KBD( 0x1000 )664664-#define _KBDTEST1 _KBD( 0x2000 )665665-#define _KBDTEST2 _KBD( 0x2400 )666666-#define _KBDTEST3 _KBD( 0x2800 )667667-#define _KBDTEST4 _KBD( 0x2c00 )668668-#define _MSECR _MSE( 0x0000 )669669-#define _MSESTAT _MSE( 0x0400 )670670-#define _MSEDATA _MSE( 0x0800 )671671-#define _MSECLKDIV _MSE( 0x0c00 )672672-#define _MSEPRECNT _MSE( 0x1000 )673673-#define _MSETEST1 _MSE( 0x2000 )674674-#define _MSETEST2 _MSE( 0x2400 )675675-#define _MSETEST3 _MSE( 0x2800 )676676-#define _MSETEST4 _MSE( 0x2c00 )677677-678678-#if ( LANGUAGE == C )679679-680680-#define KBDCR (*((volatile Word *) SA1101_p2v (_KBDCR)))681681-#define KBDSTAT (*((volatile Word *) SA1101_p2v (_KBDSTAT)))682682-#define KBDDATA (*((volatile Word *) SA1101_p2v (_KBDDATA)))683683-#define KBDCLKDIV (*((volatile Word *) SA1101_p2v (_KBDCLKDIV)))684684-#define KBDPRECNT (*((volatile Word *) SA1101_p2v (_KBDPRECNT)))685685-#define KBDTEST1 (*((volatile Word *) SA1101_p2v (_KBDTEST1)))686686-#define KBDTEST2 (*((volatile Word *) SA1101_p2v (_KBDTEST2)))687687-#define KBDTEST3 (*((volatile Word *) SA1101_p2v (_KBDTEST3)))688688-#define KBDTEST4 (*((volatile Word *) SA1101_p2v (_KBDTEST4)))689689-#define MSECR (*((volatile Word *) SA1101_p2v (_MSECR)))690690-#define MSESTAT (*((volatile Word *) SA1101_p2v (_MSESTAT)))691691-#define MSEDATA (*((volatile Word *) SA1101_p2v (_MSEDATA)))692692-#define MSECLKDIV (*((volatile Word *) SA1101_p2v (_MSECLKDIV)))693693-#define MSEPRECNT (*((volatile Word *) SA1101_p2v (_MSEPRECNT)))694694-#define MSETEST1 (*((volatile Word *) SA1101_p2v (_MSETEST1)))695695-#define MSETEST2 (*((volatile Word *) SA1101_p2v (_MSETEST2)))696696-#define MSETEST3 (*((volatile Word *) SA1101_p2v (_MSETEST3)))697697-#define MSETEST4 (*((volatile Word *) SA1101_p2v (_MSETEST4)))698698-699699-700700-#define KBDCR_ENA 0x08701701-#define KBDCR_FKD 0x02702702-#define KBDCR_FKC 0x01703703-704704-#define KBDSTAT_TXE 0x80705705-#define KBDSTAT_TXB 0x40706706-#define KBDSTAT_RXF 0x20707707-#define KBDSTAT_RXB 0x10708708-#define KBDSTAT_ENA 0x08709709-#define KBDSTAT_RXP 0x04710710-#define KBDSTAT_KBD 0x02711711-#define KBDSTAT_KBC 0x01712712-713713-#define KBDCLKDIV_DivVal Fld(4,0)714714-715715-#define MSECR_ENA 0x08716716-#define MSECR_FKD 0x02717717-#define MSECR_FKC 0x01718718-719719-#define MSESTAT_TXE 0x80720720-#define MSESTAT_TXB 0x40721721-#define MSESTAT_RXF 0x20722722-#define MSESTAT_RXB 0x10723723-#define MSESTAT_ENA 0x08724724-#define MSESTAT_RXP 0x04 725725-#define MSESTAT_MSD 0x02726726-#define MSESTAT_MSC 0x01727727-728728-#define MSECLKDIV_DivVal Fld(4,0)729729-730730-#define KBDTEST1_CD 0x80731731-#define KBDTEST1_RC1 0x40732732-#define KBDTEST1_MC 0x20733733-#define KBDTEST1_C Fld(2,3)734734-#define KBDTEST1_T2 0x40735735-#define KBDTEST1_T1 0x20736736-#define KBDTEST1_T0 0x10737737-#define KBDTEST2_TICBnRES 0x08738738-#define KBDTEST2_RKC 0x04739739-#define KBDTEST2_RKD 0x02740740-#define KBDTEST2_SEL 0x01741741-#define KBDTEST3_ms_16 0x80742742-#define KBDTEST3_us_64 0x40743743-#define KBDTEST3_us_16 0x20744744-#define KBDTEST3_DIV8 0x10745745-#define KBDTEST3_DIn 0x08746746-#define KBDTEST3_CIn 0x04747747-#define KBDTEST3_KD 0x02748748-#define KBDTEST3_KC 0x01749749-#define KBDTEST4_BC12 0x80750750-#define KBDTEST4_BC11 0x40751751-#define KBDTEST4_TRES 0x20752752-#define KBDTEST4_CLKOE 0x10753753-#define KBDTEST4_CRES 0x08754754-#define KBDTEST4_RXB 0x04755755-#define KBDTEST4_TXB 0x02756756-#define KBDTEST4_SRX 0x01757757-758758-#define MSETEST1_CD 0x80759759-#define MSETEST1_RC1 0x40760760-#define MSETEST1_MC 0x20761761-#define MSETEST1_C Fld(2,3)762762-#define MSETEST1_T2 0x40763763-#define MSETEST1_T1 0x20764764-#define MSETEST1_T0 0x10765765-#define MSETEST2_TICBnRES 0x08766766-#define MSETEST2_RKC 0x04767767-#define MSETEST2_RKD 0x02768768-#define MSETEST2_SEL 0x01769769-#define MSETEST3_ms_16 0x80770770-#define MSETEST3_us_64 0x40771771-#define MSETEST3_us_16 0x20772772-#define MSETEST3_DIV8 0x10773773-#define MSETEST3_DIn 0x08774774-#define MSETEST3_CIn 0x04775775-#define MSETEST3_KD 0x02776776-#define MSETEST3_KC 0x01777777-#define MSETEST4_BC12 0x80778778-#define MSETEST4_BC11 0x40779779-#define MSETEST4_TRES 0x20780780-#define MSETEST4_CLKOE 0x10781781-#define MSETEST4_CRES 0x08782782-#define MSETEST4_RXB 0x04783783-#define MSETEST4_TXB 0x02784784-#define MSETEST4_SRX 0x01785785-786786-#endif /* LANGUAGE == C */787787-788788-789789-/*790790- * General-Purpose I/O Interface791791- *792792- * Registers793793- * PADWR Port A Data Write Register794794- * PBDWR Port B Data Write Register795795- * PADRR Port A Data Read Register796796- * PBDRR Port B Data Read Register797797- * PADDR Port A Data Direction Register798798- * PBDDR Port B Data Direction Register799799- * PASSR Port A Sleep State Register800800- * PBSSR Port B Sleep State Register801801- *802802- */803803-804804-#define _PIO( x ) _SA1101( ( x ) + __GPIO_INTERFACE )805805-806806-#define _PADWR _PIO( 0x0000 )807807-#define _PBDWR _PIO( 0x0400 )808808-#define _PADRR _PIO( 0x0000 )809809-#define _PBDRR _PIO( 0x0400 )810810-#define _PADDR _PIO( 0x0800 )811811-#define _PBDDR _PIO( 0x0c00 )812812-#define _PASSR _PIO( 0x1000 )813813-#define _PBSSR _PIO( 0x1400 )814814-815815-816816-#if ( LANGUAGE == C )817817-818818-819819-#define PADWR (*((volatile Word *) SA1101_p2v (_PADWR)))820820-#define PBDWR (*((volatile Word *) SA1101_p2v (_PBDWR)))821821-#define PADRR (*((volatile Word *) SA1101_p2v (_PADRR)))822822-#define PBDRR (*((volatile Word *) SA1101_p2v (_PBDRR)))823823-#define PADDR (*((volatile Word *) SA1101_p2v (_PADDR)))824824-#define PBDDR (*((volatile Word *) SA1101_p2v (_PBDDR)))825825-#define PASSR (*((volatile Word *) SA1101_p2v (_PASSR)))826826-#define PBSSR (*((volatile Word *) SA1101_p2v (_PBSSR)))827827-828828-#endif829829-830830-831831-832832-/*833833- * Keypad Interface834834- *835835- * Registers836836- * PXDWR837837- * PXDRR838838- * PYDWR839839- * PYDRR840840- *841841- */842842-843843-#define _KEYPAD( x ) _SA1101( ( x ) + __KEYPAD_INTERFACE ) 844844-845845-#define _PXDWR _KEYPAD( 0x0000 )846846-#define _PXDRR _KEYPAD( 0x0000 )847847-#define _PYDWR _KEYPAD( 0x0400 )848848-#define _PYDRR _KEYPAD( 0x0400 )849849-850850-#if ( LANGUAGE == C )851851-852852-853853-#define PXDWR (*((volatile Word *) SA1101_p2v (_PXDWR)))854854-#define PXDRR (*((volatile Word *) SA1101_p2v (_PXDRR)))855855-#define PYDWR (*((volatile Word *) SA1101_p2v (_PYDWR)))856856-#define PYDRR (*((volatile Word *) SA1101_p2v (_PYDRR)))857857-858858-#endif859859-860860-861861-862862-/*863863- * PCMCIA Interface864864- *865865- * Registers866866- * PCSR Status Register867867- * PCCR Control Register868868- * PCSSR Sleep State Register869869- *870870- */871871-872872-#define _CARD( x ) _SA1101( ( x ) + __PCMCIA_INTERFACE )873873-874874-#define _PCSR _CARD( 0x0000 )875875-#define _PCCR _CARD( 0x0400 )876876-#define _PCSSR _CARD( 0x0800 )877877-878878-#if ( LANGUAGE == C )879879-#define PCSR (*((volatile Word *) SA1101_p2v (_PCSR)))880880-#define PCCR (*((volatile Word *) SA1101_p2v (_PCCR)))881881-#define PCSSR (*((volatile Word *) SA1101_p2v (_PCSSR)))882882-883883-#define PCSR_S0_ready 0x0001884884-#define PCSR_S1_ready 0x0002885885-#define PCSR_S0_detected 0x0004886886-#define PCSR_S1_detected 0x0008887887-#define PCSR_S0_VS1 0x0010888888-#define PCSR_S0_VS2 0x0020889889-#define PCSR_S1_VS1 0x0040890890-#define PCSR_S1_VS2 0x0080891891-#define PCSR_S0_WP 0x0100892892-#define PCSR_S1_WP 0x0200893893-#define PCSR_S0_BVD1_nSTSCHG 0x0400894894-#define PCSR_S0_BVD2_nSPKR 0x0800895895-#define PCSR_S1_BVD1_nSTSCHG 0x1000896896-#define PCSR_S1_BVD2_nSPKR 0x2000897897-898898-#define PCCR_S0_VPP0 0x0001899899-#define PCCR_S0_VPP1 0x0002900900-#define PCCR_S0_VCC0 0x0004901901-#define PCCR_S0_VCC1 0x0008902902-#define PCCR_S1_VPP0 0x0010903903-#define PCCR_S1_VPP1 0x0020904904-#define PCCR_S1_VCC0 0x0040905905-#define PCCR_S1_VCC1 0x0080906906-#define PCCR_S0_reset 0x0100907907-#define PCCR_S1_reset 0x0200908908-#define PCCR_S0_float 0x0400909909-#define PCCR_S1_float 0x0800910910-911911-#define PCSSR_S0_VCC0 0x0001912912-#define PCSSR_S0_VCC1 0x0002913913-#define PCSSR_S0_VPP0 0x0004914914-#define PCSSR_S0_VPP1 0x0008915915-#define PCSSR_S0_control 0x0010916916-#define PCSSR_S1_VCC0 0x0020917917-#define PCSSR_S1_VCC1 0x0040918918-#define PCSSR_S1_VPP0 0x0080919919-#define PCSSR_S1_VPP1 0x0100920920-#define PCSSR_S1_control 0x0200921921-922922-#endif923923-924924-#undef C925925-#undef Assembly