commit 41594663c3fb565940ec2b947bd7e623e3f0e600 · tjh.dev/kernel

tjh.dev / kernel

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Merge tag 'pinctrl-v6.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:

- Fix the hwirq map and pin offsets in the Qualcomm X1E80100 driver

- Fix the pin range handling in the AT91 driver so it works again

- Fix a NULL-dereference risk in pinctrl single

- Fix a serious biasing bug in the Mediatek driver

- Fix the level trigged IRQ in the StarFive JH7110

- Fix the iomux width in the Rockchip GPIO2-B pin handling

* tag 'pinctrl-v6.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: rockchip: correct RK3328 iomux width flag for GPIO2-B pins
pinctrl: starfive: jh7110: Correct the level trigger configuration of iev register
pinctrl: qcom: x1e80100: Fix special pin offsets
pinctrl: mediatek: common-v2: Fix broken bias-disable for PULL_PU_PD_RSEL_TYPE
pinctrl: single: fix potential NULL dereference in pcs_get_function()
pinctrl: at91: make it work with current gpiolib
pinctrl: qcom: x1e80100: Update PDC hwirq map

Linus Torvalds 1 year ago 41594663 6ace1c7e

+57 -46

6 changed files

expand all

unified split

drivers

pinctrl

mediatek

pinctrl-mtk-common-v2.c

pinctrl-at91.c

pinctrl-rockchip.c

pinctrl-single.c

qcom

pinctrl-x1e80100.c

starfive

pinctrl-starfive-jh7110.c

+29 -26

drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c

··· 709 709 { 710 710 int err, rsel_val; 711 711 712 - if (!pullup && arg == MTK_DISABLE) 713 - return 0; 714 - 715 712 if (hw->rsel_si_unit) { 716 713 /* find pin rsel_index from pin_rsel array*/ 717 714 err = mtk_hw_pin_rsel_lookup(hw, desc, pullup, arg, &rsel_val); 718 715 if (err) 719 - goto out; 716 + return err; 720 717 } else { 721 - if (arg < MTK_PULL_SET_RSEL_000 || 722 - arg > MTK_PULL_SET_RSEL_111) { 723 - err = -EINVAL; 724 - goto out; 725 - } 718 + if (arg < MTK_PULL_SET_RSEL_000 || arg > MTK_PULL_SET_RSEL_111) 719 + return -EINVAL; 726 720 727 721 rsel_val = arg - MTK_PULL_SET_RSEL_000; 728 722 } 729 723 730 - err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, rsel_val); 731 - if (err) 732 - goto out; 724 + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, rsel_val); 725 + } 733 726 734 - err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, MTK_ENABLE); 727 + static int mtk_pinconf_bias_set_pu_pd_rsel(struct mtk_pinctrl *hw, 728 + const struct mtk_pin_desc *desc, 729 + u32 pullup, u32 arg) 730 + { 731 + u32 enable = arg == MTK_DISABLE ? MTK_DISABLE : MTK_ENABLE; 732 + int err; 735 733 736 - out: 737 - return err; 734 + if (arg != MTK_DISABLE) { 735 + err = mtk_pinconf_bias_set_rsel(hw, desc, pullup, arg); 736 + if (err) 737 + return err; 738 + } 739 + 740 + return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable); 738 741 } 739 742 740 743 int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, ··· 753 750 try_all_type = MTK_PULL_TYPE_MASK; 754 751 755 752 if (try_all_type & MTK_PULL_RSEL_TYPE) { 756 - err = mtk_pinconf_bias_set_rsel(hw, desc, pullup, arg); 753 + err = mtk_pinconf_bias_set_pu_pd_rsel(hw, desc, pullup, arg); 757 754 if (!err) 758 - return err; 755 + return 0; 759 756 } 760 757 761 758 if (try_all_type & MTK_PULL_PU_PD_TYPE) { 762 759 err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); 763 760 if (!err) 764 - return err; 761 + return 0; 765 762 } 766 763 767 764 if (try_all_type & MTK_PULL_PULLSEL_TYPE) { 768 765 err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, 769 766 pullup, arg); 770 767 if (!err) 771 - return err; 768 + return 0; 772 769 } 773 770 774 771 if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE) ··· 806 803 return 0; 807 804 } 808 805 809 - static int mtk_pinconf_bias_get_rsel(struct mtk_pinctrl *hw, 810 - const struct mtk_pin_desc *desc, 811 - u32 *pullup, u32 *enable) 806 + static int mtk_pinconf_bias_get_pu_pd_rsel(struct mtk_pinctrl *hw, 807 + const struct mtk_pin_desc *desc, 808 + u32 *pullup, u32 *enable) 812 809 { 813 810 int pu, pd, rsel, err; 814 811 ··· 942 939 try_all_type = MTK_PULL_TYPE_MASK; 943 940 944 941 if (try_all_type & MTK_PULL_RSEL_TYPE) { 945 - err = mtk_pinconf_bias_get_rsel(hw, desc, pullup, enable); 942 + err = mtk_pinconf_bias_get_pu_pd_rsel(hw, desc, pullup, enable); 946 943 if (!err) 947 - return err; 944 + return 0; 948 945 } 949 946 950 947 if (try_all_type & MTK_PULL_PU_PD_TYPE) { 951 948 err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); 952 949 if (!err) 953 - return err; 950 + return 0; 954 951 } 955 952 956 953 if (try_all_type & MTK_PULL_PULLSEL_TYPE) { 957 954 err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, 958 955 pullup, enable); 959 956 if (!err) 960 - return err; 957 + return 0; 961 958 } 962 959 963 960 if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE)

+4 -1

drivers/pinctrl/pinctrl-at91.c

··· 1403 1403 1404 1404 /* We will handle a range of GPIO pins */ 1405 1405 for (i = 0; i < gpio_banks; i++) 1406 - if (gpio_chips[i]) 1406 + if (gpio_chips[i]) { 1407 1407 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); 1408 + gpiochip_add_pin_range(&gpio_chips[i]->chip, dev_name(info->pctl->dev), 0, 1409 + gpio_chips[i]->range.pin_base, gpio_chips[i]->range.npins); 1410 + } 1408 1411 1409 1412 dev_info(dev, "initialized AT91 pinctrl driver\n"); 1410 1413

+1 -1

drivers/pinctrl/pinctrl-rockchip.c

··· 3795 3795 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3796 3796 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3797 3797 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3798 - 0, 3798 + IOMUX_WIDTH_2BIT, 3799 3799 IOMUX_WIDTH_3BIT, 3800 3800 0), 3801 3801 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",

drivers/pinctrl/pinctrl-single.c

··· 345 345 return -ENOTSUPP; 346 346 fselector = setting->func; 347 347 function = pinmux_generic_get_function(pctldev, fselector); 348 + if (!function) 349 + return -EINVAL; 348 350 *func = function->data; 349 351 if (!(*func)) { 350 352 dev_err(pcs->dev, "%s could not find function%i\n",

+19 -16

drivers/pinctrl/qcom/pinctrl-x1e80100.c

··· 1805 1805 [235] = PINGROUP(235, aon_cci, qdss_gpio, _, _, _, _, _, _, _), 1806 1806 [236] = PINGROUP(236, aon_cci, qdss_gpio, _, _, _, _, _, _, _), 1807 1807 [237] = PINGROUP(237, _, _, _, _, _, _, _, _, _), 1808 - [238] = UFS_RESET(ufs_reset, 0x1f9000), 1809 - [239] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1f2000, 14, 6), 1810 - [240] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1f2000, 11, 3), 1811 - [241] = SDC_QDSD_PINGROUP(sdc2_data, 0x1f2000, 9, 0), 1808 + [238] = UFS_RESET(ufs_reset, 0xf9000), 1809 + [239] = SDC_QDSD_PINGROUP(sdc2_clk, 0xf2000, 14, 6), 1810 + [240] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xf2000, 11, 3), 1811 + [241] = SDC_QDSD_PINGROUP(sdc2_data, 0xf2000, 9, 0), 1812 1812 }; 1813 1813 1814 1814 static const struct msm_gpio_wakeirq_map x1e80100_pdc_map[] = { 1815 1815 { 0, 72 }, { 2, 70 }, { 3, 71 }, { 6, 123 }, { 7, 67 }, { 11, 85 }, 1816 - { 15, 68 }, { 18, 122 }, { 19, 69 }, { 21, 158 }, { 23, 143 }, { 26, 129 }, 1817 - { 27, 144 }, { 28, 77 }, { 29, 78 }, { 30, 92 }, { 32, 145 }, { 33, 115 }, 1818 - { 34, 130 }, { 35, 146 }, { 36, 147 }, { 39, 80 }, { 43, 148 }, { 47, 149 }, 1819 - { 51, 79 }, { 53, 89 }, { 59, 87 }, { 64, 90 }, { 65, 106 }, { 66, 142 }, 1820 - { 67, 88 }, { 71, 91 }, { 75, 152 }, { 79, 153 }, { 80, 125 }, { 81, 128 }, 1821 - { 84, 137 }, { 85, 155 }, { 87, 156 }, { 91, 157 }, { 92, 138 }, { 94, 140 }, 1822 - { 95, 141 }, { 113, 84 }, { 121, 73 }, { 123, 74 }, { 129, 76 }, { 131, 82 }, 1823 - { 134, 83 }, { 141, 93 }, { 144, 94 }, { 147, 96 }, { 148, 97 }, { 150, 102 }, 1824 - { 151, 103 }, { 153, 104 }, { 156, 105 }, { 157, 107 }, { 163, 98 }, { 166, 112 }, 1825 - { 172, 99 }, { 181, 101 }, { 184, 116 }, { 193, 40 }, { 193, 117 }, { 196, 108 }, 1826 - { 203, 133 }, { 212, 120 }, { 213, 150 }, { 214, 121 }, { 215, 118 }, { 217, 109 }, 1827 - { 220, 110 }, { 221, 111 }, { 222, 124 }, { 224, 131 }, { 225, 132 }, 1816 + { 13, 86 }, { 15, 68 }, { 18, 122 }, { 19, 69 }, { 21, 158 }, { 23, 143 }, 1817 + { 24, 126 }, { 26, 129 }, { 27, 144 }, { 28, 77 }, { 29, 78 }, { 30, 92 }, 1818 + { 31, 159 }, { 32, 145 }, { 33, 115 }, { 34, 130 }, { 35, 146 }, { 36, 147 }, 1819 + { 38, 113 }, { 39, 80 }, { 43, 148 }, { 47, 149 }, { 51, 79 }, { 53, 89 }, 1820 + { 55, 81 }, { 59, 87 }, { 64, 90 }, { 65, 106 }, { 66, 142 }, { 67, 88 }, 1821 + { 68, 151 }, { 71, 91 }, { 75, 152 }, { 79, 153 }, { 80, 125 }, { 81, 128 }, 1822 + { 83, 154 }, { 84, 137 }, { 85, 155 }, { 87, 156 }, { 91, 157 }, { 92, 138 }, 1823 + { 93, 139 }, { 94, 140 }, { 95, 141 }, { 113, 84 }, { 121, 73 }, { 123, 74 }, 1824 + { 125, 75 }, { 129, 76 }, { 131, 82 }, { 134, 83 }, { 141, 93 }, { 144, 94 }, 1825 + { 145, 95 }, { 147, 96 }, { 148, 97 }, { 150, 102 }, { 151, 103 }, { 153, 104 }, 1826 + { 154, 100 }, { 156, 105 }, { 157, 107 }, { 163, 98 }, { 166, 112 }, { 172, 99 }, 1827 + { 175, 114 }, { 181, 101 }, { 184, 116 }, { 193, 117 }, { 196, 108 }, { 203, 133 }, 1828 + { 208, 134 }, { 212, 120 }, { 213, 150 }, { 214, 121 }, { 215, 118 }, { 217, 109 }, 1829 + { 219, 119 }, { 220, 110 }, { 221, 111 }, { 222, 124 }, { 224, 131 }, { 225, 132 }, 1830 + { 228, 135 }, { 230, 136 }, { 232, 162 }, 1828 1831 }; 1829 1832 1830 1833 static const struct msm_pinctrl_soc_data x1e80100_pinctrl = {

+2 -2

drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c

··· 793 793 case IRQ_TYPE_LEVEL_HIGH: 794 794 irq_type = 0; /* 0: level triggered */ 795 795 edge_both = 0; /* 0: ignored */ 796 - polarity = mask; /* 1: high level */ 796 + polarity = 0; /* 0: high level */ 797 797 break; 798 798 case IRQ_TYPE_LEVEL_LOW: 799 799 irq_type = 0; /* 0: level triggered */ 800 800 edge_both = 0; /* 0: ignored */ 801 - polarity = 0; /* 0: low level */ 801 + polarity = mask; /* 1: low level */ 802 802 break; 803 803 default: 804 804 return -EINVAL;