Revert "drm/nouveau: set DMA mask before creating the flush page"

This reverts commit ebe755605082eddff80eafe0c50915b1366ee98f.

Tested the latest kernel on my GB203 and this seems to break it somehow.

Nov 09 04:16:14 bighp kernel: nouveau 0000:02:00.0: gsp: GSP-FMC boot failed (mbox: 0x0000000b)
Nov 09 04:16:14 bighp kernel: nouveau 0000:02:00.0: gsp: init failed, -5
Nov 09 04:16:14 bighp kernel: nouveau 0000:02:00.0: init failed with -5
Nov 09 04:16:14 bighp kernel: nouveau: drm:00000000:00000080: init failed with -5
Nov 09 04:16:14 bighp kernel: nouveau 0000:02:00.0: drm: Device allocation failed: -5
Nov 09 04:16:14 bighp kernel: nouveau 0000:02:00.0: probe with driver nouveau failed with error -5

Not sure why, I went over the patch and thought it should have worked, but there must be some
32-bit problem maybe in the FMC boot path.

Signed-off-by: Dave Airlie <airlied@redhat.com>

Changed files
+12 -12
drivers
gpu
drm
nouveau
nvkm
engine
device
+12 -12
drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c
··· 1695 1695 *pdevice = &pdev->device; 1696 1696 pdev->pdev = pci_dev; 1697 1697 1698 - /* Set DMA mask based on capabilities reported by the MMU subdev. */ 1699 - if (pdev->device.mmu && !pdev->device.pci->agp.bridge) 1700 - bits = pdev->device.mmu->dma_bits; 1701 - else 1702 - bits = 32; 1703 - 1704 - ret = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(bits)); 1705 - if (ret && bits != 32) { 1706 - dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32)); 1707 - pdev->device.mmu->dma_bits = 32; 1708 - } 1709 - 1710 1698 ret = nvkm_device_ctor(&nvkm_device_pci_func, quirk, &pci_dev->dev, 1711 1699 pci_is_pcie(pci_dev) ? NVKM_DEVICE_PCIE : 1712 1700 pci_find_capability(pci_dev, PCI_CAP_ID_AGP) ? ··· 1707 1719 1708 1720 if (ret) 1709 1721 return ret; 1722 + 1723 + /* Set DMA mask based on capabilities reported by the MMU subdev. */ 1724 + if (pdev->device.mmu && !pdev->device.pci->agp.bridge) 1725 + bits = pdev->device.mmu->dma_bits; 1726 + else 1727 + bits = 32; 1728 + 1729 + ret = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(bits)); 1730 + if (ret && bits != 32) { 1731 + dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32)); 1732 + pdev->device.mmu->dma_bits = 32; 1733 + } 1710 1734 1711 1735 return 0; 1712 1736 }