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[PATCH] ARM: 2650/1: PXA27x sleep - workaround Errata 39 & 50 (Patch 2667)
Patch from Jeff Lackey
This patch updates arch/arm/mach-pxa/sleep.S to support
the PXA270 CPU. It works around Errata 39 & 50 from the
Intel(R) PXA27x Processor Family Specification Update.
Signed-off-by: Jeff Lackey
Signed-off-by: Russell King
authored by
Jeff Lackey
and committed by
Russell King
41130d37
eec99e34
+52
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+52
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arch/arm/mach-pxa/sleep.S
+52
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arch/arm/mach-pxa/sleep.S
···
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#include <asm/arch/pxa-regs.h>
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#ifdef CONFIG_PXA27x // workaround for Errata 50
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#define MDREFR_KDIV 0x200a4000 // all banks
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#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
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#endif
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.text
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/*
···
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ENTRY(pxa_cpu_suspend)
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#ifndef CONFIG_IWMMXT
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mra r2, r3, acc0
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#endif
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stmfd sp!, {r2 - r12, lr} @ save registers on stack
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@ get coprocessor registers
···
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@ prepare value for sleep mode
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mov r1, #3 @ sleep mode
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@ prepare to put SDRAM into self-refresh manually
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ldr r4, =MDREFR
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ldr r5, [r4]
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orr r5, r5, #MDREFR_SLFRSH
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@ prepare pointer to physical address 0 (virtual mapping in generic.c)
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mov r2, #UNCACHED_PHYS_0
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@ prepare SDRAM refresh settings
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ldr r4, =MDREFR
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ldr r5, [r4]
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@ enable SDRAM self-refresh mode
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orr r5, r5, #MDREFR_SLFRSH
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#ifdef CONFIG_PXA27x
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@ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
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ldr r6, =MDREFR_KDIV
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orr r5, r5, r6
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#endif
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#ifdef CONFIG_PXA25x
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@ Intel PXA255 Specification Update notes problems
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@ about suspending with PXBus operating above 133MHz
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@ (see Errata 31, GPIO output signals, ... unpredictable in sleep
···
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mov r0, #0
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mcr p14, 0, r0, c6, c0, 0
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orr r0, r0, #2 @ initiate change bit
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#endif
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#ifdef CONFIG_PXA27x
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@ Intel PXA270 Specification Update notes problems sleeping
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@ with core operating above 91 MHz
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@ (see Errata 50, ...processor does not exit from sleep...)
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ldr r6, =CCCR
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ldr r8, [r6] @ keep original value for resume
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ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value
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mov r0, #0x2 @ prepare value for CLKCFG
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#endif
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@ align execution to a cache line
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b 1f
···
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@ All needed values are now in registers.
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@ These last instructions should be in cache
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#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
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@ initiate the frequency change...
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str r7, [r6]
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mcr p14, 0, r0, c6, c0, 0
···
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@ restore the original cpu speed value for resume
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str r8, [r6]
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@ put SDRAM into self-refresh
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str r5, [r4]
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@ need 6 13-MHz cycles before changing PWRMODE
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@ just set frequency to 91-MHz... 6*91/13 = 42
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mov r0, #42
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10: subs r0, r0, #1
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bne 10b
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#endif
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@ Do not reorder...
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@ Intel PXA270 Specification Update notes problems performing
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@ external accesses after SDRAM is put in self-refresh mode
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@ (see Errata 39 ...hangs when entering self-refresh mode)
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@ force address lines low by reading at physical address 0
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ldr r3, [r2]
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@ put SDRAM into self-refresh
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str r5, [r4]
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@ enter sleep mode
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mcr p14, 0, r1, c7, c0, 0
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mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
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20: b 20b @ loop waiting for sleep
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···
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bl cpu_xscale_proc_init
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#endif
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ldmfd sp!, {r2, r3}
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#ifndef CONFIG_IWMMXT
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mar acc0, r2, r3
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#endif
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ldmfd sp!, {r4 - r12, pc} @ return to caller
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