tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ARM: entry: data abort: ensure r5 is preserved by abort functions

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Russell King 40f0b90a 108f6af0

+38 -43
+22 -26
arch/arm/mm/abort-lv4t.S
··· 7 7 * : r4 = aborted context pc 8 8 * : r5 = aborted context psr 9 9 * 10 - * Returns : r0 = address of abort 11 - * : r1 = FSR, bit 11 = write 12 - * : r2-r8 = corrupted 13 - * : r9 = preserved 14 - * : sp = pointer to registers 10 + * Returns : r4-r5, r10-r11, r13 preserved 15 11 * 16 12 * Purpose : obtain information about current aborted instruction. 17 13 * Note: we read user space. This means we might cause a data ··· 68 72 add r6, r6, r6, lsr #8 69 73 add r6, r6, r6, lsr #4 70 74 and r6, r6, #15 @ r6 = no. of registers to transfer. 71 - and r5, r8, #15 << 16 @ Extract 'n' from instruction 72 - ldr r7, [r2, r5, lsr #14] @ Get register 'Rn' 75 + and r9, r8, #15 << 16 @ Extract 'n' from instruction 76 + ldr r7, [r2, r9, lsr #14] @ Get register 'Rn' 73 77 tst r8, #1 << 23 @ Check U bit 74 78 subne r7, r7, r6, lsl #2 @ Undo increment 75 79 addeq r7, r7, r6, lsl #2 @ Undo decrement 76 - str r7, [r2, r5, lsr #14] @ Put register 'Rn' 80 + str r7, [r2, r9, lsr #14] @ Put register 'Rn' 77 81 b do_DataAbort 78 82 79 83 .data_arm_lateldrhpre: 80 84 tst r8, #1 << 21 @ Check writeback bit 81 85 beq do_DataAbort @ No writeback -> no fixup 82 86 .data_arm_lateldrhpost: 83 - and r5, r8, #0x00f @ get Rm / low nibble of immediate value 87 + and r9, r8, #0x00f @ get Rm / low nibble of immediate value 84 88 tst r8, #1 << 22 @ if (immediate offset) 85 89 andne r6, r8, #0xf00 @ { immediate high nibble 86 - orrne r6, r5, r6, lsr #4 @ combine nibbles } else 87 - ldreq r6, [r2, r5, lsl #2] @ { load Rm value } 90 + orrne r6, r9, r6, lsr #4 @ combine nibbles } else 91 + ldreq r6, [r2, r9, lsl #2] @ { load Rm value } 88 92 .data_arm_apply_r6_and_rn: 89 - and r5, r8, #15 << 16 @ Extract 'n' from instruction 90 - ldr r7, [r2, r5, lsr #14] @ Get register 'Rn' 93 + and r9, r8, #15 << 16 @ Extract 'n' from instruction 94 + ldr r7, [r2, r9, lsr #14] @ Get register 'Rn' 91 95 tst r8, #1 << 23 @ Check U bit 92 96 subne r7, r7, r6 @ Undo incrmenet 93 97 addeq r7, r7, r6 @ Undo decrement 94 - str r7, [r2, r5, lsr #14] @ Put register 'Rn' 98 + str r7, [r2, r9, lsr #14] @ Put register 'Rn' 95 99 b do_DataAbort 96 100 97 101 .data_arm_lateldrpreconst: ··· 100 104 .data_arm_lateldrpostconst: 101 105 movs r6, r8, lsl #20 @ Get offset 102 106 beq do_DataAbort @ zero -> no fixup 103 - and r5, r8, #15 << 16 @ Extract 'n' from instruction 104 - ldr r7, [r2, r5, lsr #14] @ Get register 'Rn' 107 + and r9, r8, #15 << 16 @ Extract 'n' from instruction 108 + ldr r7, [r2, r9, lsr #14] @ Get register 'Rn' 105 109 tst r8, #1 << 23 @ Check U bit 106 110 subne r7, r7, r6, lsr #20 @ Undo increment 107 111 addeq r7, r7, r6, lsr #20 @ Undo decrement 108 - str r7, [r2, r5, lsr #14] @ Put register 'Rn' 112 + str r7, [r2, r9, lsr #14] @ Put register 'Rn' 109 113 b do_DataAbort 110 114 111 115 .data_arm_lateldrprereg: ··· 114 118 .data_arm_lateldrpostreg: 115 119 and r7, r8, #15 @ Extract 'm' from instruction 116 120 ldr r6, [r2, r7, lsl #2] @ Get register 'Rm' 117 - mov r5, r8, lsr #7 @ get shift count 118 - ands r5, r5, #31 121 + mov r9, r8, lsr #7 @ get shift count 122 + ands r9, r9, #31 119 123 and r7, r8, #0x70 @ get shift type 120 124 orreq r7, r7, #8 @ shift count = 0 121 125 add pc, pc, r7 122 126 nop 123 127 124 - mov r6, r6, lsl r5 @ 0: LSL #!0 128 + mov r6, r6, lsl r9 @ 0: LSL #!0 125 129 b .data_arm_apply_r6_and_rn 126 130 b .data_arm_apply_r6_and_rn @ 1: LSL #0 127 131 nop ··· 129 133 nop 130 134 b .data_unknown @ 3: MUL? 131 135 nop 132 - mov r6, r6, lsr r5 @ 4: LSR #!0 136 + mov r6, r6, lsr r9 @ 4: LSR #!0 133 137 b .data_arm_apply_r6_and_rn 134 138 mov r6, r6, lsr #32 @ 5: LSR #32 135 139 b .data_arm_apply_r6_and_rn ··· 137 141 nop 138 142 b .data_unknown @ 7: MUL? 139 143 nop 140 - mov r6, r6, asr r5 @ 8: ASR #!0 144 + mov r6, r6, asr r9 @ 8: ASR #!0 141 145 b .data_arm_apply_r6_and_rn 142 146 mov r6, r6, asr #32 @ 9: ASR #32 143 147 b .data_arm_apply_r6_and_rn ··· 145 149 nop 146 150 b .data_unknown @ B: MUL? 147 151 nop 148 - mov r6, r6, ror r5 @ C: ROR #!0 152 + mov r6, r6, ror r9 @ C: ROR #!0 149 153 b .data_arm_apply_r6_and_rn 150 154 mov r6, r6, rrx @ D: RRX 151 155 b .data_arm_apply_r6_and_rn ··· 212 216 and r6, r6, #0x33 213 217 add r6, r6, r9, lsr #2 214 218 add r6, r6, r6, lsr #4 215 - and r5, r8, #7 << 8 216 - ldr r7, [r2, r5, lsr #6] 219 + and r9, r8, #7 << 8 220 + ldr r7, [r2, r9, lsr #6] 217 221 and r6, r6, #15 @ number of regs to transfer 218 222 sub r7, r7, r6, lsl #2 @ always decrement 219 - str r7, [r2, r5, lsr #6] 223 + str r7, [r2, r9, lsr #6] 220 224 b do_DataAbort
+16 -17
arch/arm/mm/proc-arm6_7.S
··· 35 35 * 36 36 * Purpose : obtain information about current aborted instruction 37 37 * 38 - * Returns : r0 = address of abort 39 - * : r1 = FSR 38 + * Returns : r4-r5, r10-r11, r13 preserved 40 39 */ 41 40 42 41 ENTRY(cpu_arm7_data_abort) ··· 94 95 add r6, r6, r6, lsr #8 95 96 add r6, r6, r6, lsr #4 96 97 and r6, r6, #15 @ r6 = no. of registers to transfer. 97 - and r5, r8, #15 << 16 @ Extract 'n' from instruction 98 - ldr r7, [r2, r5, lsr #14] @ Get register 'Rn' 98 + and r9, r8, #15 << 16 @ Extract 'n' from instruction 99 + ldr r7, [r2, r9, lsr #14] @ Get register 'Rn' 99 100 tst r8, #1 << 23 @ Check U bit 100 101 subne r7, r7, r6, lsl #2 @ Undo increment 101 102 addeq r7, r7, r6, lsl #2 @ Undo decrement 102 - str r7, [r2, r5, lsr #14] @ Put register 'Rn' 103 + str r7, [r2, r9, lsr #14] @ Put register 'Rn' 103 104 b do_DataAbort 104 105 105 106 .data_arm_apply_r6_and_rn: 106 - and r5, r8, #15 << 16 @ Extract 'n' from instruction 107 - ldr r7, [r2, r5, lsr #14] @ Get register 'Rn' 107 + and r9, r8, #15 << 16 @ Extract 'n' from instruction 108 + ldr r7, [r2, r9, lsr #14] @ Get register 'Rn' 108 109 tst r8, #1 << 23 @ Check U bit 109 110 subne r7, r7, r6 @ Undo incrmenet 110 111 addeq r7, r7, r6 @ Undo decrement 111 - str r7, [r2, r5, lsr #14] @ Put register 'Rn' 112 + str r7, [r2, r9, lsr #14] @ Put register 'Rn' 112 113 b do_DataAbort 113 114 114 115 .data_arm_lateldrpreconst: ··· 117 118 .data_arm_lateldrpostconst: 118 119 movs r6, r8, lsl #20 @ Get offset 119 120 beq do_DataAbort @ zero -> no fixup 120 - and r5, r8, #15 << 16 @ Extract 'n' from instruction 121 - ldr r7, [r2, r5, lsr #14] @ Get register 'Rn' 121 + and r9, r8, #15 << 16 @ Extract 'n' from instruction 122 + ldr r7, [r2, r9, lsr #14] @ Get register 'Rn' 122 123 tst r8, #1 << 23 @ Check U bit 123 124 subne r7, r7, r6, lsr #20 @ Undo increment 124 125 addeq r7, r7, r6, lsr #20 @ Undo decrement 125 - str r7, [r2, r5, lsr #14] @ Put register 'Rn' 126 + str r7, [r2, r9, lsr #14] @ Put register 'Rn' 126 127 b do_DataAbort 127 128 128 129 .data_arm_lateldrprereg: ··· 131 132 .data_arm_lateldrpostreg: 132 133 and r7, r8, #15 @ Extract 'm' from instruction 133 134 ldr r6, [r2, r7, lsl #2] @ Get register 'Rm' 134 - mov r5, r8, lsr #7 @ get shift count 135 - ands r5, r5, #31 135 + mov r9, r8, lsr #7 @ get shift count 136 + ands r9, r9, #31 136 137 and r7, r8, #0x70 @ get shift type 137 138 orreq r7, r7, #8 @ shift count = 0 138 139 add pc, pc, r7 139 140 nop 140 141 141 - mov r6, r6, lsl r5 @ 0: LSL #!0 142 + mov r6, r6, lsl r9 @ 0: LSL #!0 142 143 b .data_arm_apply_r6_and_rn 143 144 b .data_arm_apply_r6_and_rn @ 1: LSL #0 144 145 nop ··· 146 147 nop 147 148 b .data_unknown @ 3: MUL? 148 149 nop 149 - mov r6, r6, lsr r5 @ 4: LSR #!0 150 + mov r6, r6, lsr r9 @ 4: LSR #!0 150 151 b .data_arm_apply_r6_and_rn 151 152 mov r6, r6, lsr #32 @ 5: LSR #32 152 153 b .data_arm_apply_r6_and_rn ··· 154 155 nop 155 156 b .data_unknown @ 7: MUL? 156 157 nop 157 - mov r6, r6, asr r5 @ 8: ASR #!0 158 + mov r6, r6, asr r9 @ 8: ASR #!0 158 159 b .data_arm_apply_r6_and_rn 159 160 mov r6, r6, asr #32 @ 9: ASR #32 160 161 b .data_arm_apply_r6_and_rn ··· 162 163 nop 163 164 b .data_unknown @ B: MUL? 164 165 nop 165 - mov r6, r6, ror r5 @ C: ROR #!0 166 + mov r6, r6, ror r9 @ C: ROR #!0 166 167 b .data_arm_apply_r6_and_rn 167 168 mov r6, r6, rrx @ D: RRX 168 169 b .data_arm_apply_r6_and_rn