Merge branch '20231106-topic-sm8650-upstream-clocks-v3-5-761a6fadb4c0@linaro.org' into arm64-for-6.8

+1

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

··· 35 35 - qcom,sm8350-rpmh-clk 36 36 - qcom,sm8450-rpmh-clk 37 37 - qcom,sm8550-rpmh-clk 38 + - qcom,sm8650-rpmh-clk 38 39 39 40 clocks: 40 41 maxItems: 1

+2

Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml

··· 17 17 include/dt-bindings/clock/qcom,sm8450-gpucc.h 18 18 include/dt-bindings/clock/qcom,sm8550-gpucc.h 19 19 include/dt-bindings/reset/qcom,sm8450-gpucc.h 20 + include/dt-bindings/reset/qcom,sm8650-gpucc.h 20 21 21 22 properties: 22 23 compatible: 23 24 enum: 24 25 - qcom,sm8450-gpucc 25 26 - qcom,sm8550-gpucc 27 + - qcom,sm8650-gpucc 26 28 27 29 clocks: 28 30 items:

+6 -2

Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml

··· 13 13 Qualcomm TCSR clock control module provides the clocks, resets and 14 14 power domains on SM8550 15 15 16 - See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h 16 + See also: 17 + - include/dt-bindings/clock/qcom,sm8550-tcsr.h 18 + - include/dt-bindings/clock/qcom,sm8650-tcsr.h 17 19 18 20 properties: 19 21 compatible: 20 22 items: 21 - - const: qcom,sm8550-tcsr 23 + - enum: 24 + - qcom,sm8550-tcsr 25 + - qcom,sm8650-tcsr 22 26 - const: syscon 23 27 24 28 clocks:

+106

Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Display Clock & Reset Controller for SM8650 8 + 9 + maintainers: 10 + - Bjorn Andersson <andersson@kernel.org> 11 + - Neil Armstrong <neil.armstrong@linaro.org> 12 + 13 + description: | 14 + Qualcomm display clock control module provides the clocks, resets and power 15 + domains on SM8650. 16 + 17 + See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h 18 + 19 + properties: 20 + compatible: 21 + enum: 22 + - qcom,sm8650-dispcc 23 + 24 + clocks: 25 + items: 26 + - description: Board XO source 27 + - description: Board Always On XO source 28 + - description: Display's AHB clock 29 + - description: sleep clock 30 + - description: Byte clock from DSI PHY0 31 + - description: Pixel clock from DSI PHY0 32 + - description: Byte clock from DSI PHY1 33 + - description: Pixel clock from DSI PHY1 34 + - description: Link clock from DP PHY0 35 + - description: VCO DIV clock from DP PHY0 36 + - description: Link clock from DP PHY1 37 + - description: VCO DIV clock from DP PHY1 38 + - description: Link clock from DP PHY2 39 + - description: VCO DIV clock from DP PHY2 40 + - description: Link clock from DP PHY3 41 + - description: VCO DIV clock from DP PHY3 42 + 43 + '#clock-cells': 44 + const: 1 45 + 46 + '#reset-cells': 47 + const: 1 48 + 49 + '#power-domain-cells': 50 + const: 1 51 + 52 + reg: 53 + maxItems: 1 54 + 55 + power-domains: 56 + description: 57 + A phandle and PM domain specifier for the MMCX power domain. 58 + maxItems: 1 59 + 60 + required-opps: 61 + description: 62 + A phandle to an OPP node describing required MMCX performance point. 63 + maxItems: 1 64 + 65 + required: 66 + - compatible 67 + - reg 68 + - clocks 69 + - '#clock-cells' 70 + - '#reset-cells' 71 + - '#power-domain-cells' 72 + 73 + additionalProperties: false 74 + 75 + examples: 76 + - | 77 + #include <dt-bindings/clock/qcom,sm8650-gcc.h> 78 + #include <dt-bindings/clock/qcom,rpmh.h> 79 + #include <dt-bindings/power/qcom-rpmpd.h> 80 + #include <dt-bindings/power/qcom,rpmhpd.h> 81 + clock-controller@af00000 { 82 + compatible = "qcom,sm8650-dispcc"; 83 + reg = <0x0af00000 0x10000>; 84 + clocks = <&rpmhcc RPMH_CXO_CLK>, 85 + <&rpmhcc RPMH_CXO_CLK_A>, 86 + <&gcc GCC_DISP_AHB_CLK>, 87 + <&sleep_clk>, 88 + <&dsi0_phy 0>, 89 + <&dsi0_phy 1>, 90 + <&dsi1_phy 0>, 91 + <&dsi1_phy 1>, 92 + <&dp0_phy 0>, 93 + <&dp0_phy 1>, 94 + <&dp1_phy 0>, 95 + <&dp1_phy 1>, 96 + <&dp2_phy 0>, 97 + <&dp2_phy 1>, 98 + <&dp3_phy 0>, 99 + <&dp3_phy 1>; 100 + #clock-cells = <1>; 101 + #reset-cells = <1>; 102 + #power-domain-cells = <1>; 103 + power-domains = <&rpmhpd RPMHPD_MMCX>; 104 + required-opps = <&rpmhpd_opp_low_svs>; 105 + }; 106 + ...

+65

Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Global Clock & Reset Controller on SM8650 8 + 9 + maintainers: 10 + - Bjorn Andersson <andersson@kernel.org> 11 + 12 + description: | 13 + Qualcomm global clock control module provides the clocks, resets and power 14 + domains on SM8650 15 + 16 + See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h 17 + 18 + properties: 19 + compatible: 20 + const: qcom,sm8650-gcc 21 + 22 + clocks: 23 + items: 24 + - description: Board XO source 25 + - description: Board Always On XO source 26 + - description: Sleep clock source 27 + - description: PCIE 0 Pipe clock source 28 + - description: PCIE 1 Pipe clock source 29 + - description: PCIE 1 Phy Auxiliary clock source 30 + - description: UFS Phy Rx symbol 0 clock source 31 + - description: UFS Phy Rx symbol 1 clock source 32 + - description: UFS Phy Tx symbol 0 clock source 33 + - description: USB3 Phy wrapper pipe clock source 34 + 35 + required: 36 + - compatible 37 + - clocks 38 + 39 + allOf: 40 + - $ref: qcom,gcc.yaml# 41 + 42 + unevaluatedProperties: false 43 + 44 + examples: 45 + - | 46 + #include <dt-bindings/clock/qcom,rpmh.h> 47 + clock-controller@100000 { 48 + compatible = "qcom,sm8650-gcc"; 49 + reg = <0x00100000 0x001f4200>; 50 + clocks = <&rpmhcc RPMH_CXO_CLK>, 51 + <&rpmhcc RPMH_CXO_CLK_A>, 52 + <&sleep_clk>, 53 + <&pcie0_phy>, 54 + <&pcie1_phy>, 55 + <&pcie_1_phy_aux_clk>, 56 + <&ufs_mem_phy 0>, 57 + <&ufs_mem_phy 1>, 58 + <&ufs_mem_phy 2>, 59 + <&usb_1_qmpphy>; 60 + #clock-cells = <1>; 61 + #reset-cells = <1>; 62 + #power-domain-cells = <1>; 63 + }; 64 + 65 + ...

+102

include/dt-bindings/clock/qcom,sm8650-dispcc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved 4 + * Copyright (c) 2023, Linaro Ltd. 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H 8 + #define _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H 9 + 10 + /* DISP_CC clocks */ 11 + #define DISP_CC_MDSS_ACCU_CLK 0 12 + #define DISP_CC_MDSS_AHB1_CLK 1 13 + #define DISP_CC_MDSS_AHB_CLK 2 14 + #define DISP_CC_MDSS_AHB_CLK_SRC 3 15 + #define DISP_CC_MDSS_BYTE0_CLK 4 16 + #define DISP_CC_MDSS_BYTE0_CLK_SRC 5 17 + #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 18 + #define DISP_CC_MDSS_BYTE0_INTF_CLK 7 19 + #define DISP_CC_MDSS_BYTE1_CLK 8 20 + #define DISP_CC_MDSS_BYTE1_CLK_SRC 9 21 + #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10 22 + #define DISP_CC_MDSS_BYTE1_INTF_CLK 11 23 + #define DISP_CC_MDSS_DPTX0_AUX_CLK 12 24 + #define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13 25 + #define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14 26 + #define DISP_CC_MDSS_DPTX0_LINK_CLK 15 27 + #define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16 28 + #define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17 29 + #define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18 30 + #define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19 31 + #define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20 32 + #define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21 33 + #define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22 34 + #define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23 35 + #define DISP_CC_MDSS_DPTX1_AUX_CLK 24 36 + #define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25 37 + #define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26 38 + #define DISP_CC_MDSS_DPTX1_LINK_CLK 27 39 + #define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28 40 + #define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29 41 + #define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30 42 + #define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31 43 + #define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32 44 + #define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33 45 + #define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34 46 + #define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35 47 + #define DISP_CC_MDSS_DPTX2_AUX_CLK 36 48 + #define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37 49 + #define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38 50 + #define DISP_CC_MDSS_DPTX2_LINK_CLK 39 51 + #define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40 52 + #define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41 53 + #define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42 54 + #define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43 55 + #define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44 56 + #define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45 57 + #define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46 58 + #define DISP_CC_MDSS_DPTX3_AUX_CLK 47 59 + #define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48 60 + #define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49 61 + #define DISP_CC_MDSS_DPTX3_LINK_CLK 50 62 + #define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51 63 + #define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52 64 + #define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53 65 + #define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54 66 + #define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55 67 + #define DISP_CC_MDSS_ESC0_CLK 56 68 + #define DISP_CC_MDSS_ESC0_CLK_SRC 57 69 + #define DISP_CC_MDSS_ESC1_CLK 58 70 + #define DISP_CC_MDSS_ESC1_CLK_SRC 59 71 + #define DISP_CC_MDSS_MDP1_CLK 60 72 + #define DISP_CC_MDSS_MDP_CLK 61 73 + #define DISP_CC_MDSS_MDP_CLK_SRC 62 74 + #define DISP_CC_MDSS_MDP_LUT1_CLK 63 75 + #define DISP_CC_MDSS_MDP_LUT_CLK 64 76 + #define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65 77 + #define DISP_CC_MDSS_PCLK0_CLK 66 78 + #define DISP_CC_MDSS_PCLK0_CLK_SRC 67 79 + #define DISP_CC_MDSS_PCLK1_CLK 68 80 + #define DISP_CC_MDSS_PCLK1_CLK_SRC 69 81 + #define DISP_CC_MDSS_RSCC_AHB_CLK 70 82 + #define DISP_CC_MDSS_RSCC_VSYNC_CLK 71 83 + #define DISP_CC_MDSS_VSYNC1_CLK 72 84 + #define DISP_CC_MDSS_VSYNC_CLK 73 85 + #define DISP_CC_MDSS_VSYNC_CLK_SRC 74 86 + #define DISP_CC_PLL0 75 87 + #define DISP_CC_PLL1 76 88 + #define DISP_CC_SLEEP_CLK 77 89 + #define DISP_CC_SLEEP_CLK_SRC 78 90 + #define DISP_CC_XO_CLK 79 91 + #define DISP_CC_XO_CLK_SRC 80 92 + 93 + /* DISP_CC resets */ 94 + #define DISP_CC_MDSS_CORE_BCR 0 95 + #define DISP_CC_MDSS_CORE_INT2_BCR 1 96 + #define DISP_CC_MDSS_RSCC_BCR 2 97 + 98 + /* DISP_CC GDSCR */ 99 + #define MDSS_GDSC 0 100 + #define MDSS_INT2_GDSC 1 101 + 102 + #endif

+254

include/dt-bindings/clock/qcom,sm8650-gcc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 + * Copyright (c) 2023, Linaro Limited 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H 8 + #define _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H 9 + 10 + /* GCC clocks */ 11 + #define GCC_AGGRE_NOC_PCIE_AXI_CLK 0 12 + #define GCC_AGGRE_UFS_PHY_AXI_CLK 1 13 + #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2 14 + #define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 15 + #define GCC_BOOT_ROM_AHB_CLK 4 16 + #define GCC_CAMERA_AHB_CLK 5 17 + #define GCC_CAMERA_HF_AXI_CLK 6 18 + #define GCC_CAMERA_SF_AXI_CLK 7 19 + #define GCC_CAMERA_XO_CLK 8 20 + #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9 21 + #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10 22 + #define GCC_CNOC_PCIE_SF_AXI_CLK 11 23 + #define GCC_DDRSS_GPU_AXI_CLK 12 24 + #define GCC_DDRSS_PCIE_SF_QTB_CLK 13 25 + #define GCC_DISP_AHB_CLK 14 26 + #define GCC_DISP_HF_AXI_CLK 15 27 + #define GCC_DISP_XO_CLK 16 28 + #define GCC_GP1_CLK 17 29 + #define GCC_GP1_CLK_SRC 18 30 + #define GCC_GP2_CLK 19 31 + #define GCC_GP2_CLK_SRC 20 32 + #define GCC_GP3_CLK 21 33 + #define GCC_GP3_CLK_SRC 22 34 + #define GCC_GPLL0 23 35 + #define GCC_GPLL0_OUT_EVEN 24 36 + #define GCC_GPLL1 25 37 + #define GCC_GPLL3 26 38 + #define GCC_GPLL4 27 39 + #define GCC_GPLL6 28 40 + #define GCC_GPLL7 29 41 + #define GCC_GPLL9 30 42 + #define GCC_GPU_CFG_AHB_CLK 31 43 + #define GCC_GPU_GPLL0_CLK_SRC 32 44 + #define GCC_GPU_GPLL0_DIV_CLK_SRC 33 45 + #define GCC_GPU_MEMNOC_GFX_CLK 34 46 + #define GCC_GPU_SNOC_DVM_GFX_CLK 35 47 + #define GCC_PCIE_0_AUX_CLK 36 48 + #define GCC_PCIE_0_AUX_CLK_SRC 37 49 + #define GCC_PCIE_0_CFG_AHB_CLK 38 50 + #define GCC_PCIE_0_MSTR_AXI_CLK 39 51 + #define GCC_PCIE_0_PHY_RCHNG_CLK 40 52 + #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 41 53 + #define GCC_PCIE_0_PIPE_CLK 42 54 + #define GCC_PCIE_0_PIPE_CLK_SRC 43 55 + #define GCC_PCIE_0_SLV_AXI_CLK 44 56 + #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 57 + #define GCC_PCIE_1_AUX_CLK 46 58 + #define GCC_PCIE_1_AUX_CLK_SRC 47 59 + #define GCC_PCIE_1_CFG_AHB_CLK 48 60 + #define GCC_PCIE_1_MSTR_AXI_CLK 49 61 + #define GCC_PCIE_1_PHY_AUX_CLK 50 62 + #define GCC_PCIE_1_PHY_AUX_CLK_SRC 51 63 + #define GCC_PCIE_1_PHY_RCHNG_CLK 52 64 + #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 53 65 + #define GCC_PCIE_1_PIPE_CLK 54 66 + #define GCC_PCIE_1_PIPE_CLK_SRC 55 67 + #define GCC_PCIE_1_SLV_AXI_CLK 56 68 + #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 57 69 + #define GCC_PDM2_CLK 58 70 + #define GCC_PDM2_CLK_SRC 59 71 + #define GCC_PDM_AHB_CLK 60 72 + #define GCC_PDM_XO4_CLK 61 73 + #define GCC_QMIP_CAMERA_NRT_AHB_CLK 62 74 + #define GCC_QMIP_CAMERA_RT_AHB_CLK 63 75 + #define GCC_QMIP_DISP_AHB_CLK 64 76 + #define GCC_QMIP_GPU_AHB_CLK 65 77 + #define GCC_QMIP_PCIE_AHB_CLK 66 78 + #define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 67 79 + #define GCC_QMIP_VIDEO_CVP_AHB_CLK 68 80 + #define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 69 81 + #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 70 82 + #define GCC_QUPV3_I2C_CORE_CLK 71 83 + #define GCC_QUPV3_I2C_S0_CLK 72 84 + #define GCC_QUPV3_I2C_S0_CLK_SRC 73 85 + #define GCC_QUPV3_I2C_S1_CLK 74 86 + #define GCC_QUPV3_I2C_S1_CLK_SRC 75 87 + #define GCC_QUPV3_I2C_S2_CLK 76 88 + #define GCC_QUPV3_I2C_S2_CLK_SRC 77 89 + #define GCC_QUPV3_I2C_S3_CLK 78 90 + #define GCC_QUPV3_I2C_S3_CLK_SRC 79 91 + #define GCC_QUPV3_I2C_S4_CLK 80 92 + #define GCC_QUPV3_I2C_S4_CLK_SRC 81 93 + #define GCC_QUPV3_I2C_S5_CLK 82 94 + #define GCC_QUPV3_I2C_S5_CLK_SRC 83 95 + #define GCC_QUPV3_I2C_S6_CLK 84 96 + #define GCC_QUPV3_I2C_S6_CLK_SRC 85 97 + #define GCC_QUPV3_I2C_S7_CLK 86 98 + #define GCC_QUPV3_I2C_S7_CLK_SRC 87 99 + #define GCC_QUPV3_I2C_S8_CLK 88 100 + #define GCC_QUPV3_I2C_S8_CLK_SRC 89 101 + #define GCC_QUPV3_I2C_S9_CLK 90 102 + #define GCC_QUPV3_I2C_S9_CLK_SRC 91 103 + #define GCC_QUPV3_I2C_S_AHB_CLK 92 104 + #define GCC_QUPV3_WRAP1_CORE_2X_CLK 93 105 + #define GCC_QUPV3_WRAP1_CORE_CLK 94 106 + #define GCC_QUPV3_WRAP1_QSPI_REF_CLK 95 107 + #define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 96 108 + #define GCC_QUPV3_WRAP1_S0_CLK 97 109 + #define GCC_QUPV3_WRAP1_S0_CLK_SRC 98 110 + #define GCC_QUPV3_WRAP1_S1_CLK 99 111 + #define GCC_QUPV3_WRAP1_S1_CLK_SRC 100 112 + #define GCC_QUPV3_WRAP1_S2_CLK 101 113 + #define GCC_QUPV3_WRAP1_S2_CLK_SRC 102 114 + #define GCC_QUPV3_WRAP1_S3_CLK 103 115 + #define GCC_QUPV3_WRAP1_S3_CLK_SRC 104 116 + #define GCC_QUPV3_WRAP1_S4_CLK 105 117 + #define GCC_QUPV3_WRAP1_S4_CLK_SRC 106 118 + #define GCC_QUPV3_WRAP1_S5_CLK 107 119 + #define GCC_QUPV3_WRAP1_S5_CLK_SRC 108 120 + #define GCC_QUPV3_WRAP1_S6_CLK 109 121 + #define GCC_QUPV3_WRAP1_S6_CLK_SRC 110 122 + #define GCC_QUPV3_WRAP1_S7_CLK 111 123 + #define GCC_QUPV3_WRAP1_S7_CLK_SRC 112 124 + #define GCC_QUPV3_WRAP2_CORE_2X_CLK 113 125 + #define GCC_QUPV3_WRAP2_CORE_CLK 114 126 + #define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 115 127 + #define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 116 128 + #define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 117 129 + #define GCC_QUPV3_WRAP2_S0_CLK 118 130 + #define GCC_QUPV3_WRAP2_S0_CLK_SRC 119 131 + #define GCC_QUPV3_WRAP2_S1_CLK 120 132 + #define GCC_QUPV3_WRAP2_S1_CLK_SRC 121 133 + #define GCC_QUPV3_WRAP2_S2_CLK 122 134 + #define GCC_QUPV3_WRAP2_S2_CLK_SRC 123 135 + #define GCC_QUPV3_WRAP2_S3_CLK 124 136 + #define GCC_QUPV3_WRAP2_S3_CLK_SRC 125 137 + #define GCC_QUPV3_WRAP2_S4_CLK 126 138 + #define GCC_QUPV3_WRAP2_S4_CLK_SRC 127 139 + #define GCC_QUPV3_WRAP2_S5_CLK 128 140 + #define GCC_QUPV3_WRAP2_S5_CLK_SRC 129 141 + #define GCC_QUPV3_WRAP2_S6_CLK 130 142 + #define GCC_QUPV3_WRAP2_S6_CLK_SRC 131 143 + #define GCC_QUPV3_WRAP2_S7_CLK 132 144 + #define GCC_QUPV3_WRAP2_S7_CLK_SRC 133 145 + #define GCC_QUPV3_WRAP3_CORE_2X_CLK 134 146 + #define GCC_QUPV3_WRAP3_CORE_CLK 135 147 + #define GCC_QUPV3_WRAP3_QSPI_REF_CLK 136 148 + #define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 137 149 + #define GCC_QUPV3_WRAP3_S0_CLK 138 150 + #define GCC_QUPV3_WRAP3_S0_CLK_SRC 139 151 + #define GCC_QUPV3_WRAP_1_M_AHB_CLK 140 152 + #define GCC_QUPV3_WRAP_1_S_AHB_CLK 141 153 + #define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 142 154 + #define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 143 155 + #define GCC_QUPV3_WRAP_2_M_AHB_CLK 144 156 + #define GCC_QUPV3_WRAP_2_S_AHB_CLK 145 157 + #define GCC_QUPV3_WRAP_3_M_AHB_CLK 146 158 + #define GCC_QUPV3_WRAP_3_S_AHB_CLK 147 159 + #define GCC_SDCC2_AHB_CLK 148 160 + #define GCC_SDCC2_APPS_CLK 149 161 + #define GCC_SDCC2_APPS_CLK_SRC 150 162 + #define GCC_SDCC4_AHB_CLK 151 163 + #define GCC_SDCC4_APPS_CLK 152 164 + #define GCC_SDCC4_APPS_CLK_SRC 153 165 + #define GCC_UFS_PHY_AHB_CLK 154 166 + #define GCC_UFS_PHY_AXI_CLK 155 167 + #define GCC_UFS_PHY_AXI_CLK_SRC 156 168 + #define GCC_UFS_PHY_AXI_HW_CTL_CLK 157 169 + #define GCC_UFS_PHY_ICE_CORE_CLK 158 170 + #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 159 171 + #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 160 172 + #define GCC_UFS_PHY_PHY_AUX_CLK 161 173 + #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 162 174 + #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 163 175 + #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164 176 + #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 165 177 + #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 166 178 + #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 167 179 + #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168 180 + #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 169 181 + #define GCC_UFS_PHY_UNIPRO_CORE_CLK 170 182 + #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 171 183 + #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 172 184 + #define GCC_USB30_PRIM_MASTER_CLK 173 185 + #define GCC_USB30_PRIM_MASTER_CLK_SRC 174 186 + #define GCC_USB30_PRIM_MOCK_UTMI_CLK 175 187 + #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176 188 + #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177 189 + #define GCC_USB30_PRIM_SLEEP_CLK 178 190 + #define GCC_USB3_PRIM_PHY_AUX_CLK 179 191 + #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 180 192 + #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 181 193 + #define GCC_USB3_PRIM_PHY_PIPE_CLK 182 194 + #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 183 195 + #define GCC_VIDEO_AHB_CLK 184 196 + #define GCC_VIDEO_AXI0_CLK 185 197 + #define GCC_VIDEO_AXI1_CLK 186 198 + #define GCC_VIDEO_XO_CLK 187 199 + #define GCC_GPLL0_AO 188 200 + #define GCC_GPLL0_OUT_EVEN_AO 189 201 + #define GCC_GPLL1_AO 190 202 + #define GCC_GPLL3_AO 191 203 + #define GCC_GPLL4_AO 192 204 + #define GCC_GPLL6_AO 193 205 + 206 + /* GCC resets */ 207 + #define GCC_CAMERA_BCR 0 208 + #define GCC_DISPLAY_BCR 1 209 + #define GCC_GPU_BCR 2 210 + #define GCC_PCIE_0_BCR 3 211 + #define GCC_PCIE_0_LINK_DOWN_BCR 4 212 + #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 213 + #define GCC_PCIE_0_PHY_BCR 6 214 + #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 215 + #define GCC_PCIE_1_BCR 8 216 + #define GCC_PCIE_1_LINK_DOWN_BCR 9 217 + #define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 218 + #define GCC_PCIE_1_PHY_BCR 11 219 + #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 220 + #define GCC_PCIE_PHY_BCR 13 221 + #define GCC_PCIE_PHY_CFG_AHB_BCR 14 222 + #define GCC_PCIE_PHY_COM_BCR 15 223 + #define GCC_PDM_BCR 16 224 + #define GCC_QUPV3_WRAPPER_1_BCR 17 225 + #define GCC_QUPV3_WRAPPER_2_BCR 18 226 + #define GCC_QUPV3_WRAPPER_3_BCR 19 227 + #define GCC_QUPV3_WRAPPER_I2C_BCR 20 228 + #define GCC_QUSB2PHY_PRIM_BCR 21 229 + #define GCC_QUSB2PHY_SEC_BCR 22 230 + #define GCC_SDCC2_BCR 23 231 + #define GCC_SDCC4_BCR 24 232 + #define GCC_UFS_PHY_BCR 25 233 + #define GCC_USB30_PRIM_BCR 26 234 + #define GCC_USB3_DP_PHY_PRIM_BCR 27 235 + #define GCC_USB3_DP_PHY_SEC_BCR 28 236 + #define GCC_USB3_PHY_PRIM_BCR 29 237 + #define GCC_USB3_PHY_SEC_BCR 30 238 + #define GCC_USB3PHY_PHY_PRIM_BCR 31 239 + #define GCC_USB3PHY_PHY_SEC_BCR 32 240 + #define GCC_VIDEO_AXI0_CLK_ARES 33 241 + #define GCC_VIDEO_AXI1_CLK_ARES 34 242 + #define GCC_VIDEO_BCR 35 243 + 244 + /* GCC power domains */ 245 + #define PCIE_0_GDSC 0 246 + #define PCIE_0_PHY_GDSC 1 247 + #define PCIE_1_GDSC 2 248 + #define PCIE_1_PHY_GDSC 3 249 + #define UFS_PHY_GDSC 4 250 + #define UFS_MEM_PHY_GDSC 5 251 + #define USB30_PRIM_GDSC 6 252 + #define USB3_PHY_GDSC 7 253 + 254 + #endif

+43

include/dt-bindings/clock/qcom,sm8650-gpucc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved 4 + * Copyright (c) 2023, Linaro Limited 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8650_H 8 + #define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8650_H 9 + 10 + /* GPU_CC clocks */ 11 + #define GPU_CC_AHB_CLK 0 12 + #define GPU_CC_CRC_AHB_CLK 1 13 + #define GPU_CC_CX_ACCU_SHIFT_CLK 2 14 + #define GPU_CC_CX_FF_CLK 3 15 + #define GPU_CC_CX_GMU_CLK 4 16 + #define GPU_CC_CXO_AON_CLK 5 17 + #define GPU_CC_CXO_CLK 6 18 + #define GPU_CC_DEMET_CLK 7 19 + #define GPU_CC_DPM_CLK 8 20 + #define GPU_CC_FF_CLK_SRC 9 21 + #define GPU_CC_FREQ_MEASURE_CLK 10 22 + #define GPU_CC_GMU_CLK_SRC 11 23 + #define GPU_CC_GX_ACCU_SHIFT_CLK 12 24 + #define GPU_CC_GX_FF_CLK 13 25 + #define GPU_CC_GX_GFX3D_CLK 14 26 + #define GPU_CC_GX_GFX3D_RDVM_CLK 15 27 + #define GPU_CC_GX_GMU_CLK 16 28 + #define GPU_CC_GX_VSENSE_CLK 17 29 + #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18 30 + #define GPU_CC_HUB_AON_CLK 19 31 + #define GPU_CC_HUB_CLK_SRC 20 32 + #define GPU_CC_HUB_CX_INT_CLK 21 33 + #define GPU_CC_HUB_DIV_CLK_SRC 22 34 + #define GPU_CC_MEMNOC_GFX_CLK 23 35 + #define GPU_CC_PLL0 24 36 + #define GPU_CC_PLL1 25 37 + #define GPU_CC_SLEEP_CLK 26 38 + 39 + /* GDSCs */ 40 + #define GPU_GX_GDSC 0 41 + #define GPU_CX_GDSC 1 42 + 43 + #endif

+18

include/dt-bindings/clock/qcom,sm8650-tcsr.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 + * Copyright (c) 2023, Linaro Limited 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8650_H 8 + #define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8650_H 9 + 10 + /* TCSR CC clocks */ 11 + #define TCSR_PCIE_0_CLKREF_EN 0 12 + #define TCSR_PCIE_1_CLKREF_EN 1 13 + #define TCSR_UFS_CLKREF_EN 2 14 + #define TCSR_UFS_PAD_CLKREF_EN 3 15 + #define TCSR_USB2_CLKREF_EN 4 16 + #define TCSR_USB3_CLKREF_EN 5 17 + 18 + #endif

+20

include/dt-bindings/reset/qcom,sm8650-gpucc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 + * Copyright (c) 2023, Linaro Limited 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8650_H 8 + #define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8650_H 9 + 10 + #define GPUCC_GPU_CC_ACD_BCR 0 11 + #define GPUCC_GPU_CC_CX_BCR 1 12 + #define GPUCC_GPU_CC_FAST_HUB_BCR 2 13 + #define GPUCC_GPU_CC_FF_BCR 3 14 + #define GPUCC_GPU_CC_GFX3D_AON_BCR 4 15 + #define GPUCC_GPU_CC_GMU_BCR 5 16 + #define GPUCC_GPU_CC_GX_BCR 6 17 + #define GPUCC_GPU_CC_XO_BCR 7 18 + #define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8 19 + 20 + #endif