b43; N-PHY: write most of the missing code for revs 7+

+1 -1

drivers/net/wireless/b43/main.c

··· 4360 4360 #endif 4361 4361 #ifdef CONFIG_B43_PHY_N 4362 4362 case B43_PHYTYPE_N: 4363 - if (phy_rev > 9) 4363 + if (phy_rev >= 19) 4364 4364 unsupported = 1; 4365 4365 break; 4366 4366 #endif

+268 -38

drivers/net/wireless/b43/phy_n.c

··· 36 36 #include "main.h" 37 37 38 38 struct nphy_txgains { 39 + u16 tx_lpf[2]; 39 40 u16 txgm[2]; 40 41 u16 pga[2]; 41 42 u16 pad[2]; ··· 44 43 }; 45 44 46 45 struct nphy_iqcal_params { 46 + u16 tx_lpf; 47 47 u16 txgm; 48 48 u16 pga; 49 49 u16 pad; ··· 69 67 B43_RFSEQ_UPDATE_GAINH, 70 68 B43_RFSEQ_UPDATE_GAINL, 71 69 B43_RFSEQ_UPDATE_GAINU, 70 + }; 71 + 72 + enum n_rf_ctl_over_cmd { 73 + N_RF_CTL_OVER_CMD_RXRF_PU = 0, 74 + N_RF_CTL_OVER_CMD_RX_PU = 1, 75 + N_RF_CTL_OVER_CMD_TX_PU = 2, 76 + N_RF_CTL_OVER_CMD_RX_GAIN = 3, 77 + N_RF_CTL_OVER_CMD_TX_GAIN = 4, 72 78 }; 73 79 74 80 enum n_intc_override { ··· 201 191 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift)); 202 192 } 203 193 } 194 + } 195 + } 196 + 197 + /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverideOneToMany */ 198 + static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev *dev, 199 + enum n_rf_ctl_over_cmd cmd, 200 + u16 value, u8 core, bool off) 201 + { 202 + struct b43_phy *phy = &dev->phy; 203 + u16 tmp; 204 + 205 + B43_WARN_ON(phy->rev < 7); 206 + 207 + switch (cmd) { 208 + case N_RF_CTL_OVER_CMD_RXRF_PU: 209 + b43_nphy_rf_ctl_override_rev7(dev, 0x20, value, core, off, 1); 210 + b43_nphy_rf_ctl_override_rev7(dev, 0x10, value, core, off, 1); 211 + b43_nphy_rf_ctl_override_rev7(dev, 0x08, value, core, off, 1); 212 + break; 213 + case N_RF_CTL_OVER_CMD_RX_PU: 214 + b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 1); 215 + b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); 216 + b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1); 217 + b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2); 218 + b43_nphy_rf_ctl_override_rev7(dev, 0x0800, value, core, off, 1); 219 + break; 220 + case N_RF_CTL_OVER_CMD_TX_PU: 221 + b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0); 222 + b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); 223 + b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2); 224 + b43_nphy_rf_ctl_override_rev7(dev, 0x0800, value, core, off, 1); 225 + break; 226 + case N_RF_CTL_OVER_CMD_RX_GAIN: 227 + tmp = value & 0xFF; 228 + b43_nphy_rf_ctl_override_rev7(dev, 0x0800, tmp, core, off, 0); 229 + tmp = value >> 8; 230 + b43_nphy_rf_ctl_override_rev7(dev, 0x6000, tmp, core, off, 0); 231 + break; 232 + case N_RF_CTL_OVER_CMD_TX_GAIN: 233 + tmp = value & 0x7FFF; 234 + b43_nphy_rf_ctl_override_rev7(dev, 0x1000, tmp, core, off, 0); 235 + tmp = value >> 14; 236 + b43_nphy_rf_ctl_override_rev7(dev, 0x4000, tmp, core, off, 0); 237 + break; 204 238 } 205 239 } 206 240 ··· 572 518 b43_nphy_write_clip_detection(dev, nphy->clip_state); 573 519 } 574 520 } 521 + } 522 + 523 + /* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */ 524 + static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset) 525 + { 526 + if (!offset) 527 + offset = b43_is_40mhz(dev) ? 0x159 : 0x154; 528 + return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7; 575 529 } 576 530 577 531 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */ ··· 1472 1410 b43_nphy_stay_in_carrier_search(dev, true); 1473 1411 1474 1412 if (phy->rev >= 7) { 1475 - /* TODO */ 1413 + bool lpf_bw3, lpf_bw4; 1414 + 1415 + lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80; 1416 + lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80; 1417 + 1418 + if (lpf_bw3 || lpf_bw4) { 1419 + /* TODO */ 1420 + } else { 1421 + u16 value = b43_nphy_read_lpf_ctl(dev, 0); 1422 + if (phy->rev >= 19) 1423 + b43_nphy_rf_ctl_override_rev19(dev, 0x80, value, 1424 + 0, false, 1); 1425 + else 1426 + b43_nphy_rf_ctl_override_rev7(dev, 0x80, value, 1427 + 0, false, 1); 1428 + nphy->lpf_bw_overrode_for_sample_play = true; 1429 + } 1476 1430 } 1477 1431 1478 1432 if ((nphy->bb_mult_save & 0x80000000) == 0) { ··· 1935 1857 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER, 1936 1858 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2, 1937 1859 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER, 1938 - 0x342, 0x343, 0x346, 0x347, 1860 + B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4, 1861 + B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6, 1939 1862 0x2ff, 1940 1863 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1, 1941 1864 B43_NPHY_RFCTL_CMD, 1942 1865 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2, 1943 - 0x340, 0x341, 0x344, 0x345, 1866 + B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4, 1867 + B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6, 1944 1868 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2 1945 1869 }; 1946 1870 u16 *regs_to_store; ··· 1989 1909 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7); 1990 1910 1991 1911 if (dev->phy.rev >= 7) { 1992 - /* TODO */ 1912 + b43_nphy_rf_ctl_override_one_to_many(dev, 1913 + N_RF_CTL_OVER_CMD_RXRF_PU, 1914 + 0, 0, false); 1915 + b43_nphy_rf_ctl_override_one_to_many(dev, 1916 + N_RF_CTL_OVER_CMD_RX_PU, 1917 + 1, 0, false); 1918 + b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0); 1919 + b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0); 1993 1920 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1921 + b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false, 1922 + 0); 1923 + b43_nphy_rf_ctl_override_rev7(dev, 0x10, 1, 0, false, 1924 + 0); 1994 1925 } else { 1926 + b43_nphy_rf_ctl_override_rev7(dev, 0x10, 0, 0, false, 1927 + 0); 1928 + b43_nphy_rf_ctl_override_rev7(dev, 0x20, 1, 0, false, 1929 + 0); 1995 1930 } 1996 1931 } else { 1997 1932 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false); ··· 2035 1940 /* Grab RSSI results for every possible VCM */ 2036 1941 for (vcm = 0; vcm < 8; vcm++) { 2037 1942 if (dev->phy.rev >= 7) 2038 - ; 1943 + b43_radio_maskset(dev, 1944 + core ? R2057_NB_MASTER_CORE1 : 1945 + R2057_NB_MASTER_CORE0, 1946 + ~R2057_VCM_MASK, vcm); 2039 1947 else 2040 1948 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 2041 1949 0xE3, vcm << 2); ··· 2069 1971 2070 1972 /* Select the best VCM */ 2071 1973 if (dev->phy.rev >= 7) 2072 - ; 1974 + b43_radio_maskset(dev, 1975 + core ? R2057_NB_MASTER_CORE1 : 1976 + R2057_NB_MASTER_CORE0, 1977 + ~R2057_VCM_MASK, vcm); 2073 1978 else 2074 1979 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 2075 1980 0xE3, vcm_final << 2); ··· 2142 2041 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; 2143 2042 } 2144 2043 if (dev->phy.rev >= 7) { 2044 + rssical_radio_regs[0] = b43_radio_read(dev, 2045 + R2057_NB_MASTER_CORE0); 2046 + rssical_radio_regs[1] = b43_radio_read(dev, 2047 + R2057_NB_MASTER_CORE1); 2145 2048 } else { 2146 2049 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 | 2147 2050 B2056_RX_RSSI_MISC); ··· 2580 2475 b43_nphy_gain_ctl_workarounds_rev3(dev); 2581 2476 else 2582 2477 b43_nphy_gain_ctl_workarounds_rev1_2(dev); 2583 - } 2584 - 2585 - /* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */ 2586 - static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset) 2587 - { 2588 - if (!offset) 2589 - offset = b43_is_40mhz(dev) ? 0x159 : 0x154; 2590 - return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7; 2591 2478 } 2592 2479 2593 2480 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev) ··· 3268 3171 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ 3269 3172 static void b43_nphy_stop_playback(struct b43_wldev *dev) 3270 3173 { 3174 + struct b43_phy *phy = &dev->phy; 3271 3175 struct b43_phy_n *nphy = dev->phy.n; 3272 3176 u16 tmp; 3273 3177 ··· 3289 3191 nphy->bb_mult_save = 0; 3290 3192 } 3291 3193 3292 - if (dev->phy.rev >= 7) { 3293 - /* TODO */ 3194 + if (phy->rev >= 7) { 3195 + if (phy->rev >= 19) 3196 + b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true, 3197 + 1); 3198 + else 3199 + b43_nphy_rf_ctl_override_rev7(dev, 0x80, 0, 0, true, 1); 3200 + nphy->lpf_bw_overrode_for_sample_play = false; 3294 3201 } 3295 3202 3296 3203 if (nphy->hang_avoid) ··· 3312 3209 u16 gain; 3313 3210 3314 3211 if (dev->phy.rev >= 3) { 3212 + params->tx_lpf = target.tx_lpf[core]; /* Rev 7+ */ 3315 3213 params->txgm = target.txgm[core]; 3316 3214 params->pga = target.pga[core]; 3317 3215 params->pad = target.pad[core]; ··· 3320 3216 if (phy->rev >= 19) { 3321 3217 /* TODO */ 3322 3218 } else if (phy->rev >= 7) { 3323 - /* TODO */ 3219 + params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 3) | (params->ipa) | (params->tx_lpf << 15); 3324 3220 } else { 3325 3221 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 4) | (params->ipa); 3326 3222 } ··· 3437 3333 if (phy->rev >= 19) { 3438 3334 /* TODO */ 3439 3335 } else if (phy->rev >= 7) { 3440 - /* TODO */ 3336 + b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, 3337 + ~B43_NPHY_TXPCTL_CMD_INIT, 3338 + 0x32); 3339 + b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, 3340 + ~B43_NPHY_TXPCTL_INIT_PIDXI1, 3341 + 0x32); 3441 3342 } else { 3442 3343 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, 3443 3344 ~B43_NPHY_TXPCTL_CMD_INIT, ··· 4030 3921 B43_NPHY_RFCTL_INTC2); 4031 3922 band = b43_current_band(dev->wl); 4032 3923 if (dev->phy.rev >= 7) { 4033 - /* TODO */ 4034 - return; 3924 + tmp = 0x1480; 4035 3925 } else if (dev->phy.rev >= 3) { 4036 3926 if (band == IEEE80211_BAND_5GHZ) 4037 3927 tmp = 0x600; ··· 4481 4373 if (dev->phy.rev >= 19) { 4482 4374 /* TODO */ 4483 4375 } else if (dev->phy.rev >= 7) { 4484 - /* TODO */ 4376 + b43_radio_maskset(dev, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK, 4377 + rssical_radio_regs[0]); 4378 + b43_radio_maskset(dev, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK, 4379 + rssical_radio_regs[1]); 4485 4380 } else { 4486 4381 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3, 4487 4382 rssical_radio_regs[0]); ··· 4515 4404 4516 4405 static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev *dev) 4517 4406 { 4518 - /* TODO */ 4407 + struct b43_phy *phy = &dev->phy; 4408 + struct b43_phy_n *nphy = dev->phy.n; 4409 + u16 *save = nphy->tx_rx_cal_radio_saveregs; 4410 + int core, off; 4411 + u16 r, tmp; 4412 + 4413 + for (core = 0; core < 2; core++) { 4414 + r = core ? 0x20 : 0; 4415 + off = core * 11; 4416 + 4417 + save[off + 0] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MASTER); 4418 + save[off + 1] = b43_radio_read(dev, r + R2057_TX0_IQCAL_VCM_HG); 4419 + save[off + 2] = b43_radio_read(dev, r + R2057_TX0_IQCAL_IDAC); 4420 + save[off + 3] = b43_radio_read(dev, r + R2057_TX0_TSSI_VCM); 4421 + save[off + 4] = 0; 4422 + save[off + 5] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MUX); 4423 + if (phy->radio_rev != 5) 4424 + save[off + 6] = b43_radio_read(dev, r + R2057_TX0_TSSIA); 4425 + save[off + 7] = b43_radio_read(dev, r + R2057_TX0_TSSIG); 4426 + save[off + 8] = b43_radio_read(dev, r + R2057_TX0_TSSI_MISC1); 4427 + 4428 + if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 4429 + b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0xA); 4430 + b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); 4431 + b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); 4432 + b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); 4433 + b43_radio_write(dev, r + R2057_TX0_TSSIG, 0); 4434 + if (nphy->use_int_tx_iq_lo_cal) { 4435 + b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x4); 4436 + tmp = true ? 0x31 : 0x21; /* TODO */ 4437 + b43_radio_write(dev, r + R2057_TX0_TSSIA, tmp); 4438 + } 4439 + b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0x00); 4440 + } else { 4441 + b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0x6); 4442 + b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); 4443 + b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); 4444 + b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); 4445 + 4446 + if (phy->radio_rev != 5) 4447 + b43_radio_write(dev, r + R2057_TX0_TSSIA, 0); 4448 + if (nphy->use_int_tx_iq_lo_cal) { 4449 + b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x6); 4450 + tmp = true ? 0x31 : 0x21; /* TODO */ 4451 + b43_radio_write(dev, r + R2057_TX0_TSSIG, tmp); 4452 + } 4453 + b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0); 4454 + } 4455 + } 4519 4456 } 4520 4457 4521 4458 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */ ··· 4744 4585 b43_nphy_stay_in_carrier_search(dev, false); 4745 4586 4746 4587 for (i = 0; i < 2; ++i) { 4747 - if (dev->phy.rev >= 3) { 4588 + if (dev->phy.rev >= 7) { 4589 + target.ipa[i] = curr_gain[i] & 0x0007; 4590 + target.pad[i] = (curr_gain[i] & 0x00F8) >> 3; 4591 + target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; 4592 + target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; 4593 + target.tx_lpf[i] = (curr_gain[i] & 0x8000) >> 15; 4594 + } else if (dev->phy.rev >= 3) { 4748 4595 target.ipa[i] = curr_gain[i] & 0x000F; 4749 4596 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; 4750 4597 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; ··· 4777 4612 if (!table) 4778 4613 break; 4779 4614 4780 - if (dev->phy.rev >= 3) { 4615 + if (dev->phy.rev >= 7) { 4616 + target.ipa[i] = (table[index[i]] >> 16) & 0x7; 4617 + target.pad[i] = (table[index[i]] >> 19) & 0x1F; 4618 + target.pga[i] = (table[index[i]] >> 24) & 0xF; 4619 + target.txgm[i] = (table[index[i]] >> 28) & 0x7; 4620 + target.tx_lpf[i] = (table[index[i]] >> 31) & 0x1; 4621 + } else if (dev->phy.rev >= 3) { 4781 4622 target.ipa[i] = (table[index[i]] >> 16) & 0xF; 4782 4623 target.pad[i] = (table[index[i]] >> 20) & 0xF; 4783 4624 target.pga[i] = (table[index[i]] >> 24) & 0xF; ··· 4833 4662 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) 4834 4663 { 4835 4664 struct b43_phy *phy = &dev->phy; 4665 + struct b43_phy_n *nphy = dev->phy.n; 4836 4666 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 4837 4667 u16 tmp; 4838 4668 ··· 4865 4693 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 4866 4694 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 4867 4695 4868 - b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3); 4696 + if (!nphy->use_int_tx_iq_lo_cal) 4697 + b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 4698 + 1, 3); 4699 + else 4700 + b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 4701 + 0, 3); 4869 4702 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1); 4870 4703 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2); 4871 4704 ··· 4879 4702 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); 4880 4703 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); 4881 4704 4705 + tmp = b43_nphy_read_lpf_ctl(dev, 0); 4882 4706 if (phy->rev >= 19) 4883 - ; /* TODO */ 4707 + b43_nphy_rf_ctl_override_rev19(dev, 0x80, tmp, 0, false, 4708 + 1); 4884 4709 else if (phy->rev >= 7) 4885 - ; /* TODO */ 4710 + b43_nphy_rf_ctl_override_rev7(dev, 0x80, tmp, 0, false, 4711 + 1); 4886 4712 4887 - if (0 /* FIXME */) { 4713 + if (nphy->use_int_tx_iq_lo_cal && true /* FIXME */) { 4888 4714 if (phy->rev >= 19) { 4889 - /* TODO */ 4715 + b43_nphy_rf_ctl_override_rev19(dev, 0x8, 0, 0x3, 4716 + false, 0); 4890 4717 } else if (phy->rev >= 8) { 4891 - /* TODO */ 4718 + b43_nphy_rf_ctl_override_rev7(dev, 0x8, 0, 0x3, 4719 + false, 0); 4892 4720 } else if (phy->rev == 7) { 4893 - /* TODO */ 4721 + b43_radio_maskset(dev, R2057_OVR_REG0, 1 << 4, 1 << 4); 4722 + if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 4723 + b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0); 4724 + b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0); 4725 + } else { 4726 + b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0); 4727 + b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0); 4728 + } 4894 4729 } 4895 4730 } 4896 4731 } else { ··· 4961 4772 if (phy->rev >= 19) { 4962 4773 /* TODO */ 4963 4774 } else if (phy->rev >= 7) { 4964 - /* TODO */ 4775 + txcal_radio_regs[0] = b43_radio_read(dev, 4776 + R2057_TX0_LOFT_FINE_I); 4777 + txcal_radio_regs[1] = b43_radio_read(dev, 4778 + R2057_TX0_LOFT_FINE_Q); 4779 + txcal_radio_regs[4] = b43_radio_read(dev, 4780 + R2057_TX0_LOFT_COARSE_I); 4781 + txcal_radio_regs[5] = b43_radio_read(dev, 4782 + R2057_TX0_LOFT_COARSE_Q); 4783 + txcal_radio_regs[2] = b43_radio_read(dev, 4784 + R2057_TX1_LOFT_FINE_I); 4785 + txcal_radio_regs[3] = b43_radio_read(dev, 4786 + R2057_TX1_LOFT_FINE_Q); 4787 + txcal_radio_regs[6] = b43_radio_read(dev, 4788 + R2057_TX1_LOFT_COARSE_I); 4789 + txcal_radio_regs[7] = b43_radio_read(dev, 4790 + R2057_TX1_LOFT_COARSE_Q); 4965 4791 } else if (phy->rev >= 3) { 4966 4792 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); 4967 4793 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); ··· 5055 4851 if (phy->rev >= 19) { 5056 4852 /* TODO */ 5057 4853 } else if (phy->rev >= 7) { 5058 - /* TODO */ 4854 + b43_radio_write(dev, R2057_TX0_LOFT_FINE_I, 4855 + txcal_radio_regs[0]); 4856 + b43_radio_write(dev, R2057_TX0_LOFT_FINE_Q, 4857 + txcal_radio_regs[1]); 4858 + b43_radio_write(dev, R2057_TX0_LOFT_COARSE_I, 4859 + txcal_radio_regs[4]); 4860 + b43_radio_write(dev, R2057_TX0_LOFT_COARSE_Q, 4861 + txcal_radio_regs[5]); 4862 + b43_radio_write(dev, R2057_TX1_LOFT_FINE_I, 4863 + txcal_radio_regs[2]); 4864 + b43_radio_write(dev, R2057_TX1_LOFT_FINE_Q, 4865 + txcal_radio_regs[3]); 4866 + b43_radio_write(dev, R2057_TX1_LOFT_COARSE_I, 4867 + txcal_radio_regs[6]); 4868 + b43_radio_write(dev, R2057_TX1_LOFT_COARSE_Q, 4869 + txcal_radio_regs[7]); 5059 4870 } else if (phy->rev >= 3) { 5060 4871 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); 5061 4872 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); ··· 5151 4932 if (phy->rev >= 19) { 5152 4933 /* TODO */ 5153 4934 } else if (phy->rev >= 7) { 5154 - /* TODO */ 4935 + b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AD9); 5155 4936 } else { 5156 4937 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); 5157 4938 } ··· 5715 5496 #endif 5716 5497 } 5717 5498 } 5499 + nphy->use_int_tx_iq_lo_cal = b43_nphy_ipa(dev) || 5500 + phy->rev >= 7 || 5501 + (phy->rev >= 5 && 5502 + sprom->boardflags2_hi & B43_BFH2_INTERNDET_TXIQCAL); 5718 5503 nphy->deaf_count = 0; 5719 5504 b43_nphy_tables_init(dev); 5720 5505 nphy->crsminpwr_adjusted = false; ··· 5729 5506 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); 5730 5507 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); 5731 5508 if (phy->rev >= 7) { 5732 - /* TODO */ 5509 + b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0); 5510 + b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0); 5511 + b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0); 5512 + b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0); 5733 5513 } 5734 5514 if (phy->rev >= 19) { 5735 5515 /* TODO */ ··· 6258 6032 b43err(dev->wl, "MAC not suspended\n"); 6259 6033 6260 6034 if (blocked) { 6261 - b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 6262 - ~B43_NPHY_RFCTL_CMD_CHIP0PU); 6263 6035 if (phy->rev >= 19) { 6264 6036 /* TODO */ 6037 + } else if (phy->rev >= 8) { 6038 + b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 6039 + ~B43_NPHY_RFCTL_CMD_CHIP0PU); 6265 6040 } else if (phy->rev >= 7) { 6266 - /* TODO */ 6041 + /* Nothing needed */ 6267 6042 } else if (phy->rev >= 3) { 6043 + b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 6044 + ~B43_NPHY_RFCTL_CMD_CHIP0PU); 6045 + 6268 6046 b43_radio_mask(dev, 0x09, ~0x2); 6269 6047 6270 6048 b43_radio_write(dev, 0x204D, 0);

+11

drivers/net/wireless/b43/phy_n.h

··· 857 857 #define B43_NPHY_REV3_C2_CLIP2_GAIN_A B43_PHY_N(0x2AF) 858 858 #define B43_NPHY_REV3_C2_CLIP2_GAIN_B B43_PHY_N(0x2B0) 859 859 860 + #define B43_NPHY_REV7_RF_CTL_MISC_REG3 B43_PHY_N(0x340) 861 + #define B43_NPHY_REV7_RF_CTL_MISC_REG4 B43_PHY_N(0x341) 862 + #define B43_NPHY_REV7_RF_CTL_OVER3 B43_PHY_N(0x342) 863 + #define B43_NPHY_REV7_RF_CTL_OVER4 B43_PHY_N(0x343) 864 + #define B43_NPHY_REV7_RF_CTL_MISC_REG5 B43_PHY_N(0x344) 865 + #define B43_NPHY_REV7_RF_CTL_MISC_REG6 B43_PHY_N(0x345) 866 + #define B43_NPHY_REV7_RF_CTL_OVER5 B43_PHY_N(0x346) 867 + #define B43_NPHY_REV7_RF_CTL_OVER6 B43_PHY_N(0x347) 868 + 860 869 #define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */ 861 870 #define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A) 862 871 ··· 944 935 bool gain_boost; 945 936 bool elna_gain_config; 946 937 bool band5g_pwrgain; 938 + bool use_int_tx_iq_lo_cal; 939 + bool lpf_bw_overrode_for_sample_play; 947 940 948 941 u8 mphase_cal_phase_id; 949 942 u16 mphase_txcal_cmdidx;

+10

drivers/net/wireless/b43/radio_2057.h

··· 84 84 #define R2057_CMOSBUF_RX_RCCR 0x04c 85 85 #define R2057_LOGEN_SEL_PKDET 0x04d 86 86 #define R2057_CMOSBUF_SHAREIQ_PTAT 0x04e 87 + 88 + /* MISC core 0 */ 87 89 #define R2057_RXTXBIAS_CONFIG_CORE0 0x04f 88 90 #define R2057_TXGM_TXRF_PUS_CORE0 0x050 89 91 #define R2057_TXGM_IDAC_BLEED_CORE0 0x051 ··· 206 204 #define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0x0d1 207 205 #define R2057_LPF_GAIN_CORE0 0x0d2 208 206 #define R2057_DACBUF_IDACS_BW_CORE0 0x0d3 207 + 208 + /* MISC core 1 */ 209 209 #define R2057_RXTXBIAS_CONFIG_CORE1 0x0d4 210 210 #define R2057_TXGM_TXRF_PUS_CORE1 0x0d5 211 211 #define R2057_TXGM_IDAC_BLEED_CORE1 0x0d6 ··· 328 324 #define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156 329 325 #define R2057_LPF_GAIN_CORE1 0x157 330 326 #define R2057_DACBUF_IDACS_BW_CORE1 0x158 327 + 331 328 #define R2057_DACBUF_VINCM_CORE1 0x159 332 329 #define R2057_RCCAL_START_R1_Q1_P1 0x15a 333 330 #define R2057_RCCAL_X1 0x15b ··· 350 345 #define R2057_RCCAL_BCAP_VAL 0x16b 351 346 #define R2057_RCCAL_HPC_VAL 0x16c 352 347 #define R2057_RCCAL_OVERRIDES 0x16d 348 + 349 + /* TX core 0 */ 353 350 #define R2057_TX0_IQCAL_GAIN_BW 0x170 354 351 #define R2057_TX0_LOFT_FINE_I 0x171 355 352 #define R2057_TX0_LOFT_FINE_Q 0x172 ··· 369 362 #define R2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e 370 363 #define R2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f 371 364 #define R2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180 365 + 366 + /* TX core 1 */ 372 367 #define R2057_TX1_IQCAL_GAIN_BW 0x190 373 368 #define R2057_TX1_LOFT_FINE_I 0x191 374 369 #define R2057_TX1_LOFT_FINE_Q 0x192 ··· 388 379 #define R2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e 389 380 #define R2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f 390 381 #define R2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0 382 + 391 383 #define R2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1 392 384 #define R2057_AFE_SET_VCM_I_CORE0 0x1a2 393 385 #define R2057_AFE_SET_VCM_Q_CORE0 0x1a3