tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amd/dc: include new ip and ip_offset headers

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Hawking Zhang and committed by
Alex Deucher 407e7517 48569ffc

+26 -13
+2 -1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 61 61 62 62 #include "dcn/dcn_1_0_offset.h" 63 63 #include "dcn/dcn_1_0_sh_mask.h" 64 - #include "soc15ip.h" 64 + #include "soc15_hw_ip.h" 65 + #include "vega10_ip_offset.h" 65 66 66 67 #include "soc15_common.h" 67 68 #endif
+2 -1
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
··· 33 33 34 34 #include "dce/dce_12_0_offset.h" 35 35 #include "dce/dce_12_0_sh_mask.h" 36 - #include "soc15ip.h" 36 + #include "soc15_hw_ip.h" 37 + #include "vega10_ip_offset.h" 37 38 #include "reg_helper.h" 38 39 39 40 #define CTX \
+2 -1
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
··· 56 56 57 57 #include "dce/dce_12_0_offset.h" 58 58 #include "dce/dce_12_0_sh_mask.h" 59 - #include "soc15ip.h" 59 + #include "soc15_hw_ip.h" 60 + #include "vega10_ip_offset.h" 60 61 #include "nbio/nbio_6_1_offset.h" 61 62 #include "reg_helper.h" 62 63
+2 -1
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
··· 27 27 28 28 #include "dce/dce_12_0_offset.h" 29 29 #include "dce/dce_12_0_sh_mask.h" 30 - #include "soc15ip.h" 30 + #include "soc15_hw_ip.h" 31 + #include "vega10_ip_offset.h" 31 32 32 33 #include "dc_types.h" 33 34 #include "dc_bios_types.h"
+2 -1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
··· 50 50 #include "dcn10_hubp.h" 51 51 #include "dcn10_hubbub.h" 52 52 53 - #include "soc15ip.h" 53 + #include "soc15_hw_ip.h" 54 + #include "vega10_ip_offset.h" 54 55 55 56 #include "dcn/dcn_1_0_offset.h" 56 57 #include "dcn/dcn_1_0_sh_mask.h"
+2 -1
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
··· 36 36 37 37 #include "dce/dce_12_0_offset.h" 38 38 #include "dce/dce_12_0_sh_mask.h" 39 - #include "soc15ip.h" 39 + #include "soc15_hw_ip.h" 40 + #include "vega10_ip_offset.h" 40 41 41 42 #define block HPD 42 43 #define reg_num 0
+2 -1
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
··· 35 35 36 36 #include "dce/dce_12_0_offset.h" 37 37 #include "dce/dce_12_0_sh_mask.h" 38 - #include "soc15ip.h" 38 + #include "soc15_hw_ip.h" 39 + #include "vega10_ip_offset.h" 39 40 40 41 /* begin ********************* 41 42 * macros to expend register list macro defined in HW object header file */
+2 -1
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
··· 36 36 37 37 #include "dcn/dcn_1_0_offset.h" 38 38 #include "dcn/dcn_1_0_sh_mask.h" 39 - #include "soc15ip.h" 39 + #include "soc15_hw_ip.h" 40 + #include "vega10_ip_offset.h" 40 41 41 42 #define block HPD 42 43 #define reg_num 0
+2 -1
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
··· 35 35 36 36 #include "dcn/dcn_1_0_offset.h" 37 37 #include "dcn/dcn_1_0_sh_mask.h" 38 - #include "soc15ip.h" 38 + #include "soc15_hw_ip.h" 39 + #include "vega10_ip_offset.h" 39 40 40 41 /* begin ********************* 41 42 * macros to expend register list macro defined in HW object header file */
+2 -1
drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
··· 38 38 39 39 #include "dce/dce_12_0_offset.h" 40 40 #include "dce/dce_12_0_sh_mask.h" 41 - #include "soc15ip.h" 41 + #include "soc15_hw_ip.h" 42 + #include "vega10_ip_offset.h" 42 43 43 44 /* begin ********************* 44 45 * macros to expend register list macro defined in HW object header file */
+2 -1
drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
··· 38 38 39 39 #include "dcn/dcn_1_0_offset.h" 40 40 #include "dcn/dcn_1_0_sh_mask.h" 41 - #include "soc15ip.h" 41 + #include "soc15_hw_ip.h" 42 + #include "vega10_ip_offset.h" 42 43 43 44 /* begin ********************* 44 45 * macros to expend register list macro defined in HW object header file */
+2 -1
drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
··· 32 32 33 33 #include "dce/dce_12_0_offset.h" 34 34 #include "dce/dce_12_0_sh_mask.h" 35 - #include "soc15ip.h" 35 + #include "soc15_hw_ip.h" 36 + #include "vega10_ip_offset.h" 36 37 37 38 #include "ivsrcid/ivsrcid_vislands30.h" 38 39
+2 -1
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
··· 31 31 32 32 #include "dcn/dcn_1_0_offset.h" 33 33 #include "dcn/dcn_1_0_sh_mask.h" 34 - #include "soc15ip.h" 34 + #include "soc15_hw_ip.h" 35 + #include "vega10_ip_offset.h" 35 36 36 37 #include "irq_service_dcn10.h" 37 38