tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

ARM: tegra: apalis: Properly align pin names

Align pin names on subsequent lines with the first the name of the first
pin in the first line.

Signed-off-by: Thierry Reding <treding@nvidia.com>

Thierry Reding 40699b92 4399f40b

+76 -76
+76 -76
arch/arm/boot/dts/tegra30-apalis.dtsi
··· 58 58 59 59 /* Apalis BKL1_PWM */ 60 60 uart3_rts_n_pc0 { 61 - nvidia,pins = "uart3_rts_n_pc0"; 61 + nvidia,pins = "uart3_rts_n_pc0"; 62 62 nvidia,function = "pwm0"; 63 63 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 64 64 nvidia,tristate = <TEGRA_PIN_DISABLE>; 65 65 }; 66 66 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ 67 67 uart3_cts_n_pa1 { 68 - nvidia,pins = "uart3_cts_n_pa1"; 68 + nvidia,pins = "uart3_cts_n_pa1"; 69 69 nvidia,function = "rsvd2"; 70 70 nvidia,pull = <TEGRA_PIN_PULL_UP>; 71 71 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 73 73 74 74 /* Apalis CAN1 on SPI6 */ 75 75 spi2_cs0_n_px3 { 76 - nvidia,pins = "spi2_cs0_n_px3", 77 - "spi2_miso_px1", 78 - "spi2_mosi_px0", 79 - "spi2_sck_px2"; 76 + nvidia,pins = "spi2_cs0_n_px3", 77 + "spi2_miso_px1", 78 + "spi2_mosi_px0", 79 + "spi2_sck_px2"; 80 80 nvidia,function = "spi6"; 81 81 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 82 82 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 92 92 93 93 /* Apalis CAN2 on SPI4 */ 94 94 gmi_a16_pj7 { 95 - nvidia,pins = "gmi_a16_pj7", 96 - "gmi_a17_pb0", 97 - "gmi_a18_pb1", 98 - "gmi_a19_pk7"; 95 + nvidia,pins = "gmi_a16_pj7", 96 + "gmi_a17_pb0", 97 + "gmi_a18_pb1", 98 + "gmi_a19_pk7"; 99 99 nvidia,function = "spi4"; 100 100 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 101 101 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 111 111 112 112 /* Apalis Digital Audio */ 113 113 clk1_req_pee2 { 114 - nvidia,pins = "clk1_req_pee2"; 114 + nvidia,pins = "clk1_req_pee2"; 115 115 nvidia,function = "hda"; 116 116 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 117 117 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 124 124 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 125 125 }; 126 126 dap1_fs_pn0 { 127 - nvidia,pins = "dap1_fs_pn0", 128 - "dap1_din_pn1", 129 - "dap1_dout_pn2", 130 - "dap1_sclk_pn3"; 127 + nvidia,pins = "dap1_fs_pn0", 128 + "dap1_din_pn1", 129 + "dap1_dout_pn2", 130 + "dap1_sclk_pn3"; 131 131 nvidia,function = "hda"; 132 132 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 133 133 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 147 147 148 148 /* Apalis MMC1 */ 149 149 sdmmc3_clk_pa6 { 150 - nvidia,pins = "sdmmc3_clk_pa6", 151 - "sdmmc3_cmd_pa7"; 150 + nvidia,pins = "sdmmc3_clk_pa6", 151 + "sdmmc3_cmd_pa7"; 152 152 nvidia,function = "sdmmc3"; 153 153 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 154 154 nvidia,tristate = <TEGRA_PIN_DISABLE>; 155 155 }; 156 156 sdmmc3_dat0_pb7 { 157 - nvidia,pins = "sdmmc3_dat0_pb7", 158 - "sdmmc3_dat1_pb6", 159 - "sdmmc3_dat2_pb5", 160 - "sdmmc3_dat3_pb4", 161 - "sdmmc3_dat4_pd1", 162 - "sdmmc3_dat5_pd0", 163 - "sdmmc3_dat6_pd3", 164 - "sdmmc3_dat7_pd4"; 157 + nvidia,pins = "sdmmc3_dat0_pb7", 158 + "sdmmc3_dat1_pb6", 159 + "sdmmc3_dat2_pb5", 160 + "sdmmc3_dat3_pb4", 161 + "sdmmc3_dat4_pd1", 162 + "sdmmc3_dat5_pd0", 163 + "sdmmc3_dat6_pd3", 164 + "sdmmc3_dat7_pd4"; 165 165 nvidia,function = "sdmmc3"; 166 166 nvidia,pull = <TEGRA_PIN_PULL_UP>; 167 167 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 177 177 178 178 /* Apalis PWM1 */ 179 179 pu6 { 180 - nvidia,pins = "pu6"; 180 + nvidia,pins = "pu6"; 181 181 nvidia,function = "pwm3"; 182 182 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 183 183 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 185 185 186 186 /* Apalis PWM2 */ 187 187 pu5 { 188 - nvidia,pins = "pu5"; 188 + nvidia,pins = "pu5"; 189 189 nvidia,function = "pwm2"; 190 190 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 191 191 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 193 193 194 194 /* Apalis PWM3 */ 195 195 pu4 { 196 - nvidia,pins = "pu4"; 196 + nvidia,pins = "pu4"; 197 197 nvidia,function = "pwm1"; 198 198 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 199 199 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 201 201 202 202 /* Apalis PWM4 */ 203 203 pu3 { 204 - nvidia,pins = "pu3"; 204 + nvidia,pins = "pu3"; 205 205 nvidia,function = "pwm0"; 206 206 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 207 207 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 223 223 nvidia,tristate = <TEGRA_PIN_DISABLE>; 224 224 }; 225 225 sdmmc1_cmd_pz1 { 226 - nvidia,pins = "sdmmc1_cmd_pz1", 227 - "sdmmc1_dat0_py7", 228 - "sdmmc1_dat1_py6", 229 - "sdmmc1_dat2_py5", 230 - "sdmmc1_dat3_py4"; 226 + nvidia,pins = "sdmmc1_cmd_pz1", 227 + "sdmmc1_dat0_py7", 228 + "sdmmc1_dat1_py6", 229 + "sdmmc1_dat2_py5", 230 + "sdmmc1_dat3_py4"; 231 231 nvidia,function = "sdmmc1"; 232 232 nvidia,pull = <TEGRA_PIN_PULL_UP>; 233 233 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 243 243 244 244 /* Apalis SPI1 */ 245 245 spi1_sck_px5 { 246 - nvidia,pins = "spi1_sck_px5", 247 - "spi1_mosi_px4", 248 - "spi1_miso_px7", 249 - "spi1_cs0_n_px6"; 246 + nvidia,pins = "spi1_sck_px5", 247 + "spi1_mosi_px4", 248 + "spi1_miso_px7", 249 + "spi1_cs0_n_px6"; 250 250 nvidia,function = "spi1"; 251 251 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 252 252 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 254 254 255 255 /* Apalis SPI2 */ 256 256 lcd_sck_pz4 { 257 - nvidia,pins = "lcd_sck_pz4", 258 - "lcd_sdout_pn5", 259 - "lcd_sdin_pz2", 260 - "lcd_cs0_n_pn4"; 257 + nvidia,pins = "lcd_sck_pz4", 258 + "lcd_sdout_pn5", 259 + "lcd_sdin_pz2", 260 + "lcd_cs0_n_pn4"; 261 261 nvidia,function = "spi5"; 262 262 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 263 263 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 265 265 266 266 /* Apalis UART1 */ 267 267 ulpi_data0 { 268 - nvidia,pins = "ulpi_data0_po1", 269 - "ulpi_data1_po2", 270 - "ulpi_data2_po3", 271 - "ulpi_data3_po4", 272 - "ulpi_data4_po5", 273 - "ulpi_data5_po6", 274 - "ulpi_data6_po7", 275 - "ulpi_data7_po0"; 268 + nvidia,pins = "ulpi_data0_po1", 269 + "ulpi_data1_po2", 270 + "ulpi_data2_po3", 271 + "ulpi_data3_po4", 272 + "ulpi_data4_po5", 273 + "ulpi_data5_po6", 274 + "ulpi_data6_po7", 275 + "ulpi_data7_po0"; 276 276 nvidia,function = "uarta"; 277 277 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 278 278 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 280 280 281 281 /* Apalis UART2 */ 282 282 ulpi_clk_py0 { 283 - nvidia,pins = "ulpi_clk_py0", 284 - "ulpi_dir_py1", 285 - "ulpi_nxt_py2", 286 - "ulpi_stp_py3"; 283 + nvidia,pins = "ulpi_clk_py0", 284 + "ulpi_dir_py1", 285 + "ulpi_nxt_py2", 286 + "ulpi_stp_py3"; 287 287 nvidia,function = "uartd"; 288 288 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 289 289 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 291 291 292 292 /* Apalis UART3 */ 293 293 uart2_rxd_pc3 { 294 - nvidia,pins = "uart2_rxd_pc3", 295 - "uart2_txd_pc2"; 294 + nvidia,pins = "uart2_rxd_pc3", 295 + "uart2_txd_pc2"; 296 296 nvidia,function = "uartb"; 297 297 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 298 298 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 300 300 301 301 /* Apalis UART4 */ 302 302 uart3_rxd_pw7 { 303 - nvidia,pins = "uart3_rxd_pw7", 304 - "uart3_txd_pw6"; 303 + nvidia,pins = "uart3_rxd_pw7", 304 + "uart3_txd_pw6"; 305 305 nvidia,function = "uartc"; 306 306 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 307 307 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 337 337 338 338 /* eMMC (On-module) */ 339 339 sdmmc4_clk_pcc4 { 340 - nvidia,pins = "sdmmc4_clk_pcc4", 341 - "sdmmc4_rst_n_pcc3"; 340 + nvidia,pins = "sdmmc4_clk_pcc4", 341 + "sdmmc4_rst_n_pcc3"; 342 342 nvidia,function = "sdmmc4"; 343 343 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 344 344 nvidia,tristate = <TEGRA_PIN_DISABLE>; 345 345 }; 346 346 sdmmc4_dat0_paa0 { 347 - nvidia,pins = "sdmmc4_dat0_paa0", 348 - "sdmmc4_dat1_paa1", 349 - "sdmmc4_dat2_paa2", 350 - "sdmmc4_dat3_paa3", 351 - "sdmmc4_dat4_paa4", 352 - "sdmmc4_dat5_paa5", 353 - "sdmmc4_dat6_paa6", 354 - "sdmmc4_dat7_paa7"; 347 + nvidia,pins = "sdmmc4_dat0_paa0", 348 + "sdmmc4_dat1_paa1", 349 + "sdmmc4_dat2_paa2", 350 + "sdmmc4_dat3_paa3", 351 + "sdmmc4_dat4_paa4", 352 + "sdmmc4_dat5_paa5", 353 + "sdmmc4_dat6_paa6", 354 + "sdmmc4_dat7_paa7"; 355 355 nvidia,function = "sdmmc4"; 356 356 nvidia,pull = <TEGRA_PIN_PULL_UP>; 357 357 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 359 359 360 360 /* LVDS Transceiver Configuration */ 361 361 pbb0 { 362 - nvidia,pins = "pbb0", 363 - "pbb7", 364 - "pcc1", 365 - "pcc2"; 362 + nvidia,pins = "pbb0", 363 + "pbb7", 364 + "pcc1", 365 + "pcc2"; 366 366 nvidia,function = "rsvd2"; 367 367 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 368 368 nvidia,tristate = <TEGRA_PIN_DISABLE>; ··· 370 370 nvidia,lock = <TEGRA_PIN_DISABLE>; 371 371 }; 372 372 pbb3 { 373 - nvidia,pins = "pbb3", 374 - "pbb4", 375 - "pbb5", 376 - "pbb6"; 373 + nvidia,pins = "pbb3", 374 + "pbb4", 375 + "pbb5", 376 + "pbb6"; 377 377 nvidia,function = "displayb"; 378 378 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 379 379 nvidia,tristate = <TEGRA_PIN_DISABLE>;