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dt-bindings: Document EMAC Rockchip

This adds the necessary binding documentation for the EMAC Rockchip platform
driver found in RK3066 and RK3188 SoCs.

Signed-off-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Romain Perier and committed by
David S. Miller
40404e00 6eacf311

+50
+50
Documentation/devicetree/bindings/net/emac_rockchip.txt
··· 1 + * ARC EMAC 10/100 Ethernet platform driver for Rockchip Rk3066/RK3188 SoCs 2 + 3 + Required properties: 4 + - compatible: Should be "rockchip,rk3066-emac" or "rockchip,rk3188-emac" 5 + according to the target SoC. 6 + - reg: Address and length of the register set for the device 7 + - interrupts: Should contain the EMAC interrupts 8 + - rockchip,grf: phandle to the syscon grf used to control speed and mode 9 + for emac. 10 + - phy: see ethernet.txt file in the same directory. 11 + - phy-mode: see ethernet.txt file in the same directory. 12 + 13 + Optional properties: 14 + - phy-supply: phandle to a regulator if the PHY needs one 15 + 16 + Clock handling: 17 + - clocks: Must contain an entry for each entry in clock-names. 18 + - clock-names: Shall be "hclk" for the host clock needed to calculate and set 19 + polling period of EMAC and "macref" for the reference clock needed to transfer 20 + data to and from the phy. 21 + 22 + Child nodes of the driver are the individual PHY devices connected to the 23 + MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus. 24 + 25 + Examples: 26 + 27 + ethernet@10204000 { 28 + compatible = "rockchip,rk3188-emac"; 29 + reg = <0xc0fc2000 0x3c>; 30 + interrupts = <6>; 31 + mac-address = [ 00 11 22 33 44 55 ]; 32 + 33 + clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; 34 + clock-names = "hclk", "macref"; 35 + 36 + pinctrl-names = "default"; 37 + pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; 38 + 39 + rockchip,grf = <&grf>; 40 + 41 + phy = <&phy0>; 42 + phy-mode = "rmii"; 43 + phy-supply = <&vcc_rmii>; 44 + 45 + #address-cells = <1>; 46 + #size-cells = <0>; 47 + phy0: ethernet-phy@0 { 48 + reg = <1>; 49 + }; 50 + };