tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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[SCSI] a100u2w: Convert into Linux style

I was investigating strange driver behaviour and thought that readable
code and proper visible types might help explain why it didn't work right
the moment a second SCB was outstanding to the controller. I was right

- Cleanup, linuxise, demacro
- Remove the BSD dual licence on the new work
- Switch the if ALPHA to if __LP64__. (struct size is then right
elsewhere) and then to CONFIG_64BIT as per Christoph's request
- Fix the recursive locking on a reset. This is the only actual real code
change (I hope ;)).

I'm not clear what the right way to handle the BIOS param stuff is on n
on x86-32/64. Using phys_to_virt and stuff is ugly and probably doesn't
make sense elsewhere

Still has a couple of odd things - and there seems to be a commonly shared
EEPROM handling error several drivers have. Roughly speaking several SCSI
drivers go

try and read EEPROM
It failed..
Write any changes between the default and the data we read

Which is great as for some paths we've no idea what was in
before, so each boot won't write it all back, won't checksum but will
repeat the bug

Also it can still sleep for a second with IRQ off, and there is some
dubious looking error path locking marked FIXME in case anyone feels
inspired to work on it. Not a newly introduced bug, and at least its now
marked.

Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>

authored by

Alan Cox and committed by
James Bottomley 4023c474 0d2fcd9f

+764 -760
+639 -590
drivers/scsi/a100u2w.c
··· 19 19 * along with this program; see the file COPYING. If not, write to 20 20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 21 21 * 22 - * -------------------------------------------------------------------------- 23 - * 24 - * Redistribution and use in source and binary forms, with or without 25 - * modification, are permitted provided that the following conditions 26 - * are met: 27 - * 1. Redistributions of source code must retain the above copyright 28 - * notice, this list of conditions, and the following disclaimer, 29 - * without modification, immediately at the beginning of the file. 30 - * 2. Redistributions in binary form must reproduce the above copyright 31 - * notice, this list of conditions and the following disclaimer in the 32 - * documentation and/or other materials provided with the distribution. 33 - * 3. The name of the author may not be used to endorse or promote products 34 - * derived from this software without specific prior written permission. 35 - * 36 - * Where this Software is combined with software released under the terms of 37 - * the GNU General Public License ("GPL") and the terms of the GPL would require the 38 - * combined work to also be released under the terms of the GPL, the terms 39 - * and conditions of this License will apply in addition to those of the 40 - * GPL with the exception of any terms or conditions of this License that 41 - * conflict with, or are expressly prohibited by, the GPL. 42 - * 43 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 44 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 45 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ··· 54 75 * 9/28/04 Christoph Hellwig <hch@lst.de> 55 76 * - merge the two source files 56 77 * - remove internal queueing code 78 + * 14/06/07 Alan Cox <alan@redhat.com> 79 + * - Grand cleanup and Linuxisation 57 80 */ 58 81 59 82 #include <linux/module.h> ··· 83 102 #include "a100u2w.h" 84 103 85 104 86 - #define JIFFIES_TO_MS(t) ((t) * 1000 / HZ) 87 - #define MS_TO_JIFFIES(j) ((j * HZ) / 1000) 105 + static struct orc_scb *__orc_alloc_scb(struct orc_host * host); 106 + static void inia100_scb_handler(struct orc_host *host, struct orc_scb *scb); 88 107 89 - static ORC_SCB *orc_alloc_scb(ORC_HCS * hcsp); 90 - static void inia100SCBPost(BYTE * pHcb, BYTE * pScb); 108 + static struct orc_nvram nvram, *nvramp = &nvram; 91 109 92 - static NVRAM nvram, *nvramp = &nvram; 93 - static UCHAR dftNvRam[64] = 110 + static u8 default_nvram[64] = 94 111 { 95 112 /*----------header -------------*/ 96 113 0x01, /* 0x00: Sub System Vendor ID 0 */ ··· 137 158 }; 138 159 139 160 140 - /***************************************************************************/ 141 - static void waitForPause(unsigned amount) 142 - { 143 - ULONG the_time = jiffies + MS_TO_JIFFIES(amount); 144 - while (time_before_eq(jiffies, the_time)) 145 - cpu_relax(); 146 - } 147 - 148 - /***************************************************************************/ 149 - static UCHAR waitChipReady(ORC_HCS * hcsp) 161 + static u8 wait_chip_ready(struct orc_host * host) 150 162 { 151 163 int i; 152 164 153 165 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ 154 - if (ORC_RD(hcsp->HCS_Base, ORC_HCTRL) & HOSTSTOP) /* Wait HOSTSTOP set */ 166 + if (inb(host->base + ORC_HCTRL) & HOSTSTOP) /* Wait HOSTSTOP set */ 155 167 return 1; 156 - waitForPause(100); /* wait 100ms before try again */ 168 + mdelay(100); 169 + } 170 + return 0; 171 + } 172 + 173 + static u8 wait_firmware_ready(struct orc_host * host) 174 + { 175 + int i; 176 + 177 + for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ 178 + if (inb(host->base + ORC_HSTUS) & RREADY) /* Wait READY set */ 179 + return 1; 180 + mdelay(100); /* wait 100ms before try again */ 157 181 } 158 182 return 0; 159 183 } 160 184 161 185 /***************************************************************************/ 162 - static UCHAR waitFWReady(ORC_HCS * hcsp) 186 + static u8 wait_scsi_reset_done(struct orc_host * host) 163 187 { 164 188 int i; 165 189 166 190 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ 167 - if (ORC_RD(hcsp->HCS_Base, ORC_HSTUS) & RREADY) /* Wait READY set */ 191 + if (!(inb(host->base + ORC_HCTRL) & SCSIRST)) /* Wait SCSIRST done */ 168 192 return 1; 169 - waitForPause(100); /* wait 100ms before try again */ 193 + mdelay(100); /* wait 100ms before try again */ 170 194 } 171 195 return 0; 172 196 } 173 197 174 198 /***************************************************************************/ 175 - static UCHAR waitSCSIRSTdone(ORC_HCS * hcsp) 199 + static u8 wait_HDO_off(struct orc_host * host) 176 200 { 177 201 int i; 178 202 179 203 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ 180 - if (!(ORC_RD(hcsp->HCS_Base, ORC_HCTRL) & SCSIRST)) /* Wait SCSIRST done */ 204 + if (!(inb(host->base + ORC_HCTRL) & HDO)) /* Wait HDO off */ 181 205 return 1; 182 - waitForPause(100); /* wait 100ms before try again */ 206 + mdelay(100); /* wait 100ms before try again */ 183 207 } 184 208 return 0; 185 209 } 186 210 187 211 /***************************************************************************/ 188 - static UCHAR waitHDOoff(ORC_HCS * hcsp) 212 + static u8 wait_hdi_set(struct orc_host * host, u8 * data) 189 213 { 190 214 int i; 191 215 192 216 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ 193 - if (!(ORC_RD(hcsp->HCS_Base, ORC_HCTRL) & HDO)) /* Wait HDO off */ 194 - return 1; 195 - waitForPause(100); /* wait 100ms before try again */ 196 - } 197 - return 0; 198 - } 199 - 200 - /***************************************************************************/ 201 - static UCHAR waitHDIset(ORC_HCS * hcsp, UCHAR * pData) 202 - { 203 - int i; 204 - 205 - for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ 206 - if ((*pData = ORC_RD(hcsp->HCS_Base, ORC_HSTUS)) & HDI) 217 + if ((*data = inb(host->base + ORC_HSTUS)) & HDI) 207 218 return 1; /* Wait HDI set */ 208 - waitForPause(100); /* wait 100ms before try again */ 219 + mdelay(100); /* wait 100ms before try again */ 209 220 } 210 221 return 0; 211 222 } 212 223 213 224 /***************************************************************************/ 214 - static unsigned short get_FW_version(ORC_HCS * hcsp) 225 + static unsigned short orc_read_fwrev(struct orc_host * host) 215 226 { 216 - UCHAR bData; 217 - union { 218 - unsigned short sVersion; 219 - unsigned char cVersion[2]; 220 - } Version; 227 + u16 version; 228 + u8 data; 221 229 222 - ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_VERSION); 223 - ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO); 224 - if (waitHDOoff(hcsp) == 0) /* Wait HDO off */ 230 + outb(ORC_CMD_VERSION, host->base + ORC_HDATA); 231 + outb(HDO, host->base + ORC_HCTRL); 232 + if (wait_HDO_off(host) == 0) /* Wait HDO off */ 225 233 return 0; 226 234 227 - if (waitHDIset(hcsp, &bData) == 0) /* Wait HDI set */ 235 + if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */ 228 236 return 0; 229 - Version.cVersion[0] = ORC_RD(hcsp->HCS_Base, ORC_HDATA); 230 - ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData); /* Clear HDI */ 237 + version = inb(host->base + ORC_HDATA); 238 + outb(data, host->base + ORC_HSTUS); /* Clear HDI */ 231 239 232 - if (waitHDIset(hcsp, &bData) == 0) /* Wait HDI set */ 240 + if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */ 233 241 return 0; 234 - Version.cVersion[1] = ORC_RD(hcsp->HCS_Base, ORC_HDATA); 235 - ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData); /* Clear HDI */ 242 + version |= inb(host->base + ORC_HDATA) << 8; 243 + outb(data, host->base + ORC_HSTUS); /* Clear HDI */ 236 244 237 - return (Version.sVersion); 245 + return version; 238 246 } 239 247 240 248 /***************************************************************************/ 241 - static UCHAR set_NVRAM(ORC_HCS * hcsp, unsigned char address, unsigned char value) 249 + static u8 orc_nv_write(struct orc_host * host, unsigned char address, unsigned char value) 242 250 { 243 - ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_SET_NVM); /* Write command */ 244 - ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO); 245 - if (waitHDOoff(hcsp) == 0) /* Wait HDO off */ 251 + outb(ORC_CMD_SET_NVM, host->base + ORC_HDATA); /* Write command */ 252 + outb(HDO, host->base + ORC_HCTRL); 253 + if (wait_HDO_off(host) == 0) /* Wait HDO off */ 246 254 return 0; 247 255 248 - ORC_WR(hcsp->HCS_Base + ORC_HDATA, address); /* Write address */ 249 - ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO); 250 - if (waitHDOoff(hcsp) == 0) /* Wait HDO off */ 256 + outb(address, host->base + ORC_HDATA); /* Write address */ 257 + outb(HDO, host->base + ORC_HCTRL); 258 + if (wait_HDO_off(host) == 0) /* Wait HDO off */ 251 259 return 0; 252 260 253 - ORC_WR(hcsp->HCS_Base + ORC_HDATA, value); /* Write value */ 254 - ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO); 255 - if (waitHDOoff(hcsp) == 0) /* Wait HDO off */ 261 + outb(value, host->base + ORC_HDATA); /* Write value */ 262 + outb(HDO, host->base + ORC_HCTRL); 263 + if (wait_HDO_off(host) == 0) /* Wait HDO off */ 256 264 return 0; 257 265 258 266 return 1; 259 267 } 260 268 261 269 /***************************************************************************/ 262 - static UCHAR get_NVRAM(ORC_HCS * hcsp, unsigned char address, unsigned char *pDataIn) 270 + static u8 orc_nv_read(struct orc_host * host, u8 address, u8 *ptr) 263 271 { 264 - unsigned char bData; 272 + unsigned char data; 265 273 266 - ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_GET_NVM); /* Write command */ 267 - ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO); 268 - if (waitHDOoff(hcsp) == 0) /* Wait HDO off */ 274 + outb(ORC_CMD_GET_NVM, host->base + ORC_HDATA); /* Write command */ 275 + outb(HDO, host->base + ORC_HCTRL); 276 + if (wait_HDO_off(host) == 0) /* Wait HDO off */ 269 277 return 0; 270 278 271 - ORC_WR(hcsp->HCS_Base + ORC_HDATA, address); /* Write address */ 272 - ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO); 273 - if (waitHDOoff(hcsp) == 0) /* Wait HDO off */ 279 + outb(address, host->base + ORC_HDATA); /* Write address */ 280 + outb(HDO, host->base + ORC_HCTRL); 281 + if (wait_HDO_off(host) == 0) /* Wait HDO off */ 274 282 return 0; 275 283 276 - if (waitHDIset(hcsp, &bData) == 0) /* Wait HDI set */ 284 + if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */ 277 285 return 0; 278 - *pDataIn = ORC_RD(hcsp->HCS_Base, ORC_HDATA); 279 - ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData); /* Clear HDI */ 286 + *ptr = inb(host->base + ORC_HDATA); 287 + outb(data, host->base + ORC_HSTUS); /* Clear HDI */ 280 288 281 289 return 1; 290 + 282 291 } 283 292 284 - /***************************************************************************/ 285 - static void orc_exec_scb(ORC_HCS * hcsp, ORC_SCB * scbp) 293 + /** 294 + * orc_exec_sb - Queue an SCB with the HA 295 + * @host: host adapter the SCB belongs to 296 + * @scb: SCB to queue for execution 297 + */ 298 + 299 + static void orc_exec_scb(struct orc_host * host, struct orc_scb * scb) 286 300 { 287 - scbp->SCB_Status = ORCSCB_POST; 288 - ORC_WR(hcsp->HCS_Base + ORC_PQUEUE, scbp->SCB_ScbIdx); 289 - return; 301 + scb->status = ORCSCB_POST; 302 + outb(scb->scbidx, host->base + ORC_PQUEUE); 290 303 } 291 304 292 305 293 - /*********************************************************************** 294 - Read SCSI H/A configuration parameters from serial EEPROM 295 - ************************************************************************/ 296 - static int se2_rd_all(ORC_HCS * hcsp) 306 + /** 307 + * se2_rd_all - read SCSI parameters from EEPROM 308 + * @host: Host whose EEPROM is being loaded 309 + * 310 + * Read SCSI H/A configuration parameters from serial EEPROM 311 + */ 312 + 313 + static int se2_rd_all(struct orc_host * host) 297 314 { 298 315 int i; 299 - UCHAR *np, chksum = 0; 316 + u8 *np, chksum = 0; 300 317 301 - np = (UCHAR *) nvramp; 318 + np = (u8 *) nvramp; 302 319 for (i = 0; i < 64; i++, np++) { /* <01> */ 303 - if (get_NVRAM(hcsp, (unsigned char) i, np) == 0) 320 + if (orc_nv_read(host, (u8) i, np) == 0) 304 321 return -1; 305 - // *np++ = get_NVRAM(hcsp, (unsigned char ) i); 306 322 } 307 323 308 - /*------ Is ckecksum ok ? ------*/ 309 - np = (UCHAR *) nvramp; 324 + /*------ Is ckecksum ok ? ------*/ 325 + np = (u8 *) nvramp; 310 326 for (i = 0; i < 63; i++) 311 327 chksum += *np++; 312 328 313 - if (nvramp->CheckSum != (UCHAR) chksum) 329 + if (nvramp->CheckSum != (u8) chksum) 314 330 return -1; 315 331 return 1; 316 332 } 317 333 318 - /************************************************************************ 319 - Update SCSI H/A configuration parameters from serial EEPROM 320 - *************************************************************************/ 321 - static void se2_update_all(ORC_HCS * hcsp) 334 + /** 335 + * se2_update_all - update the EEPROM 336 + * @host: Host whose EEPROM is being updated 337 + * 338 + * Update changed bytes in the EEPROM image. 339 + */ 340 + 341 + static void se2_update_all(struct orc_host * host) 322 342 { /* setup default pattern */ 323 343 int i; 324 - UCHAR *np, *np1, chksum = 0; 344 + u8 *np, *np1, chksum = 0; 325 345 326 346 /* Calculate checksum first */ 327 - np = (UCHAR *) dftNvRam; 347 + np = (u8 *) default_nvram; 328 348 for (i = 0; i < 63; i++) 329 349 chksum += *np++; 330 350 *np = chksum; 331 351 332 - np = (UCHAR *) dftNvRam; 333 - np1 = (UCHAR *) nvramp; 352 + np = (u8 *) default_nvram; 353 + np1 = (u8 *) nvramp; 334 354 for (i = 0; i < 64; i++, np++, np1++) { 335 - if (*np != *np1) { 336 - set_NVRAM(hcsp, (unsigned char) i, *np); 337 - } 338 - } 339 - return; 340 - } 341 - 342 - /************************************************************************* 343 - Function name : read_eeprom 344 - **************************************************************************/ 345 - static void read_eeprom(ORC_HCS * hcsp) 346 - { 347 - if (se2_rd_all(hcsp) != 1) { 348 - se2_update_all(hcsp); /* setup default pattern */ 349 - se2_rd_all(hcsp); /* load again */ 355 + if (*np != *np1) 356 + orc_nv_write(host, (u8) i, *np); 350 357 } 351 358 } 352 359 360 + /** 361 + * read_eeprom - load EEPROM 362 + * @host: Host EEPROM to read 363 + * 364 + * Read the EEPROM for a given host. If it is invalid or fails 365 + * the restore the defaults and use them. 366 + */ 353 367 354 - /***************************************************************************/ 355 - static UCHAR load_FW(ORC_HCS * hcsp) 368 + static void read_eeprom(struct orc_host * host) 356 369 { 357 - U32 dData; 358 - USHORT wBIOSAddress; 359 - USHORT i; 360 - UCHAR *pData, bData; 370 + if (se2_rd_all(host) != 1) { 371 + se2_update_all(host); /* setup default pattern */ 372 + se2_rd_all(host); /* load again */ 373 + } 374 + } 361 375 362 376 363 - bData = ORC_RD(hcsp->HCS_Base, ORC_GCFG); 364 - ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData | EEPRG); /* Enable EEPROM programming */ 365 - ORC_WR(hcsp->HCS_Base + ORC_EBIOSADR2, 0x00); 366 - ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x00); 367 - if (ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA) != 0x55) { 368 - ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData); /* Disable EEPROM programming */ 377 + /** 378 + * orc_load_firmware - initialise firmware 379 + * @host: Host to set up 380 + * 381 + * Load the firmware from the EEPROM into controller SRAM. This 382 + * is basically a 4K block copy and then a 4K block read to check 383 + * correctness. The rest is convulted by the indirect interfaces 384 + * in the hardware 385 + */ 386 + 387 + static u8 orc_load_firmware(struct orc_host * host) 388 + { 389 + u32 data32; 390 + u16 bios_addr; 391 + u16 i; 392 + u8 *data32_ptr, data; 393 + 394 + 395 + /* Set up the EEPROM for access */ 396 + 397 + data = inb(host->base + ORC_GCFG); 398 + outb(data | EEPRG, host->base + ORC_GCFG); /* Enable EEPROM programming */ 399 + outb(0x00, host->base + ORC_EBIOSADR2); 400 + outw(0x0000, host->base + ORC_EBIOSADR0); 401 + if (inb(host->base + ORC_EBIOSDATA) != 0x55) { 402 + outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */ 369 403 return 0; 370 404 } 371 - ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x01); 372 - if (ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA) != 0xAA) { 373 - ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData); /* Disable EEPROM programming */ 405 + outw(0x0001, host->base + ORC_EBIOSADR0); 406 + if (inb(host->base + ORC_EBIOSDATA) != 0xAA) { 407 + outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */ 374 408 return 0; 375 409 } 376 - ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST | DOWNLOAD); /* Enable SRAM programming */ 377 - pData = (UCHAR *) & dData; 378 - dData = 0; /* Initial FW address to 0 */ 379 - ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x10); 380 - *pData = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA); /* Read from BIOS */ 381 - ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x11); 382 - *(pData + 1) = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA); /* Read from BIOS */ 383 - ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x12); 384 - *(pData + 2) = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA); /* Read from BIOS */ 385 - ORC_WR(hcsp->HCS_Base + ORC_EBIOSADR2, *(pData + 2)); 386 - ORC_WRLONG(hcsp->HCS_Base + ORC_FWBASEADR, dData); /* Write FW address */ 387 410 388 - wBIOSAddress = (USHORT) dData; /* FW code locate at BIOS address + ? */ 389 - for (i = 0, pData = (UCHAR *) & dData; /* Download the code */ 411 + outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Enable SRAM programming */ 412 + data32_ptr = (u8 *) & data32; 413 + data32 = 0; /* Initial FW address to 0 */ 414 + outw(0x0010, host->base + ORC_EBIOSADR0); 415 + *data32_ptr = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ 416 + outw(0x0011, host->base + ORC_EBIOSADR0); 417 + *(data32_ptr + 1) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ 418 + outw(0x0012, host->base + ORC_EBIOSADR0); 419 + *(data32_ptr + 2) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ 420 + outw(*(data32_ptr + 2), host->base + ORC_EBIOSADR2); 421 + outl(data32, host->base + ORC_FWBASEADR); /* Write FW address */ 422 + 423 + /* Copy the code from the BIOS to the SRAM */ 424 + 425 + bios_addr = (u16) data32; /* FW code locate at BIOS address + ? */ 426 + for (i = 0, data32_ptr = (u8 *) & data32; /* Download the code */ 390 427 i < 0x1000; /* Firmware code size = 4K */ 391 - i++, wBIOSAddress++) { 392 - ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, wBIOSAddress); 393 - *pData++ = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA); /* Read from BIOS */ 428 + i++, bios_addr++) { 429 + outw(bios_addr, host->base + ORC_EBIOSADR0); 430 + *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ 394 431 if ((i % 4) == 3) { 395 - ORC_WRLONG(hcsp->HCS_Base + ORC_RISCRAM, dData); /* Write every 4 bytes */ 396 - pData = (UCHAR *) & dData; 432 + outl(data32, host->base + ORC_RISCRAM); /* Write every 4 bytes */ 433 + data32_ptr = (u8 *) & data32; 397 434 } 398 435 } 399 436 400 - ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST | DOWNLOAD); /* Reset program count 0 */ 401 - wBIOSAddress -= 0x1000; /* Reset the BIOS adddress */ 402 - for (i = 0, pData = (UCHAR *) & dData; /* Check the code */ 437 + /* Go back and check they match */ 438 + 439 + outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Reset program count 0 */ 440 + bios_addr -= 0x1000; /* Reset the BIOS adddress */ 441 + for (i = 0, data32_ptr = (u8 *) & data32; /* Check the code */ 403 442 i < 0x1000; /* Firmware code size = 4K */ 404 - i++, wBIOSAddress++) { 405 - ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, wBIOSAddress); 406 - *pData++ = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA); /* Read from BIOS */ 443 + i++, bios_addr++) { 444 + outw(bios_addr, host->base + ORC_EBIOSADR0); 445 + *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ 407 446 if ((i % 4) == 3) { 408 - if (ORC_RDLONG(hcsp->HCS_Base, ORC_RISCRAM) != dData) { 409 - ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST); /* Reset program to 0 */ 410 - ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData); /*Disable EEPROM programming */ 447 + if (inl(host->base + ORC_RISCRAM) != data32) { 448 + outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ 449 + outb(data, host->base + ORC_GCFG); /*Disable EEPROM programming */ 411 450 return 0; 412 451 } 413 - pData = (UCHAR *) & dData; 452 + data32_ptr = (u8 *) & data32; 414 453 } 415 454 } 416 - ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST); /* Reset program to 0 */ 417 - ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData); /* Disable EEPROM programming */ 455 + 456 + /* Success */ 457 + outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ 458 + outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */ 418 459 return 1; 419 460 } 420 461 421 462 /***************************************************************************/ 422 - static void setup_SCBs(ORC_HCS * hcsp) 463 + static void setup_SCBs(struct orc_host * host) 423 464 { 424 - ORC_SCB *pVirScb; 465 + struct orc_scb *scb; 425 466 int i; 426 - ESCB *pVirEscb; 427 - dma_addr_t pPhysEscb; 467 + struct orc_extended_scb *escb; 468 + dma_addr_t escb_phys; 428 469 429 - /* Setup SCB HCS_Base and SCB Size registers */ 430 - ORC_WR(hcsp->HCS_Base + ORC_SCBSIZE, ORC_MAXQUEUE); /* Total number of SCBs */ 431 - /* SCB HCS_Base address 0 */ 432 - ORC_WRLONG(hcsp->HCS_Base + ORC_SCBBASE0, hcsp->HCS_physScbArray); 433 - /* SCB HCS_Base address 1 */ 434 - ORC_WRLONG(hcsp->HCS_Base + ORC_SCBBASE1, hcsp->HCS_physScbArray); 470 + /* Setup SCB base and SCB Size registers */ 471 + outb(ORC_MAXQUEUE, host->base + ORC_SCBSIZE); /* Total number of SCBs */ 472 + /* SCB base address 0 */ 473 + outl(host->scb_phys, host->base + ORC_SCBBASE0); 474 + /* SCB base address 1 */ 475 + outl(host->scb_phys, host->base + ORC_SCBBASE1); 435 476 436 477 /* setup scatter list address with one buffer */ 437 - pVirScb = hcsp->HCS_virScbArray; 438 - pVirEscb = hcsp->HCS_virEscbArray; 478 + scb = host->scb_virt; 479 + escb = host->escb_virt; 439 480 440 481 for (i = 0; i < ORC_MAXQUEUE; i++) { 441 - pPhysEscb = (hcsp->HCS_physEscbArray + (sizeof(ESCB) * i)); 442 - pVirScb->SCB_SGPAddr = (U32) pPhysEscb; 443 - pVirScb->SCB_SensePAddr = (U32) pPhysEscb; 444 - pVirScb->SCB_EScb = pVirEscb; 445 - pVirScb->SCB_ScbIdx = i; 446 - pVirScb++; 447 - pVirEscb++; 482 + escb_phys = (host->escb_phys + (sizeof(struct orc_extended_scb) * i)); 483 + scb->sg_addr = (u32) escb_phys; 484 + scb->sense_addr = (u32) escb_phys; 485 + scb->escb = escb; 486 + scb->scbidx = i; 487 + scb++; 488 + escb++; 448 489 } 449 - 450 - return; 451 490 } 452 491 453 - /***************************************************************************/ 454 - static void initAFlag(ORC_HCS * hcsp) 492 + /** 493 + * init_alloc_map - initialise allocation map 494 + * @host: host map to configure 495 + * 496 + * Initialise the allocation maps for this device. If the device 497 + * is not quiescent the caller must hold the allocation lock 498 + */ 499 + 500 + static void init_alloc_map(struct orc_host * host) 455 501 { 456 - UCHAR i, j; 502 + u8 i, j; 457 503 458 504 for (i = 0; i < MAX_CHANNELS; i++) { 459 505 for (j = 0; j < 8; j++) { 460 - hcsp->BitAllocFlag[i][j] = 0xffffffff; 506 + host->allocation_map[i][j] = 0xffffffff; 461 507 } 462 508 } 463 509 } 464 510 465 - /***************************************************************************/ 466 - static int init_orchid(ORC_HCS * hcsp) 467 - { 468 - UBYTE *readBytep; 469 - USHORT revision; 470 - UCHAR i; 511 + /** 512 + * init_orchid - initialise the host adapter 513 + * @host:host adapter to initialise 514 + * 515 + * Initialise the controller and if neccessary load the firmware. 516 + * 517 + * Returns -1 if the initialisation fails. 518 + */ 471 519 472 - initAFlag(hcsp); 473 - ORC_WR(hcsp->HCS_Base + ORC_GIMSK, 0xFF); /* Disable all interrupt */ 474 - if (ORC_RD(hcsp->HCS_Base, ORC_HSTUS) & RREADY) { /* Orchid is ready */ 475 - revision = get_FW_version(hcsp); 520 + static int init_orchid(struct orc_host * host) 521 + { 522 + u8 *ptr; 523 + u16 revision; 524 + u8 i; 525 + 526 + init_alloc_map(host); 527 + outb(0xFF, host->base + ORC_GIMSK); /* Disable all interrupts */ 528 + 529 + if (inb(host->base + ORC_HSTUS) & RREADY) { /* Orchid is ready */ 530 + revision = orc_read_fwrev(host); 476 531 if (revision == 0xFFFF) { 477 - ORC_WR(hcsp->HCS_Base + ORC_HCTRL, DEVRST); /* Reset Host Adapter */ 478 - if (waitChipReady(hcsp) == 0) 479 - return (-1); 480 - load_FW(hcsp); /* Download FW */ 481 - setup_SCBs(hcsp); /* Setup SCB HCS_Base and SCB Size registers */ 482 - ORC_WR(hcsp->HCS_Base + ORC_HCTRL, 0); /* clear HOSTSTOP */ 483 - if (waitFWReady(hcsp) == 0) 484 - return (-1); 532 + outb(DEVRST, host->base + ORC_HCTRL); /* Reset Host Adapter */ 533 + if (wait_chip_ready(host) == 0) 534 + return -1; 535 + orc_load_firmware(host); /* Download FW */ 536 + setup_SCBs(host); /* Setup SCB base and SCB Size registers */ 537 + outb(0x00, host->base + ORC_HCTRL); /* clear HOSTSTOP */ 538 + if (wait_firmware_ready(host) == 0) 539 + return -1; 485 540 /* Wait for firmware ready */ 486 541 } else { 487 - setup_SCBs(hcsp); /* Setup SCB HCS_Base and SCB Size registers */ 542 + setup_SCBs(host); /* Setup SCB base and SCB Size registers */ 488 543 } 489 544 } else { /* Orchid is not Ready */ 490 - ORC_WR(hcsp->HCS_Base + ORC_HCTRL, DEVRST); /* Reset Host Adapter */ 491 - if (waitChipReady(hcsp) == 0) 492 - return (-1); 493 - load_FW(hcsp); /* Download FW */ 494 - setup_SCBs(hcsp); /* Setup SCB HCS_Base and SCB Size registers */ 495 - ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO); /* Do Hardware Reset & */ 545 + outb(DEVRST, host->base + ORC_HCTRL); /* Reset Host Adapter */ 546 + if (wait_chip_ready(host) == 0) 547 + return -1; 548 + orc_load_firmware(host); /* Download FW */ 549 + setup_SCBs(host); /* Setup SCB base and SCB Size registers */ 550 + outb(HDO, host->base + ORC_HCTRL); /* Do Hardware Reset & */ 496 551 497 552 /* clear HOSTSTOP */ 498 - if (waitFWReady(hcsp) == 0) /* Wait for firmware ready */ 499 - return (-1); 553 + if (wait_firmware_ready(host) == 0) /* Wait for firmware ready */ 554 + return -1; 500 555 } 501 556 502 - /*------------- get serial EEProm settting -------*/ 557 + /* Load an EEProm copy into RAM */ 558 + /* Assumes single threaded at this point */ 559 + read_eeprom(host); 503 560 504 - read_eeprom(hcsp); 561 + if (nvramp->revision != 1) 562 + return -1; 505 563 506 - if (nvramp->Revision != 1) 507 - return (-1); 508 - 509 - hcsp->HCS_SCSI_ID = nvramp->SCSI0Id; 510 - hcsp->HCS_BIOS = nvramp->BIOSConfig1; 511 - hcsp->HCS_MaxTar = MAX_TARGETS; 512 - readBytep = (UCHAR *) & (nvramp->Target00Config); 513 - for (i = 0; i < 16; readBytep++, i++) { 514 - hcsp->TargetFlag[i] = *readBytep; 515 - hcsp->MaximumTags[i] = ORC_MAXTAGS; 516 - } /* for */ 517 - 518 - if (nvramp->SCSI0Config & NCC_BUSRESET) { /* Reset SCSI bus */ 519 - hcsp->HCS_Flags |= HCF_SCSI_RESET; 564 + host->scsi_id = nvramp->scsi_id; 565 + host->BIOScfg = nvramp->BIOSConfig1; 566 + host->max_targets = MAX_TARGETS; 567 + ptr = (u8 *) & (nvramp->Target00Config); 568 + for (i = 0; i < 16; ptr++, i++) { 569 + host->target_flag[i] = *ptr; 570 + host->max_tags[i] = ORC_MAXTAGS; 520 571 } 521 - ORC_WR(hcsp->HCS_Base + ORC_GIMSK, 0xFB); /* enable RP FIFO interrupt */ 522 - return (0); 572 + 573 + if (nvramp->SCSI0Config & NCC_BUSRESET) 574 + host->flags |= HCF_SCSI_RESET; 575 + outb(0xFB, host->base + ORC_GIMSK); /* enable RP FIFO interrupt */ 576 + return 0; 523 577 } 524 578 525 - /***************************************************************************** 526 - Function name : orc_reset_scsi_bus 527 - Description : Reset registers, reset a hanging bus and 528 - kill active and disconnected commands for target w/o soft reset 529 - Input : pHCB - Pointer to host adapter structure 530 - Output : None. 531 - Return : pSRB - Pointer to SCSI request block. 532 - *****************************************************************************/ 533 - static int orc_reset_scsi_bus(ORC_HCS * pHCB) 579 + /** 580 + * orc_reset_scsi_bus - perform bus reset 581 + * @host: host being reset 582 + * 583 + * Perform a full bus reset on the adapter. 584 + */ 585 + 586 + static int orc_reset_scsi_bus(struct orc_host * host) 534 587 { /* I need Host Control Block Information */ 535 - ULONG flags; 588 + unsigned long flags; 536 589 537 - spin_lock_irqsave(&(pHCB->BitAllocFlagLock), flags); 590 + spin_lock_irqsave(&host->allocation_lock, flags); 538 591 539 - initAFlag(pHCB); 592 + init_alloc_map(host); 540 593 /* reset scsi bus */ 541 - ORC_WR(pHCB->HCS_Base + ORC_HCTRL, SCSIRST); 542 - if (waitSCSIRSTdone(pHCB) == 0) { 543 - spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags); 594 + outb(SCSIRST, host->base + ORC_HCTRL); 595 + /* FIXME: We can spend up to a second with the lock held and 596 + interrupts off here */ 597 + if (wait_scsi_reset_done(host) == 0) { 598 + spin_unlock_irqrestore(&host->allocation_lock, flags); 544 599 return FAILED; 545 600 } else { 546 - spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags); 601 + spin_unlock_irqrestore(&host->allocation_lock, flags); 547 602 return SUCCESS; 548 603 } 549 604 } 550 605 551 - /***************************************************************************** 552 - Function name : orc_device_reset 553 - Description : Reset registers, reset a hanging bus and 554 - kill active and disconnected commands for target w/o soft reset 555 - Input : pHCB - Pointer to host adapter structure 556 - Output : None. 557 - Return : pSRB - Pointer to SCSI request block. 558 - *****************************************************************************/ 559 - static int orc_device_reset(ORC_HCS * pHCB, struct scsi_cmnd *SCpnt, unsigned int target) 560 - { /* I need Host Control Block Information */ 561 - ORC_SCB *pScb; 562 - ESCB *pVirEscb; 563 - ORC_SCB *pVirScb; 564 - UCHAR i; 565 - ULONG flags; 606 + /** 607 + * orc_device_reset - device reset handler 608 + * @host: host to reset 609 + * @cmd: command causing the reset 610 + * @target; target device 611 + * 612 + * Reset registers, reset a hanging bus and kill active and disconnected 613 + * commands for target w/o soft reset 614 + */ 566 615 567 - spin_lock_irqsave(&(pHCB->BitAllocFlagLock), flags); 568 - pScb = (ORC_SCB *) NULL; 569 - pVirEscb = (ESCB *) NULL; 616 + static int orc_device_reset(struct orc_host * host, struct scsi_cmnd *cmd, unsigned int target) 617 + { /* I need Host Control Block Information */ 618 + struct orc_scb *scb; 619 + struct orc_extended_scb *escb; 620 + struct orc_scb *host_scb; 621 + u8 i; 622 + unsigned long flags; 623 + 624 + spin_lock_irqsave(&(host->allocation_lock), flags); 625 + scb = (struct orc_scb *) NULL; 626 + escb = (struct orc_extended_scb *) NULL; 570 627 571 628 /* setup scatter list address with one buffer */ 572 - pVirScb = pHCB->HCS_virScbArray; 629 + host_scb = host->scb_virt; 573 630 574 - initAFlag(pHCB); 575 - /* device reset */ 631 + /* FIXME: is this safe if we then fail to issue the reset or race 632 + a completion ? */ 633 + init_alloc_map(host); 634 + 635 + /* Find the scb corresponding to the command */ 576 636 for (i = 0; i < ORC_MAXQUEUE; i++) { 577 - pVirEscb = pVirScb->SCB_EScb; 578 - if ((pVirScb->SCB_Status) && (pVirEscb->SCB_Srb == SCpnt)) 637 + escb = host_scb->escb; 638 + if (host_scb->status && escb->srb == cmd) 579 639 break; 580 - pVirScb++; 640 + host_scb++; 581 641 } 582 642 583 643 if (i == ORC_MAXQUEUE) { 584 - printk("Unable to Reset - No SCB Found\n"); 585 - spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags); 644 + printk(KERN_ERR "Unable to Reset - No SCB Found\n"); 645 + spin_unlock_irqrestore(&(host->allocation_lock), flags); 586 646 return FAILED; 587 647 } 588 - if ((pScb = orc_alloc_scb(pHCB)) == NULL) { 589 - spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags); 590 - return FAILED; 591 - } 592 - pScb->SCB_Opcode = ORC_BUSDEVRST; 593 - pScb->SCB_Target = target; 594 - pScb->SCB_HaStat = 0; 595 - pScb->SCB_TaStat = 0; 596 - pScb->SCB_Status = 0x0; 597 - pScb->SCB_Link = 0xFF; 598 - pScb->SCB_Reserved0 = 0; 599 - pScb->SCB_Reserved1 = 0; 600 - pScb->SCB_XferLen = 0; 601 - pScb->SCB_SGLen = 0; 602 648 603 - pVirEscb->SCB_Srb = NULL; 604 - pVirEscb->SCB_Srb = SCpnt; 605 - orc_exec_scb(pHCB, pScb); /* Start execute SCB */ 606 - spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags); 649 + /* Allocate a new SCB for the reset command to the firmware */ 650 + if ((scb = __orc_alloc_scb(host)) == NULL) { 651 + /* Can't happen.. */ 652 + spin_unlock_irqrestore(&(host->allocation_lock), flags); 653 + return FAILED; 654 + } 655 + 656 + /* Reset device is handled by the firmare, we fill in an SCB and 657 + fire it at the controller, it does the rest */ 658 + scb->opcode = ORC_BUSDEVRST; 659 + scb->target = target; 660 + scb->hastat = 0; 661 + scb->tastat = 0; 662 + scb->status = 0x0; 663 + scb->link = 0xFF; 664 + scb->reserved0 = 0; 665 + scb->reserved1 = 0; 666 + scb->xferlen = 0; 667 + scb->sg_len = 0; 668 + 669 + escb->srb = NULL; 670 + escb->srb = cmd; 671 + orc_exec_scb(host, scb); /* Start execute SCB */ 672 + spin_unlock_irqrestore(&host->allocation_lock, flags); 607 673 return SUCCESS; 608 674 } 609 675 676 + /** 677 + * __orc_alloc_scb - allocate an SCB 678 + * @host: host to allocate from 679 + * 680 + * Allocate an SCB and return a pointer to the SCB object. NULL 681 + * is returned if no SCB is free. The caller must already hold 682 + * the allocator lock at this point. 683 + */ 610 684 611 - /***************************************************************************/ 612 - static ORC_SCB *__orc_alloc_scb(ORC_HCS * hcsp) 685 + 686 + static struct orc_scb *__orc_alloc_scb(struct orc_host * host) 613 687 { 614 - ORC_SCB *pTmpScb; 615 - UCHAR Ch; 616 - ULONG idx; 617 - UCHAR index; 618 - UCHAR i; 688 + u8 channel; 689 + unsigned long idx; 690 + u8 index; 691 + u8 i; 619 692 620 - Ch = hcsp->HCS_Index; 693 + channel = host->index; 621 694 for (i = 0; i < 8; i++) { 622 695 for (index = 0; index < 32; index++) { 623 - if ((hcsp->BitAllocFlag[Ch][i] >> index) & 0x01) { 624 - hcsp->BitAllocFlag[Ch][i] &= ~(1 << index); 696 + if ((host->allocation_map[channel][i] >> index) & 0x01) { 697 + host->allocation_map[channel][i] &= ~(1 << index); 625 698 break; 626 699 } 627 700 } 628 701 idx = index + 32 * i; 629 - pTmpScb = (ORC_SCB *) ((ULONG) hcsp->HCS_virScbArray + (idx * sizeof(ORC_SCB))); 630 - return (pTmpScb); 702 + /* Translate the index to a structure instance */ 703 + return (struct orc_scb *) ((unsigned long) host->scb_virt + (idx * sizeof(struct orc_scb))); 631 704 } 632 - return (NULL); 705 + return NULL; 633 706 } 634 707 635 - static ORC_SCB *orc_alloc_scb(ORC_HCS * hcsp) 636 - { 637 - ORC_SCB *pTmpScb; 638 - ULONG flags; 708 + /** 709 + * orc_alloc_scb - allocate an SCB 710 + * @host: host to allocate from 711 + * 712 + * Allocate an SCB and return a pointer to the SCB object. NULL 713 + * is returned if no SCB is free. 714 + */ 639 715 640 - spin_lock_irqsave(&(hcsp->BitAllocFlagLock), flags); 641 - pTmpScb = __orc_alloc_scb(hcsp); 642 - spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags); 643 - return (pTmpScb); 716 + static struct orc_scb *orc_alloc_scb(struct orc_host * host) 717 + { 718 + struct orc_scb *scb; 719 + unsigned long flags; 720 + 721 + spin_lock_irqsave(&host->allocation_lock, flags); 722 + scb = __orc_alloc_scb(host); 723 + spin_unlock_irqrestore(&host->allocation_lock, flags); 724 + return scb; 644 725 } 645 726 727 + /** 728 + * orc_release_scb - release an SCB 729 + * @host: host owning the SCB 730 + * @scb: SCB that is now free 731 + * 732 + * Called to return a completed SCB to the allocation pool. Before 733 + * calling the SCB must be out of use on both the host and the HA. 734 + */ 646 735 647 - /***************************************************************************/ 648 - static void orc_release_scb(ORC_HCS * hcsp, ORC_SCB * scbp) 736 + static void orc_release_scb(struct orc_host *host, struct orc_scb *scb) 649 737 { 650 - ULONG flags; 651 - UCHAR Index; 652 - UCHAR i; 653 - UCHAR Ch; 738 + unsigned long flags; 739 + u8 index, i, channel; 654 740 655 - spin_lock_irqsave(&(hcsp->BitAllocFlagLock), flags); 656 - Ch = hcsp->HCS_Index; 657 - Index = scbp->SCB_ScbIdx; 658 - i = Index / 32; 659 - Index %= 32; 660 - hcsp->BitAllocFlag[Ch][i] |= (1 << Index); 661 - spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags); 741 + spin_lock_irqsave(&(host->allocation_lock), flags); 742 + channel = host->index; /* Channel */ 743 + index = scb->scbidx; 744 + i = index / 32; 745 + index %= 32; 746 + host->allocation_map[channel][i] |= (1 << index); 747 + spin_unlock_irqrestore(&(host->allocation_lock), flags); 662 748 } 663 749 664 - /***************************************************************************** 665 - Function name : abort_SCB 666 - Description : Abort a queued command. 667 - (commands that are on the bus can't be aborted easily) 668 - Input : pHCB - Pointer to host adapter structure 669 - Output : None. 670 - Return : pSRB - Pointer to SCSI request block. 671 - *****************************************************************************/ 672 - static int abort_SCB(ORC_HCS * hcsp, ORC_SCB * pScb) 750 + /** 751 + * orchid_abort_scb - abort a command 752 + * 753 + * Abort a queued command that has been passed to the firmware layer 754 + * if possible. This is all handled by the firmware. We aks the firmware 755 + * and it either aborts the command or fails 756 + */ 757 + 758 + static int orchid_abort_scb(struct orc_host * host, struct orc_scb * scb) 673 759 { 674 - unsigned char bData, bStatus; 760 + unsigned char data, status; 675 761 676 - ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_ABORT_SCB); /* Write command */ 677 - ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO); 678 - if (waitHDOoff(hcsp) == 0) /* Wait HDO off */ 762 + outb(ORC_CMD_ABORT_SCB, host->base + ORC_HDATA); /* Write command */ 763 + outb(HDO, host->base + ORC_HCTRL); 764 + if (wait_HDO_off(host) == 0) /* Wait HDO off */ 679 765 return 0; 680 766 681 - ORC_WR(hcsp->HCS_Base + ORC_HDATA, pScb->SCB_ScbIdx); /* Write address */ 682 - ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO); 683 - if (waitHDOoff(hcsp) == 0) /* Wait HDO off */ 767 + outb(scb->scbidx, host->base + ORC_HDATA); /* Write address */ 768 + outb(HDO, host->base + ORC_HCTRL); 769 + if (wait_HDO_off(host) == 0) /* Wait HDO off */ 684 770 return 0; 685 771 686 - if (waitHDIset(hcsp, &bData) == 0) /* Wait HDI set */ 772 + if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */ 687 773 return 0; 688 - bStatus = ORC_RD(hcsp->HCS_Base, ORC_HDATA); 689 - ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData); /* Clear HDI */ 774 + status = inb(host->base + ORC_HDATA); 775 + outb(data, host->base + ORC_HSTUS); /* Clear HDI */ 690 776 691 - if (bStatus == 1) /* 0 - Successfully */ 777 + if (status == 1) /* 0 - Successfully */ 692 778 return 0; /* 1 - Fail */ 693 779 return 1; 694 780 } 695 781 696 - /***************************************************************************** 697 - Function name : inia100_abort 698 - Description : Abort a queued command. 699 - (commands that are on the bus can't be aborted easily) 700 - Input : pHCB - Pointer to host adapter structure 701 - Output : None. 702 - Return : pSRB - Pointer to SCSI request block. 703 - *****************************************************************************/ 704 - static int orc_abort_srb(ORC_HCS * hcsp, struct scsi_cmnd *SCpnt) 782 + static int inia100_abort_cmd(struct orc_host * host, struct scsi_cmnd *cmd) 705 783 { 706 - ESCB *pVirEscb; 707 - ORC_SCB *pVirScb; 708 - UCHAR i; 709 - ULONG flags; 784 + struct orc_extended_scb *escb; 785 + struct orc_scb *scb; 786 + u8 i; 787 + unsigned long flags; 710 788 711 - spin_lock_irqsave(&(hcsp->BitAllocFlagLock), flags); 789 + spin_lock_irqsave(&(host->allocation_lock), flags); 712 790 713 - pVirScb = hcsp->HCS_virScbArray; 791 + scb = host->scb_virt; 714 792 715 - for (i = 0; i < ORC_MAXQUEUE; i++, pVirScb++) { 716 - pVirEscb = pVirScb->SCB_EScb; 717 - if ((pVirScb->SCB_Status) && (pVirEscb->SCB_Srb == SCpnt)) { 718 - if (pVirScb->SCB_TagMsg == 0) { 719 - spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags); 720 - return FAILED; 793 + /* Walk the queue until we find the SCB that belongs to the command 794 + block. This isn't a performance critical path so a walk in the park 795 + here does no harm */ 796 + 797 + for (i = 0; i < ORC_MAXQUEUE; i++, scb++) { 798 + escb = scb->escb; 799 + if (scb->status && escb->srb == cmd) { 800 + if (scb->tag_msg == 0) { 801 + goto out; 721 802 } else { 722 - if (abort_SCB(hcsp, pVirScb)) { 723 - pVirEscb->SCB_Srb = NULL; 724 - spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags); 803 + /* Issue an ABORT to the firmware */ 804 + if (orchid_abort_scb(host, scb)) { 805 + escb->srb = NULL; 806 + spin_unlock_irqrestore(&host->allocation_lock, flags); 725 807 return SUCCESS; 726 - } else { 727 - spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags); 728 - return FAILED; 729 - } 808 + } else 809 + goto out; 730 810 } 731 811 } 732 812 } 733 - spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags); 813 + out: 814 + spin_unlock_irqrestore(&host->allocation_lock, flags); 734 815 return FAILED; 735 816 } 736 817 737 - /*********************************************************************** 738 - Routine Description: 739 - This is the interrupt service routine for the Orchid SCSI adapter. 740 - It reads the interrupt register to determine if the adapter is indeed 741 - the source of the interrupt and clears the interrupt at the device. 742 - Arguments: 743 - HwDeviceExtension - HBA miniport driver's adapter data storage 744 - Return Value: 745 - ***********************************************************************/ 746 - static void orc_interrupt( 747 - ORC_HCS * hcsp 748 - ) 818 + /** 819 + * orc_interrupt - IRQ processing 820 + * @host: Host causing the interrupt 821 + * 822 + * This function is called from the IRQ handler and protected 823 + * by the host lock. While the controller reports that there are 824 + * scb's for processing we pull them off the controller, turn the 825 + * index into a host address pointer to the scb and call the scb 826 + * handler. 827 + * 828 + * Returns IRQ_HANDLED if any SCBs were processed, IRQ_NONE otherwise 829 + */ 830 + 831 + static irqreturn_t orc_interrupt(struct orc_host * host) 749 832 { 750 - BYTE bScbIdx; 751 - ORC_SCB *pScb; 833 + u8 scb_index; 834 + struct orc_scb *scb; 752 835 753 - if (ORC_RD(hcsp->HCS_Base, ORC_RQUEUECNT) == 0) { 754 - return; // 0; 836 + /* Check if we have an SCB queued for servicing */ 837 + if (inb(host->base + ORC_RQUEUECNT) == 0) 838 + return IRQ_NONE; 755 839 756 - } 757 840 do { 758 - bScbIdx = ORC_RD(hcsp->HCS_Base, ORC_RQUEUE); 841 + /* Get the SCB index of the SCB to service */ 842 + scb_index = inb(host->base + ORC_RQUEUE); 759 843 760 - pScb = (ORC_SCB *) ((ULONG) hcsp->HCS_virScbArray + (ULONG) (sizeof(ORC_SCB) * bScbIdx)); 761 - pScb->SCB_Status = 0x0; 762 - 763 - inia100SCBPost((BYTE *) hcsp, (BYTE *) pScb); 764 - } while (ORC_RD(hcsp->HCS_Base, ORC_RQUEUECNT)); 765 - return; //1; 766 - 844 + /* Translate it back to a host pointer */ 845 + scb = (struct orc_scb *) ((unsigned long) host->scb_virt + (unsigned long) (sizeof(struct orc_scb) * scb_index)); 846 + scb->status = 0x0; 847 + /* Process the SCB */ 848 + inia100_scb_handler(host, scb); 849 + } while (inb(host->base + ORC_RQUEUECNT)); 850 + return IRQ_HANDLED; 767 851 } /* End of I1060Interrupt() */ 768 852 769 - /***************************************************************************** 770 - Function name : inia100BuildSCB 771 - Description : 772 - Input : pHCB - Pointer to host adapter structure 773 - Output : None. 774 - Return : pSRB - Pointer to SCSI request block. 775 - *****************************************************************************/ 776 - static void inia100BuildSCB(ORC_HCS * pHCB, ORC_SCB * pSCB, struct scsi_cmnd * SCpnt) 853 + /** 854 + * inia100_build_scb - build SCB 855 + * @host: host owing the control block 856 + * @scb: control block to use 857 + * @cmd: Mid layer command 858 + * 859 + * Build a host adapter control block from the SCSI mid layer command 860 + */ 861 + 862 + static void inia100_build_scb(struct orc_host * host, struct orc_scb * scb, struct scsi_cmnd * cmd) 777 863 { /* Create corresponding SCB */ 778 864 struct scatterlist *sg; 779 - ORC_SG *pSG; /* Pointer to SG list */ 865 + struct orc_sgent *sgent; /* Pointer to SG list */ 780 866 int i, count_sg; 781 - ESCB *pEScb; 867 + struct orc_extended_scb *escb; 782 868 783 - pEScb = pSCB->SCB_EScb; 784 - pEScb->SCB_Srb = SCpnt; 785 - pSG = NULL; 869 + /* Links between the escb, scb and Linux scsi midlayer cmd */ 870 + escb = scb->escb; 871 + escb->srb = cmd; 872 + sgent = NULL; 786 873 787 - pSCB->SCB_Opcode = ORC_EXECSCSI; 788 - pSCB->SCB_Flags = SCF_NO_DCHK; /* Clear done bit */ 789 - pSCB->SCB_Target = SCpnt->device->id; 790 - pSCB->SCB_Lun = SCpnt->device->lun; 791 - pSCB->SCB_Reserved0 = 0; 792 - pSCB->SCB_Reserved1 = 0; 793 - pSCB->SCB_SGLen = 0; 874 + /* Set up the SCB to do a SCSI command block */ 875 + scb->opcode = ORC_EXECSCSI; 876 + scb->flags = SCF_NO_DCHK; /* Clear done bit */ 877 + scb->target = cmd->device->id; 878 + scb->lun = cmd->device->lun; 879 + scb->reserved0 = 0; 880 + scb->reserved1 = 0; 881 + scb->sg_len = 0; 794 882 795 - pSCB->SCB_XferLen = (U32) scsi_bufflen(SCpnt); 796 - pSG = (ORC_SG *) & pEScb->ESCB_SGList[0]; 883 + scb->xferlen = (u32) scsi_bufflen(cmd); 884 + sgent = (struct orc_sgent *) & escb->sglist[0]; 797 885 798 - count_sg = scsi_dma_map(SCpnt); 886 + count_sg = scsi_dma_map(cmd); 799 887 BUG_ON(count_sg < 0); 888 + 889 + /* Build the scatter gather lists */ 800 890 if (count_sg) { 801 - pSCB->SCB_SGLen = (U32) (count_sg * 8); 802 - scsi_for_each_sg(SCpnt, sg, count_sg, i) { 803 - pSG->SG_Ptr = (U32) sg_dma_address(sg); 804 - pSG->SG_Len = (U32) sg_dma_len(sg); 805 - pSG++; 891 + scb->sg_len = (u32) (count_sg * 8); 892 + scsi_for_each_sg(cmd, sg, count_sg, i) { 893 + sgent->base = (u32) sg_dma_address(sg); 894 + sgent->length = (u32) sg_dma_len(sg); 895 + sgent++; 806 896 } 807 897 } else { 808 - pSCB->SCB_SGLen = 0; 809 - pSG->SG_Ptr = 0; 810 - pSG->SG_Len = 0; 898 + scb->sg_len = 0; 899 + sgent->base = 0; 900 + sgent->length = 0; 811 901 } 812 - pSCB->SCB_SGPAddr = (U32) pSCB->SCB_SensePAddr; 813 - pSCB->SCB_HaStat = 0; 814 - pSCB->SCB_TaStat = 0; 815 - pSCB->SCB_Link = 0xFF; 816 - pSCB->SCB_SenseLen = SENSE_SIZE; 817 - pSCB->SCB_CDBLen = SCpnt->cmd_len; 818 - if (pSCB->SCB_CDBLen >= IMAX_CDB) { 819 - printk("max cdb length= %x\b", SCpnt->cmd_len); 820 - pSCB->SCB_CDBLen = IMAX_CDB; 902 + scb->sg_addr = (u32) scb->sense_addr; 903 + scb->hastat = 0; 904 + scb->tastat = 0; 905 + scb->link = 0xFF; 906 + scb->sense_len = SENSE_SIZE; 907 + scb->cdb_len = cmd->cmd_len; 908 + if (scb->cdb_len >= IMAX_CDB) { 909 + printk("max cdb length= %x\b", cmd->cmd_len); 910 + scb->cdb_len = IMAX_CDB; 821 911 } 822 - pSCB->SCB_Ident = SCpnt->device->lun | DISC_ALLOW; 823 - if (SCpnt->device->tagged_supported) { /* Tag Support */ 824 - pSCB->SCB_TagMsg = SIMPLE_QUEUE_TAG; /* Do simple tag only */ 912 + scb->ident = cmd->device->lun | DISC_ALLOW; 913 + if (cmd->device->tagged_supported) { /* Tag Support */ 914 + scb->tag_msg = SIMPLE_QUEUE_TAG; /* Do simple tag only */ 825 915 } else { 826 - pSCB->SCB_TagMsg = 0; /* No tag support */ 916 + scb->tag_msg = 0; /* No tag support */ 827 917 } 828 - memcpy(&pSCB->SCB_CDB[0], &SCpnt->cmnd, pSCB->SCB_CDBLen); 829 - return; 918 + memcpy(&scb->cdb[0], &cmd->cmnd, scb->cdb_len); 830 919 } 831 920 832 - /***************************************************************************** 833 - Function name : inia100_queue 834 - Description : Queue a command and setup interrupts for a free bus. 835 - Input : pHCB - Pointer to host adapter structure 836 - Output : None. 837 - Return : pSRB - Pointer to SCSI request block. 838 - *****************************************************************************/ 839 - static int inia100_queue(struct scsi_cmnd * SCpnt, void (*done) (struct scsi_cmnd *)) 840 - { 841 - register ORC_SCB *pSCB; 842 - ORC_HCS *pHCB; /* Point to Host adapter control block */ 921 + /** 922 + * inia100_queue - queue command with host 923 + * @cmd: Command block 924 + * @done: Completion function 925 + * 926 + * Called by the mid layer to queue a command. Process the command 927 + * block, build the host specific scb structures and if there is room 928 + * queue the command down to the controller 929 + */ 843 930 844 - pHCB = (ORC_HCS *) SCpnt->device->host->hostdata; 845 - SCpnt->scsi_done = done; 931 + static int inia100_queue(struct scsi_cmnd * cmd, void (*done) (struct scsi_cmnd *)) 932 + { 933 + struct orc_scb *scb; 934 + struct orc_host *host; /* Point to Host adapter control block */ 935 + 936 + host = (struct orc_host *) cmd->device->host->hostdata; 937 + cmd->scsi_done = done; 846 938 /* Get free SCSI control block */ 847 - if ((pSCB = orc_alloc_scb(pHCB)) == NULL) 939 + if ((scb = orc_alloc_scb(host)) == NULL) 848 940 return SCSI_MLQUEUE_HOST_BUSY; 849 941 850 - inia100BuildSCB(pHCB, pSCB, SCpnt); 851 - orc_exec_scb(pHCB, pSCB); /* Start execute SCB */ 852 - 853 - return (0); 942 + inia100_build_scb(host, scb, cmd); 943 + orc_exec_scb(host, scb); /* Start execute SCB */ 944 + return 0; 854 945 } 855 946 856 947 /***************************************************************************** 857 948 Function name : inia100_abort 858 949 Description : Abort a queued command. 859 950 (commands that are on the bus can't be aborted easily) 860 - Input : pHCB - Pointer to host adapter structure 951 + Input : host - Pointer to host adapter structure 861 952 Output : None. 862 953 Return : pSRB - Pointer to SCSI request block. 863 954 *****************************************************************************/ 864 - static int inia100_abort(struct scsi_cmnd * SCpnt) 955 + static int inia100_abort(struct scsi_cmnd * cmd) 865 956 { 866 - ORC_HCS *hcsp; 957 + struct orc_host *host; 867 958 868 - hcsp = (ORC_HCS *) SCpnt->device->host->hostdata; 869 - return orc_abort_srb(hcsp, SCpnt); 959 + host = (struct orc_host *) cmd->device->host->hostdata; 960 + return inia100_abort_cmd(host, cmd); 870 961 } 871 962 872 963 /***************************************************************************** 873 964 Function name : inia100_reset 874 965 Description : Reset registers, reset a hanging bus and 875 966 kill active and disconnected commands for target w/o soft reset 876 - Input : pHCB - Pointer to host adapter structure 967 + Input : host - Pointer to host adapter structure 877 968 Output : None. 878 969 Return : pSRB - Pointer to SCSI request block. 879 970 *****************************************************************************/ 880 - static int inia100_bus_reset(struct scsi_cmnd * SCpnt) 971 + static int inia100_bus_reset(struct scsi_cmnd * cmd) 881 972 { /* I need Host Control Block Information */ 882 - ORC_HCS *pHCB; 883 - pHCB = (ORC_HCS *) SCpnt->device->host->hostdata; 884 - return orc_reset_scsi_bus(pHCB); 973 + struct orc_host *host; 974 + host = (struct orc_host *) cmd->device->host->hostdata; 975 + return orc_reset_scsi_bus(host); 885 976 } 886 977 887 978 /***************************************************************************** 888 979 Function name : inia100_device_reset 889 980 Description : Reset the device 890 - Input : pHCB - Pointer to host adapter structure 981 + Input : host - Pointer to host adapter structure 891 982 Output : None. 892 983 Return : pSRB - Pointer to SCSI request block. 893 984 *****************************************************************************/ 894 - static int inia100_device_reset(struct scsi_cmnd * SCpnt) 985 + static int inia100_device_reset(struct scsi_cmnd * cmd) 895 986 { /* I need Host Control Block Information */ 896 - ORC_HCS *pHCB; 897 - pHCB = (ORC_HCS *) SCpnt->device->host->hostdata; 898 - return orc_device_reset(pHCB, SCpnt, scmd_id(SCpnt)); 987 + struct orc_host *host; 988 + host = (struct orc_host *) cmd->device->host->hostdata; 989 + return orc_device_reset(host, cmd, scmd_id(cmd)); 899 990 900 991 } 901 992 902 - /***************************************************************************** 903 - Function name : inia100SCBPost 904 - Description : This is callback routine be called when orc finish one 905 - SCSI command. 906 - Input : pHCB - Pointer to host adapter control block. 907 - pSCB - Pointer to SCSI control block. 908 - Output : None. 909 - Return : None. 910 - *****************************************************************************/ 911 - static void inia100SCBPost(BYTE * pHcb, BYTE * pScb) 912 - { 913 - struct scsi_cmnd *pSRB; /* Pointer to SCSI request block */ 914 - ORC_HCS *pHCB; 915 - ORC_SCB *pSCB; 916 - ESCB *pEScb; 993 + /** 994 + * inia100_scb_handler - interrupt callback 995 + * @host: Host causing the interrupt 996 + * @scb: SCB the controller returned as needing processing 997 + * 998 + * Perform completion processing on a control block. Do the conversions 999 + * from host to SCSI midlayer error coding, save any sense data and 1000 + * the complete with the midlayer and recycle the scb. 1001 + */ 917 1002 918 - pHCB = (ORC_HCS *) pHcb; 919 - pSCB = (ORC_SCB *) pScb; 920 - pEScb = pSCB->SCB_EScb; 921 - if ((pSRB = (struct scsi_cmnd *) pEScb->SCB_Srb) == 0) { 922 - printk("inia100SCBPost: SRB pointer is empty\n"); 923 - orc_release_scb(pHCB, pSCB); /* Release SCB for current channel */ 1003 + static void inia100_scb_handler(struct orc_host *host, struct orc_scb *scb) 1004 + { 1005 + struct scsi_cmnd *cmd; /* Pointer to SCSI request block */ 1006 + struct orc_extended_scb *escb; 1007 + 1008 + escb = scb->escb; 1009 + if ((cmd = (struct scsi_cmnd *) escb->srb) == NULL) { 1010 + printk(KERN_ERR "inia100_scb_handler: SRB pointer is empty\n"); 1011 + orc_release_scb(host, scb); /* Release SCB for current channel */ 924 1012 return; 925 1013 } 926 - pEScb->SCB_Srb = NULL; 1014 + escb->srb = NULL; 927 1015 928 - switch (pSCB->SCB_HaStat) { 1016 + switch (scb->hastat) { 929 1017 case 0x0: 930 1018 case 0xa: /* Linked command complete without error and linked normally */ 931 1019 case 0xb: /* Linked command complete without error interrupt generated */ 932 - pSCB->SCB_HaStat = 0; 1020 + scb->hastat = 0; 933 1021 break; 934 1022 935 1023 case 0x11: /* Selection time out-The initiator selection or target 936 1024 reselection was not complete within the SCSI Time out period */ 937 - pSCB->SCB_HaStat = DID_TIME_OUT; 1025 + scb->hastat = DID_TIME_OUT; 938 1026 break; 939 1027 940 1028 case 0x14: /* Target bus phase sequence failure-An invalid bus phase or bus 941 1029 phase sequence was requested by the target. The host adapter 942 1030 will generate a SCSI Reset Condition, notifying the host with 943 1031 a SCRD interrupt */ 944 - pSCB->SCB_HaStat = DID_RESET; 1032 + scb->hastat = DID_RESET; 945 1033 break; 946 1034 947 1035 case 0x1a: /* SCB Aborted. 07/21/98 */ 948 - pSCB->SCB_HaStat = DID_ABORT; 1036 + scb->hastat = DID_ABORT; 949 1037 break; 950 1038 951 1039 case 0x12: /* Data overrun/underrun-The target attempted to transfer more data ··· 1022 976 case 0x16: /* Invalid CCB Operation Code-The first byte of the CCB was invalid. */ 1023 977 1024 978 default: 1025 - printk("inia100: %x %x\n", pSCB->SCB_HaStat, pSCB->SCB_TaStat); 1026 - pSCB->SCB_HaStat = DID_ERROR; /* Couldn't find any better */ 979 + printk(KERN_DEBUG "inia100: %x %x\n", scb->hastat, scb->tastat); 980 + scb->hastat = DID_ERROR; /* Couldn't find any better */ 1027 981 break; 1028 982 } 1029 983 1030 - if (pSCB->SCB_TaStat == 2) { /* Check condition */ 1031 - memcpy((unsigned char *) &pSRB->sense_buffer[0], 1032 - (unsigned char *) &pEScb->ESCB_SGList[0], SENSE_SIZE); 984 + if (scb->tastat == 2) { /* Check condition */ 985 + memcpy((unsigned char *) &cmd->sense_buffer[0], 986 + (unsigned char *) &escb->sglist[0], SENSE_SIZE); 1033 987 } 1034 - pSRB->result = pSCB->SCB_TaStat | (pSCB->SCB_HaStat << 16); 1035 - 1036 - scsi_dma_unmap(pSRB); 1037 - 1038 - pSRB->scsi_done(pSRB); /* Notify system DONE */ 1039 - 1040 - orc_release_scb(pHCB, pSCB); /* Release SCB for current channel */ 988 + cmd->result = scb->tastat | (scb->hastat << 16); 989 + scsi_dma_unmap(cmd); 990 + cmd->scsi_done(cmd); /* Notify system DONE */ 991 + orc_release_scb(host, scb); /* Release SCB for current channel */ 1041 992 } 1042 993 1043 - /* 1044 - * Interrupt handler (main routine of the driver) 994 + /** 995 + * inia100_intr - interrupt handler 996 + * @irqno: Interrupt value 997 + * @devid: Host adapter 998 + * 999 + * Entry point for IRQ handling. All the real work is performed 1000 + * by orc_interrupt. 1045 1001 */ 1046 1002 static irqreturn_t inia100_intr(int irqno, void *devid) 1047 1003 { 1048 - struct Scsi_Host *host = (struct Scsi_Host *)devid; 1049 - ORC_HCS *pHcb = (ORC_HCS *)host->hostdata; 1004 + struct Scsi_Host *shost = (struct Scsi_Host *)devid; 1005 + struct orc_host *host = (struct orc_host *)shost->hostdata; 1050 1006 unsigned long flags; 1007 + irqreturn_t res; 1051 1008 1052 - spin_lock_irqsave(host->host_lock, flags); 1053 - orc_interrupt(pHcb); 1054 - spin_unlock_irqrestore(host->host_lock, flags); 1009 + spin_lock_irqsave(shost->host_lock, flags); 1010 + res = orc_interrupt(host); 1011 + spin_unlock_irqrestore(shost->host_lock, flags); 1055 1012 1056 - return IRQ_HANDLED; 1013 + return res; 1057 1014 } 1058 1015 1059 1016 static struct scsi_host_template inia100_template = { ··· 1077 1028 const struct pci_device_id *id) 1078 1029 { 1079 1030 struct Scsi_Host *shost; 1080 - ORC_HCS *pHCB; 1031 + struct orc_host *host; 1081 1032 unsigned long port, bios; 1082 1033 int error = -ENODEV; 1083 1034 u32 sz; 1084 - unsigned long dBiosAdr; 1085 - char *pbBiosAdr; 1035 + unsigned long biosaddr; 1036 + char *bios_phys; 1086 1037 1087 1038 if (pci_enable_device(pdev)) 1088 1039 goto out; ··· 1101 1052 } 1102 1053 1103 1054 /* <02> read from base address + 0x50 offset to get the bios value. */ 1104 - bios = ORC_RDWORD(port, 0x50); 1055 + bios = inw(port + 0x50); 1105 1056 1106 1057 1107 - shost = scsi_host_alloc(&inia100_template, sizeof(ORC_HCS)); 1058 + shost = scsi_host_alloc(&inia100_template, sizeof(struct orc_host)); 1108 1059 if (!shost) 1109 1060 goto out_release_region; 1110 1061 1111 - pHCB = (ORC_HCS *)shost->hostdata; 1112 - pHCB->pdev = pdev; 1113 - pHCB->HCS_Base = port; 1114 - pHCB->HCS_BIOS = bios; 1115 - spin_lock_init(&pHCB->BitAllocFlagLock); 1062 + host = (struct orc_host *)shost->hostdata; 1063 + host->pdev = pdev; 1064 + host->base = port; 1065 + host->BIOScfg = bios; 1066 + spin_lock_init(&host->allocation_lock); 1116 1067 1117 1068 /* Get total memory needed for SCB */ 1118 - sz = ORC_MAXQUEUE * sizeof(ORC_SCB); 1119 - pHCB->HCS_virScbArray = pci_alloc_consistent(pdev, sz, 1120 - &pHCB->HCS_physScbArray); 1121 - if (!pHCB->HCS_virScbArray) { 1069 + sz = ORC_MAXQUEUE * sizeof(struct orc_scb); 1070 + host->scb_virt = pci_alloc_consistent(pdev, sz, 1071 + &host->scb_phys); 1072 + if (!host->scb_virt) { 1122 1073 printk("inia100: SCB memory allocation error\n"); 1123 1074 goto out_host_put; 1124 1075 } 1125 - memset(pHCB->HCS_virScbArray, 0, sz); 1076 + memset(host->scb_virt, 0, sz); 1126 1077 1127 1078 /* Get total memory needed for ESCB */ 1128 - sz = ORC_MAXQUEUE * sizeof(ESCB); 1129 - pHCB->HCS_virEscbArray = pci_alloc_consistent(pdev, sz, 1130 - &pHCB->HCS_physEscbArray); 1131 - if (!pHCB->HCS_virEscbArray) { 1079 + sz = ORC_MAXQUEUE * sizeof(struct orc_extended_scb); 1080 + host->escb_virt = pci_alloc_consistent(pdev, sz, 1081 + &host->escb_phys); 1082 + if (!host->escb_virt) { 1132 1083 printk("inia100: ESCB memory allocation error\n"); 1133 1084 goto out_free_scb_array; 1134 1085 } 1135 - memset(pHCB->HCS_virEscbArray, 0, sz); 1086 + memset(host->escb_virt, 0, sz); 1136 1087 1137 - dBiosAdr = pHCB->HCS_BIOS; 1138 - dBiosAdr = (dBiosAdr << 4); 1139 - pbBiosAdr = phys_to_virt(dBiosAdr); 1140 - if (init_orchid(pHCB)) { /* Initialize orchid chip */ 1088 + biosaddr = host->BIOScfg; 1089 + biosaddr = (biosaddr << 4); 1090 + bios_phys = phys_to_virt(biosaddr); 1091 + if (init_orchid(host)) { /* Initialize orchid chip */ 1141 1092 printk("inia100: initial orchid fail!!\n"); 1142 1093 goto out_free_escb_array; 1143 1094 } 1144 1095 1145 - shost->io_port = pHCB->HCS_Base; 1096 + shost->io_port = host->base; 1146 1097 shost->n_io_port = 0xff; 1147 1098 shost->can_queue = ORC_MAXQUEUE; 1148 1099 shost->unique_id = shost->io_port; 1149 - shost->max_id = pHCB->HCS_MaxTar; 1100 + shost->max_id = host->max_targets; 1150 1101 shost->max_lun = 16; 1151 - shost->irq = pHCB->HCS_Intr = pdev->irq; 1152 - shost->this_id = pHCB->HCS_SCSI_ID; /* Assign HCS index */ 1102 + shost->irq = pdev->irq; 1103 + shost->this_id = host->scsi_id; /* Assign HCS index */ 1153 1104 shost->sg_tablesize = TOTAL_SG_ENTRY; 1154 1105 1155 1106 /* Initial orc chip */ ··· 1170 1121 scsi_scan_host(shost); 1171 1122 return 0; 1172 1123 1173 - out_free_irq: 1124 + out_free_irq: 1174 1125 free_irq(shost->irq, shost); 1175 - out_free_escb_array: 1176 - pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(ESCB), 1177 - pHCB->HCS_virEscbArray, pHCB->HCS_physEscbArray); 1178 - out_free_scb_array: 1179 - pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(ORC_SCB), 1180 - pHCB->HCS_virScbArray, pHCB->HCS_physScbArray); 1181 - out_host_put: 1126 + out_free_escb_array: 1127 + pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(struct orc_extended_scb), 1128 + host->escb_virt, host->escb_phys); 1129 + out_free_scb_array: 1130 + pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(struct orc_scb), 1131 + host->scb_virt, host->scb_phys); 1132 + out_host_put: 1182 1133 scsi_host_put(shost); 1183 - out_release_region: 1134 + out_release_region: 1184 1135 release_region(port, 256); 1185 - out_disable_device: 1136 + out_disable_device: 1186 1137 pci_disable_device(pdev); 1187 - out: 1138 + out: 1188 1139 return error; 1189 1140 } 1190 1141 1191 1142 static void __devexit inia100_remove_one(struct pci_dev *pdev) 1192 1143 { 1193 1144 struct Scsi_Host *shost = pci_get_drvdata(pdev); 1194 - ORC_HCS *pHCB = (ORC_HCS *)shost->hostdata; 1145 + struct orc_host *host = (struct orc_host *)shost->hostdata; 1195 1146 1196 1147 scsi_remove_host(shost); 1197 1148 1198 1149 free_irq(shost->irq, shost); 1199 - pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(ESCB), 1200 - pHCB->HCS_virEscbArray, pHCB->HCS_physEscbArray); 1201 - pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(ORC_SCB), 1202 - pHCB->HCS_virScbArray, pHCB->HCS_physScbArray); 1150 + pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(struct orc_extended_scb), 1151 + host->escb_virt, host->escb_phys); 1152 + pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(struct orc_scb), 1153 + host->scb_virt, host->scb_phys); 1203 1154 release_region(shost->io_port, 256); 1204 1155 1205 1156 scsi_host_put(shost);
+125 -170
drivers/scsi/a100u2w.h
··· 18 18 * along with this program; see the file COPYING. If not, write to 19 19 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 20 20 * 21 - * -------------------------------------------------------------------------- 22 - * 23 - * Redistribution and use in source and binary forms, with or without 24 - * modification, are permitted provided that the following conditions 25 - * are met: 26 - * 1. Redistributions of source code must retain the above copyright 27 - * notice, this list of conditions, and the following disclaimer, 28 - * without modification, immediately at the beginning of the file. 29 - * 2. Redistributions in binary form must reproduce the above copyright 30 - * notice, this list of conditions and the following disclaimer in the 31 - * documentation and/or other materials provided with the distribution. 32 - * 3. The name of the author may not be used to endorse or promote products 33 - * derived from this software without specific prior written permission. 34 - * 35 - * Where this Software is combined with software released under the terms of 36 - * the GNU General Public License ("GPL") and the terms of the GPL would require the 37 - * combined work to also be released under the terms of the GPL, the terms 38 - * and conditions of this License will apply in addition to those of the 39 - * GPL with the exception of any terms or conditions of this License that 40 - * conflict with, or are expressly prohibited by, the GPL. 41 - * 42 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 43 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 44 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ··· 29 50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 52 * SUCH DAMAGE. 32 - */ 33 - 34 - /* 53 + * 35 54 * Revision History: 36 55 * 06/18/98 HL, Initial production Version 1.02 37 56 * 12/19/98 bv, Use spinlocks for 2.1.95 and up 38 57 * 06/25/02 Doug Ledford <dledford@redhat.com> 39 58 * - This and the i60uscsi.h file are almost identical, 40 59 * merged them into a single header used by both .c files. 60 + * 14/06/07 Alan Cox <alan@redhat.com> 61 + * - Grand cleanup and Linuxisation 41 62 */ 42 63 43 64 #define inia100_REVID "Initio INI-A100U2W SCSI device driver; Revision: 1.02d" 44 - 45 - #define ULONG unsigned long 46 - #define USHORT unsigned short 47 - #define UCHAR unsigned char 48 - #define BYTE unsigned char 49 - #define WORD unsigned short 50 - #define DWORD unsigned long 51 - #define UBYTE unsigned char 52 - #define UWORD unsigned short 53 - #define UDWORD unsigned long 54 - #define U32 u32 55 65 56 66 #if 1 57 67 #define ORC_MAXQUEUE 245 ··· 58 90 /************************************************************************/ 59 91 /* Scatter-Gather Element Structure */ 60 92 /************************************************************************/ 61 - typedef struct ORC_SG_Struc { 62 - U32 SG_Ptr; /* Data Pointer */ 63 - U32 SG_Len; /* Data Length */ 64 - } ORC_SG; 93 + struct orc_sgent { 94 + u32 base; /* Data Pointer */ 95 + u32 length; /* Data Length */ 96 + }; 65 97 66 98 /* SCSI related definition */ 67 99 #define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */ ··· 133 165 #define ORC_PRGMCTR1 0xE3 /* RISC program counter */ 134 166 #define ORC_RISCRAM 0xEC /* RISC RAM data port 4 bytes */ 135 167 136 - typedef struct orc_extended_scb { /* Extended SCB */ 137 - ORC_SG ESCB_SGList[TOTAL_SG_ENTRY]; /*0 Start of SG list */ 138 - struct scsi_cmnd *SCB_Srb; /*50 SRB Pointer */ 139 - } ESCB; 168 + struct orc_extended_scb { /* Extended SCB */ 169 + struct orc_sgent sglist[TOTAL_SG_ENTRY]; /*0 Start of SG list */ 170 + struct scsi_cmnd *srb; /*50 SRB Pointer */ 171 + }; 140 172 141 173 /*********************************************************************** 142 174 SCSI Control Block 143 - ************************************************************************/ 144 - typedef struct orc_scb { /* Scsi_Ctrl_Blk */ 145 - UBYTE SCB_Opcode; /*00 SCB command code&residual */ 146 - UBYTE SCB_Flags; /*01 SCB Flags */ 147 - UBYTE SCB_Target; /*02 Target Id */ 148 - UBYTE SCB_Lun; /*03 Lun */ 149 - U32 SCB_Reserved0; /*04 Reserved for ORCHID must 0 */ 150 - U32 SCB_XferLen; /*08 Data Transfer Length */ 151 - U32 SCB_Reserved1; /*0C Reserved for ORCHID must 0 */ 152 - U32 SCB_SGLen; /*10 SG list # * 8 */ 153 - U32 SCB_SGPAddr; /*14 SG List Buf physical Addr */ 154 - U32 SCB_SGPAddrHigh; /*18 SG Buffer high physical Addr */ 155 - UBYTE SCB_HaStat; /*1C Host Status */ 156 - UBYTE SCB_TaStat; /*1D Target Status */ 157 - UBYTE SCB_Status; /*1E SCB status */ 158 - UBYTE SCB_Link; /*1F Link pointer, default 0xFF */ 159 - UBYTE SCB_SenseLen; /*20 Sense Allocation Length */ 160 - UBYTE SCB_CDBLen; /*21 CDB Length */ 161 - UBYTE SCB_Ident; /*22 Identify */ 162 - UBYTE SCB_TagMsg; /*23 Tag Message */ 163 - UBYTE SCB_CDB[IMAX_CDB]; /*24 SCSI CDBs */ 164 - UBYTE SCB_ScbIdx; /*3C Index for this ORCSCB */ 165 - U32 SCB_SensePAddr; /*34 Sense Buffer physical Addr */ 166 175 167 - ESCB *SCB_EScb; /*38 Extended SCB Pointer */ 168 - #ifndef ALPHA 169 - UBYTE SCB_Reserved2[4]; /*3E Reserved for Driver use */ 176 + 0x40 bytes long, the last 8 are user bytes 177 + ************************************************************************/ 178 + struct orc_scb { /* Scsi_Ctrl_Blk */ 179 + u8 opcode; /*00 SCB command code&residual */ 180 + u8 flags; /*01 SCB Flags */ 181 + u8 target; /*02 Target Id */ 182 + u8 lun; /*03 Lun */ 183 + u32 reserved0; /*04 Reserved for ORCHID must 0 */ 184 + u32 xferlen; /*08 Data Transfer Length */ 185 + u32 reserved1; /*0C Reserved for ORCHID must 0 */ 186 + u32 sg_len; /*10 SG list # * 8 */ 187 + u32 sg_addr; /*14 SG List Buf physical Addr */ 188 + u32 sg_addrhigh; /*18 SG Buffer high physical Addr */ 189 + u8 hastat; /*1C Host Status */ 190 + u8 tastat; /*1D Target Status */ 191 + u8 status; /*1E SCB status */ 192 + u8 link; /*1F Link pointer, default 0xFF */ 193 + u8 sense_len; /*20 Sense Allocation Length */ 194 + u8 cdb_len; /*21 CDB Length */ 195 + u8 ident; /*22 Identify */ 196 + u8 tag_msg; /*23 Tag Message */ 197 + u8 cdb[IMAX_CDB]; /*24 SCSI CDBs */ 198 + u8 scbidx; /*3C Index for this ORCSCB */ 199 + u32 sense_addr; /*34 Sense Buffer physical Addr */ 200 + 201 + struct orc_extended_scb *escb; /*38 Extended SCB Pointer */ 202 + /* 64bit pointer or 32bit pointer + reserved ? */ 203 + #ifndef CONFIG_64BIT 204 + u8 reserved2[4]; /*3E Reserved for Driver use */ 170 205 #endif 171 - } ORC_SCB; 206 + }; 172 207 173 208 /* Opcodes of ORCSCB_Opcode */ 174 209 #define ORC_EXECSCSI 0x00 /* SCSI initiator command with residual */ ··· 210 239 Target Device Control Structure 211 240 **********************************************************************/ 212 241 213 - typedef struct ORC_Tar_Ctrl_Struc { 214 - UBYTE TCS_DrvDASD; /* 6 */ 215 - UBYTE TCS_DrvSCSI; /* 7 */ 216 - UBYTE TCS_DrvHead; /* 8 */ 217 - UWORD TCS_DrvFlags; /* 4 */ 218 - UBYTE TCS_DrvSector; /* 7 */ 219 - } ORC_TCS; 242 + struct orc_target { 243 + u8 TCS_DrvDASD; /* 6 */ 244 + u8 TCS_DrvSCSI; /* 7 */ 245 + u8 TCS_DrvHead; /* 8 */ 246 + u16 TCS_DrvFlags; /* 4 */ 247 + u8 TCS_DrvSector; /* 7 */ 248 + }; 220 249 221 250 /* Bit Definition for TCF_DrvFlags */ 222 251 #define TCS_DF_NODASD_SUPT 0x20 /* Suppress OS/2 DASD Mgr support */ ··· 226 255 /*********************************************************************** 227 256 Host Adapter Control Structure 228 257 ************************************************************************/ 229 - typedef struct ORC_Ha_Ctrl_Struc { 230 - USHORT HCS_Base; /* 00 */ 231 - UBYTE HCS_Index; /* 02 */ 232 - UBYTE HCS_Intr; /* 04 */ 233 - UBYTE HCS_SCSI_ID; /* 06 H/A SCSI ID */ 234 - UBYTE HCS_BIOS; /* 07 BIOS configuration */ 235 - 236 - UBYTE HCS_Flags; /* 0B */ 237 - UBYTE HCS_HAConfig1; /* 1B SCSI0MAXTags */ 238 - UBYTE HCS_MaxTar; /* 1B SCSI0MAXTags */ 239 - 240 - USHORT HCS_Units; /* Number of units this adapter */ 241 - USHORT HCS_AFlags; /* Adapter info. defined flags */ 242 - ULONG HCS_Timeout; /* Adapter timeout value */ 243 - ORC_SCB *HCS_virScbArray; /* 28 Virtual Pointer to SCB array */ 244 - dma_addr_t HCS_physScbArray; /* Scb Physical address */ 245 - ESCB *HCS_virEscbArray; /* Virtual pointer to ESCB Scatter list */ 246 - dma_addr_t HCS_physEscbArray; /* scatter list Physical address */ 247 - UBYTE TargetFlag[16]; /* 30 target configuration, TCF_EN_TAG */ 248 - UBYTE MaximumTags[16]; /* 40 ORC_MAX_SCBS */ 249 - UBYTE ActiveTags[16][16]; /* 50 */ 250 - ORC_TCS HCS_Tcs[16]; /* 28 */ 251 - U32 BitAllocFlag[MAX_CHANNELS][8]; /* Max STB is 256, So 256/32 */ 252 - spinlock_t BitAllocFlagLock; 258 + struct orc_host { 259 + unsigned long base; /* Base address */ 260 + u8 index; /* Index (Channel)*/ 261 + u8 scsi_id; /* H/A SCSI ID */ 262 + u8 BIOScfg; /*BIOS configuration */ 263 + u8 flags; 264 + u8 max_targets; /* SCSI0MAXTags */ 265 + struct orc_scb *scb_virt; /* Virtual Pointer to SCB array */ 266 + dma_addr_t scb_phys; /* Scb Physical address */ 267 + struct orc_extended_scb *escb_virt; /* Virtual pointer to ESCB Scatter list */ 268 + dma_addr_t escb_phys; /* scatter list Physical address */ 269 + u8 target_flag[16]; /* target configuration, TCF_EN_TAG */ 270 + u8 max_tags[16]; /* ORC_MAX_SCBS */ 271 + u32 allocation_map[MAX_CHANNELS][8]; /* Max STB is 256, So 256/32 */ 272 + spinlock_t allocation_lock; 253 273 struct pci_dev *pdev; 254 - } ORC_HCS; 274 + }; 255 275 256 276 /* Bit Definition for HCS_Flags */ 257 277 ··· 263 301 #define HCS_AF_DISABLE_RESET 0x10 /* Adapter disable reset */ 264 302 #define HCS_AF_DISABLE_ADPT 0x80 /* Adapter disable */ 265 303 266 - typedef struct _NVRAM { 304 + struct orc_nvram { 267 305 /*----------header ---------------*/ 268 - UCHAR SubVendorID0; /* 00 - Sub Vendor ID */ 269 - UCHAR SubVendorID1; /* 00 - Sub Vendor ID */ 270 - UCHAR SubSysID0; /* 02 - Sub System ID */ 271 - UCHAR SubSysID1; /* 02 - Sub System ID */ 272 - UCHAR SubClass; /* 04 - Sub Class */ 273 - UCHAR VendorID0; /* 05 - Vendor ID */ 274 - UCHAR VendorID1; /* 05 - Vendor ID */ 275 - UCHAR DeviceID0; /* 07 - Device ID */ 276 - UCHAR DeviceID1; /* 07 - Device ID */ 277 - UCHAR Reserved0[2]; /* 09 - Reserved */ 278 - UCHAR Revision; /* 0B - Revision of data structure */ 306 + u8 SubVendorID0; /* 00 - Sub Vendor ID */ 307 + u8 SubVendorID1; /* 00 - Sub Vendor ID */ 308 + u8 SubSysID0; /* 02 - Sub System ID */ 309 + u8 SubSysID1; /* 02 - Sub System ID */ 310 + u8 SubClass; /* 04 - Sub Class */ 311 + u8 VendorID0; /* 05 - Vendor ID */ 312 + u8 VendorID1; /* 05 - Vendor ID */ 313 + u8 DeviceID0; /* 07 - Device ID */ 314 + u8 DeviceID1; /* 07 - Device ID */ 315 + u8 Reserved0[2]; /* 09 - Reserved */ 316 + u8 revision; /* 0B - revision of data structure */ 279 317 /* ----Host Adapter Structure ---- */ 280 - UCHAR NumOfCh; /* 0C - Number of SCSI channel */ 281 - UCHAR BIOSConfig1; /* 0D - BIOS configuration 1 */ 282 - UCHAR BIOSConfig2; /* 0E - BIOS boot channel&target ID */ 283 - UCHAR BIOSConfig3; /* 0F - BIOS configuration 3 */ 318 + u8 NumOfCh; /* 0C - Number of SCSI channel */ 319 + u8 BIOSConfig1; /* 0D - BIOS configuration 1 */ 320 + u8 BIOSConfig2; /* 0E - BIOS boot channel&target ID */ 321 + u8 BIOSConfig3; /* 0F - BIOS configuration 3 */ 284 322 /* ----SCSI channel Structure ---- */ 285 323 /* from "CTRL-I SCSI Host Adapter SetUp menu " */ 286 - UCHAR SCSI0Id; /* 10 - Channel 0 SCSI ID */ 287 - UCHAR SCSI0Config; /* 11 - Channel 0 SCSI configuration */ 288 - UCHAR SCSI0MaxTags; /* 12 - Channel 0 Maximum tags */ 289 - UCHAR SCSI0ResetTime; /* 13 - Channel 0 Reset recovering time */ 290 - UCHAR ReservedforChannel0[2]; /* 14 - Reserved */ 324 + u8 scsi_id; /* 10 - Channel 0 SCSI ID */ 325 + u8 SCSI0Config; /* 11 - Channel 0 SCSI configuration */ 326 + u8 SCSI0MaxTags; /* 12 - Channel 0 Maximum tags */ 327 + u8 SCSI0ResetTime; /* 13 - Channel 0 Reset recovering time */ 328 + u8 ReservedforChannel0[2]; /* 14 - Reserved */ 291 329 292 330 /* ----SCSI target Structure ---- */ 293 331 /* from "CTRL-I SCSI device SetUp menu " */ 294 - UCHAR Target00Config; /* 16 - Channel 0 Target 0 config */ 295 - UCHAR Target01Config; /* 17 - Channel 0 Target 1 config */ 296 - UCHAR Target02Config; /* 18 - Channel 0 Target 2 config */ 297 - UCHAR Target03Config; /* 19 - Channel 0 Target 3 config */ 298 - UCHAR Target04Config; /* 1A - Channel 0 Target 4 config */ 299 - UCHAR Target05Config; /* 1B - Channel 0 Target 5 config */ 300 - UCHAR Target06Config; /* 1C - Channel 0 Target 6 config */ 301 - UCHAR Target07Config; /* 1D - Channel 0 Target 7 config */ 302 - UCHAR Target08Config; /* 1E - Channel 0 Target 8 config */ 303 - UCHAR Target09Config; /* 1F - Channel 0 Target 9 config */ 304 - UCHAR Target0AConfig; /* 20 - Channel 0 Target A config */ 305 - UCHAR Target0BConfig; /* 21 - Channel 0 Target B config */ 306 - UCHAR Target0CConfig; /* 22 - Channel 0 Target C config */ 307 - UCHAR Target0DConfig; /* 23 - Channel 0 Target D config */ 308 - UCHAR Target0EConfig; /* 24 - Channel 0 Target E config */ 309 - UCHAR Target0FConfig; /* 25 - Channel 0 Target F config */ 332 + u8 Target00Config; /* 16 - Channel 0 Target 0 config */ 333 + u8 Target01Config; /* 17 - Channel 0 Target 1 config */ 334 + u8 Target02Config; /* 18 - Channel 0 Target 2 config */ 335 + u8 Target03Config; /* 19 - Channel 0 Target 3 config */ 336 + u8 Target04Config; /* 1A - Channel 0 Target 4 config */ 337 + u8 Target05Config; /* 1B - Channel 0 Target 5 config */ 338 + u8 Target06Config; /* 1C - Channel 0 Target 6 config */ 339 + u8 Target07Config; /* 1D - Channel 0 Target 7 config */ 340 + u8 Target08Config; /* 1E - Channel 0 Target 8 config */ 341 + u8 Target09Config; /* 1F - Channel 0 Target 9 config */ 342 + u8 Target0AConfig; /* 20 - Channel 0 Target A config */ 343 + u8 Target0BConfig; /* 21 - Channel 0 Target B config */ 344 + u8 Target0CConfig; /* 22 - Channel 0 Target C config */ 345 + u8 Target0DConfig; /* 23 - Channel 0 Target D config */ 346 + u8 Target0EConfig; /* 24 - Channel 0 Target E config */ 347 + u8 Target0FConfig; /* 25 - Channel 0 Target F config */ 310 348 311 - UCHAR SCSI1Id; /* 26 - Channel 1 SCSI ID */ 312 - UCHAR SCSI1Config; /* 27 - Channel 1 SCSI configuration */ 313 - UCHAR SCSI1MaxTags; /* 28 - Channel 1 Maximum tags */ 314 - UCHAR SCSI1ResetTime; /* 29 - Channel 1 Reset recovering time */ 315 - UCHAR ReservedforChannel1[2]; /* 2A - Reserved */ 349 + u8 SCSI1Id; /* 26 - Channel 1 SCSI ID */ 350 + u8 SCSI1Config; /* 27 - Channel 1 SCSI configuration */ 351 + u8 SCSI1MaxTags; /* 28 - Channel 1 Maximum tags */ 352 + u8 SCSI1ResetTime; /* 29 - Channel 1 Reset recovering time */ 353 + u8 ReservedforChannel1[2]; /* 2A - Reserved */ 316 354 317 355 /* ----SCSI target Structure ---- */ 318 356 /* from "CTRL-I SCSI device SetUp menu " */ 319 - UCHAR Target10Config; /* 2C - Channel 1 Target 0 config */ 320 - UCHAR Target11Config; /* 2D - Channel 1 Target 1 config */ 321 - UCHAR Target12Config; /* 2E - Channel 1 Target 2 config */ 322 - UCHAR Target13Config; /* 2F - Channel 1 Target 3 config */ 323 - UCHAR Target14Config; /* 30 - Channel 1 Target 4 config */ 324 - UCHAR Target15Config; /* 31 - Channel 1 Target 5 config */ 325 - UCHAR Target16Config; /* 32 - Channel 1 Target 6 config */ 326 - UCHAR Target17Config; /* 33 - Channel 1 Target 7 config */ 327 - UCHAR Target18Config; /* 34 - Channel 1 Target 8 config */ 328 - UCHAR Target19Config; /* 35 - Channel 1 Target 9 config */ 329 - UCHAR Target1AConfig; /* 36 - Channel 1 Target A config */ 330 - UCHAR Target1BConfig; /* 37 - Channel 1 Target B config */ 331 - UCHAR Target1CConfig; /* 38 - Channel 1 Target C config */ 332 - UCHAR Target1DConfig; /* 39 - Channel 1 Target D config */ 333 - UCHAR Target1EConfig; /* 3A - Channel 1 Target E config */ 334 - UCHAR Target1FConfig; /* 3B - Channel 1 Target F config */ 335 - UCHAR reserved[3]; /* 3C - Reserved */ 357 + u8 Target10Config; /* 2C - Channel 1 Target 0 config */ 358 + u8 Target11Config; /* 2D - Channel 1 Target 1 config */ 359 + u8 Target12Config; /* 2E - Channel 1 Target 2 config */ 360 + u8 Target13Config; /* 2F - Channel 1 Target 3 config */ 361 + u8 Target14Config; /* 30 - Channel 1 Target 4 config */ 362 + u8 Target15Config; /* 31 - Channel 1 Target 5 config */ 363 + u8 Target16Config; /* 32 - Channel 1 Target 6 config */ 364 + u8 Target17Config; /* 33 - Channel 1 Target 7 config */ 365 + u8 Target18Config; /* 34 - Channel 1 Target 8 config */ 366 + u8 Target19Config; /* 35 - Channel 1 Target 9 config */ 367 + u8 Target1AConfig; /* 36 - Channel 1 Target A config */ 368 + u8 Target1BConfig; /* 37 - Channel 1 Target B config */ 369 + u8 Target1CConfig; /* 38 - Channel 1 Target C config */ 370 + u8 Target1DConfig; /* 39 - Channel 1 Target D config */ 371 + u8 Target1EConfig; /* 3A - Channel 1 Target E config */ 372 + u8 Target1FConfig; /* 3B - Channel 1 Target F config */ 373 + u8 reserved[3]; /* 3C - Reserved */ 336 374 /* ---------- CheckSum ---------- */ 337 - UCHAR CheckSum; /* 3F - Checksum of NVRam */ 338 - } NVRAM, *PNVRAM; 375 + u8 CheckSum; /* 3F - Checksum of NVRam */ 376 + }; 339 377 340 378 /* Bios Configuration for nvram->BIOSConfig1 */ 341 379 #define NBC_BIOSENABLE 0x01 /* BIOS enable */ ··· 369 407 #define NCC_RESET_TIME 0x0A /* SCSI RESET recovering time */ 370 408 #define NTC_DEFAULT (NTC_1GIGA | NTC_NO_WIDESYNC | NTC_DISC_ENABLE) 371 409 372 - #define ORC_RD(x,y) (UCHAR)(inb( (int)((ULONG)((ULONG)x+(UCHAR)y)) )) 373 - #define ORC_RDWORD(x,y) (short)(inl((int)((ULONG)((ULONG)x+(UCHAR)y)) )) 374 - #define ORC_RDLONG(x,y) (long)(inl((int)((ULONG)((ULONG)x+(UCHAR)y)) )) 375 - 376 - #define ORC_WR( adr,data) outb( (UCHAR)(data), (int)(adr)) 377 - #define ORC_WRSHORT(adr,data) outw( (UWORD)(data), (int)(adr)) 378 - #define ORC_WRLONG( adr,data) outl( (ULONG)(data), (int)(adr))