x86/fpu: Rename xsave.header::xstate_bv to 'xfeatures'

'xsave.header::xstate_bv' is a misnomer - what does 'bv' stand for?

It probably comes from the 'XGETBV' instruction name, but I could
not find in the Intel documentation where that abbreviation comes
from. It could mean 'bit vector' - or something else?

But how about - instead of guessing about a weird name - we named
the field in an obvious and descriptive way that tells us exactly
what it does?

So rename it to 'xfeatures', which is a bitmask of the
xfeatures that are fpstate_active in that context structure.

Eyesore like:

fpu->state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP;

is now much more readable:

fpu->state->xsave.header.xfeatures |= XSTATE_FP;

Which form is not just infinitely more readable, but is also
shorter as well.

Reviewed-by: Borislav Petkov <[e-mail]>
Cc: Andy Lutomirski <[e-mail]>
Cc: Dave Hansen <[e-mail]>
Cc: Fenghua Yu <[e-mail]>
Cc: H. Peter Anvin <[e-mail]>
Cc: Linus Torvalds <[e-mail]>
Cc: Oleg Nesterov <[e-mail]>
Cc: Peter Zijlstra <[e-mail]>
Cc: Thomas Gleixner <[e-mail]>
Signed-off-by: Ingo Molnar <[e-mail]>

arch/x86/include/asm/fpu/internal.h

···
 		/*
 		 * xsave header may indicate the init state of the FP.
 		 */
-		if (!(fpu->state->xsave.header.xstate_bv & XSTATE_FP))
+		if (!(fpu->state->xsave.header.xfeatures & XSTATE_FP))
 			return 1;
 	} else if (use_fxsr()) {
 		fpu_fxsave(fpu);

arch/x86/include/asm/fpu/types.h

···
 } __packed;
 
 struct xstate_header {
-	u64				xstate_bv;
+	u64				xfeatures;
 	u64				xcomp_bv;
 	u64				reserved[6];
 } __attribute__((packed));

arch/x86/include/asm/user.h

···
 };
 
 struct user_xstate_header {
-	__u64 xstate_bv;
+	__u64 xfeatures;
 	__u64 reserved1[2];
 	__u64 reserved2[5];
 };
···
  * particular process/thread.
  *
  * Also when the user modifies certain state FP/SSE/etc through the
- * ptrace interface, they must ensure that the header.xstate_bv
+ * ptrace interface, they must ensure that the header.xfeatures
  * bytes[512..519] of the memory layout are updated correspondingly.
  * i.e., for example when FP state is modified to a non-init state,
- * header.xstate_bv's bit 0 must be set to '1', when SSE is modified to
- * non-init state, header.xstate_bv's bit 1 must to be set to '1', etc.
+ * header.xfeatures's bit 0 must be set to '1', when SSE is modified to
+ * non-init state, header.xfeatures's bit 1 must to be set to '1', etc.
  */
 #define USER_XSTATE_FX_SW_WORDS 6
 #define USER_XSTATE_XCR0_WORD	0

arch/x86/include/uapi/asm/sigcontext.h

···
 	__u32 extended_size;	/* total size of the layout referred by
 				 * fpstate pointer in the sigcontext.
 				 */
-	__u64 xstate_bv;
+	__u64 xfeatures;
 				/* feature bit mask (including fp/sse/extended
 				 * state) that is present in the memory
 				 * layout.
···
 #endif /* !__i386__ */
 
 struct _header {
-	__u64 xstate_bv;
+	__u64 xfeatures;
 	__u64 reserved1[2];
 	__u64 reserved2[5];
 };

arch/x86/kernel/fpu/core.c

···
 	 * presence of FP and SSE state.
 	 */
 	if (cpu_has_xsave)
-		fpu->state->xsave.header.xstate_bv |= XSTATE_FPSSE;
+		fpu->state->xsave.header.xfeatures |= XSTATE_FPSSE;
 
 	return ret;
 }
···
 	 * mxcsr reserved bits must be masked to zero for security reasons.
 	 */
 	xsave->i387.mxcsr &= mxcsr_feature_mask;
-	xsave->header.xstate_bv &= xfeatures_mask;
+	xsave->header.xfeatures &= xfeatures_mask;
 	/*
 	 * These bits must be zero.
 	 */
···
 	 * presence of FP.
 	 */
 	if (cpu_has_xsave)
-		fpu->state->xsave.header.xstate_bv |= XSTATE_FP;
+		fpu->state->xsave.header.xfeatures |= XSTATE_FP;
 	return ret;
 }
 

arch/x86/kernel/fpu/xsave.c

···
 /*
  * If a processor implementation discern that a processor state component is
  * in its initialized state it may modify the corresponding bit in the
- * header.xstate_bv as '0', with out modifying the corresponding memory
+ * header.xfeatures as '0', with out modifying the corresponding memory
  * layout in the case of xsaveopt. While presenting the xstate information to
  * the user, we always ensure that the memory layout of a feature will be in
  * the init state if the corresponding header bit is zero. This is to ensure
···
 {
 	struct i387_fxsave_struct *fx = &tsk->thread.fpu.state->fxsave;
 	int feature_bit = 0x2;
-	u64 xstate_bv;
+	u64 xfeatures;
 
 	if (!fx)
 		return;
 
-	xstate_bv = tsk->thread.fpu.state->xsave.header.xstate_bv;
+	xfeatures = tsk->thread.fpu.state->xsave.header.xfeatures;
 
 	/*
 	 * None of the feature bits are in init state. So nothing else
 	 * to do for us, as the memory layout is up to date.
 	 */
-	if ((xstate_bv & xfeatures_mask) == xfeatures_mask)
+	if ((xfeatures & xfeatures_mask) == xfeatures_mask)
 		return;
 
 	/*
 	 * FP is in init state
 	 */
-	if (!(xstate_bv & XSTATE_FP)) {
+	if (!(xfeatures & XSTATE_FP)) {
 		fx->cwd = 0x37f;
 		fx->swd = 0;
 		fx->twd = 0;
···
 	/*
 	 * SSE is in init state
 	 */
-	if (!(xstate_bv & XSTATE_SSE))
+	if (!(xfeatures & XSTATE_SSE))
 		memset(&fx->xmm_space[0], 0, 256);
 
-	xstate_bv = (xfeatures_mask & ~xstate_bv) >> 2;
+	xfeatures = (xfeatures_mask & ~xfeatures) >> 2;
 
 	/*
 	 * Update all the other memory layouts for which the corresponding
 	 * header bit is in the init state.
 	 */
-	while (xstate_bv) {
-		if (xstate_bv & 0x1) {
+	while (xfeatures) {
+		if (xfeatures & 0x1) {
 			int offset = xstate_offsets[feature_bit];
 			int size = xstate_sizes[feature_bit];
 
···
 			       size);
 		}
 
-		xstate_bv >>= 1;
+		xfeatures >>= 1;
 		feature_bit++;
 	}
 }
···
 {
 	struct xsave_struct __user *x = buf;
 	struct _fpx_sw_bytes *sw_bytes;
-	u32 xstate_bv;
+	u32 xfeatures;
 	int err;
 
 	/* Setup the bytes not touched by the [f]xsave and reserved for SW. */
···
 	err |= __put_user(FP_XSTATE_MAGIC2, (__u32 *)(buf + xstate_size));
 
 	/*
-	 * Read the xstate_bv which we copied (directly from the cpu or
+	 * Read the xfeatures which we copied (directly from the cpu or
 	 * from the state in task struct) to the user buffers.
 	 */
-	err |= __get_user(xstate_bv, (__u32 *)&x->header.xstate_bv);
+	err |= __get_user(xfeatures, (__u32 *)&x->header.xfeatures);
 
 	/*
 	 * For legacy compatible, we always set FP/SSE bits in the bit
 	 * vector while saving the state to the user context. This will
 	 * enable us capturing any changes(during sigreturn) to
 	 * the FP/SSE bits by the legacy applications which don't touch
-	 * xstate_bv in the xsave header.
+	 * xfeatures in the xsave header.
 	 *
-	 * xsave aware apps can change the xstate_bv in the xsave
+	 * xsave aware apps can change the xfeatures in the xsave
 	 * header as well as change any contents in the memory layout.
 	 * xrestore as part of sigreturn will capture all the changes.
 	 */
-	xstate_bv |= XSTATE_FPSSE;
+	xfeatures |= XSTATE_FPSSE;
 
-	err |= __put_user(xstate_bv, (__u32 *)&x->header.xstate_bv);
+	err |= __put_user(xfeatures, (__u32 *)&x->header.xfeatures);
 
 	return err;
 }
···
 static inline void
 sanitize_restored_xstate(struct task_struct *tsk,
 			 struct user_i387_ia32_struct *ia32_env,
-			 u64 xstate_bv, int fx_only)
+			 u64 xfeatures, int fx_only)
 {
 	struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave;
 	struct xstate_header *header = &xsave->header;
···
 		 * layout and not enabled by the OS.
 		 */
 		if (fx_only)
-			header->xstate_bv = XSTATE_FPSSE;
+			header->xfeatures = XSTATE_FPSSE;
 		else
-			header->xstate_bv &= (xfeatures_mask & xstate_bv);
+			header->xfeatures &= (xfeatures_mask & xfeatures);
 	}
 
 	if (use_fxsr()) {
···
 	struct task_struct *tsk = current;
 	struct fpu *fpu = &tsk->thread.fpu;
 	int state_size = xstate_size;
-	u64 xstate_bv = 0;
+	u64 xfeatures = 0;
 	int fx_only = 0;
 
 	ia32_fxstate &= (config_enabled(CONFIG_X86_32) ||
···
 			fx_only = 1;
 		} else {
 			state_size = fx_sw_user.xstate_size;
-			xstate_bv = fx_sw_user.xstate_bv;
+			xfeatures = fx_sw_user.xfeatures;
 		}
 	}
 
···
 			fpstate_init(fpu);
 			err = -1;
 		} else {
-			sanitize_restored_xstate(tsk, &env, xstate_bv, fx_only);
+			sanitize_restored_xstate(tsk, &env, xfeatures, fx_only);
 		}
 
 		fpu->fpstate_active = 1;
···
 		 * state to the registers directly (with exceptions handled).
 		 */
 		user_fpu_begin();
-		if (restore_user_xstate(buf_fx, xstate_bv, fx_only)) {
+		if (restore_user_xstate(buf_fx, xfeatures, fx_only)) {
 			fpu_reset_state(fpu);
 			return -1;
 		}
···
 
 	fx_sw_reserved.magic1 = FP_XSTATE_MAGIC1;
 	fx_sw_reserved.extended_size = size;
-	fx_sw_reserved.xstate_bv = xfeatures_mask;
+	fx_sw_reserved.xfeatures = xfeatures_mask;
 	fx_sw_reserved.xstate_size = xstate_size;
 
 	if (config_enabled(CONFIG_IA32_EMULATION)) {
···
 	if (cpu_has_xsaves) {
 		init_xstate_buf->header.xcomp_bv =
 						(u64)1 << 63 | xfeatures_mask;
-		init_xstate_buf->header.xstate_bv = xfeatures_mask;
+		init_xstate_buf->header.xfeatures = xfeatures_mask;
 	}
 
 	/*

arch/x86/kvm/x86.c

···
 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
 {
 	struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
-	u64 xstate_bv = xsave->header.xstate_bv;
+	u64 xstate_bv = xsave->header.xfeatures;
 	u64 valid;
 
 	/*
···
 	memcpy(xsave, src, XSAVE_HDR_OFFSET);
 
 	/* Set XSTATE_BV and possibly XCOMP_BV.  */
-	xsave->header.xstate_bv = xstate_bv;
+	xsave->header.xfeatures = xstate_bv;
 	if (cpu_has_xsaves)
 		xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;