Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

clk: qcom: Enable FSM mode for votable alpha PLLs

The votable alpha PLLs need to have the fsm mode enabled as part
of the initialization. The sequence seems to be the same as used
by clk-pll, so move the function which does this into a common
place and reuse it for the clk-alpha-pll

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

authored by

Rajendra Nayak and committed by
Stephen Boyd
400d9fda 31256f48

+38 -28
+4
drivers/clk/qcom/clk-alpha-pll.c
··· 18 18 #include <linux/delay.h> 19 19 20 20 #include "clk-alpha-pll.h" 21 + #include "common.h" 21 22 22 23 #define PLL_MODE 0x00 23 24 # define PLL_OUTCTRL BIT(0) ··· 137 136 mask |= config->vco_mask; 138 137 139 138 regmap_update_bits(regmap, off + PLL_USER_CTL, mask, val); 139 + 140 + if (pll->flags & SUPPORTS_FSM_MODE) 141 + qcom_pll_set_fsm_mode(regmap, off + PLL_MODE, 6, 0); 140 142 } 141 143 142 144 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
+1
drivers/clk/qcom/clk-alpha-pll.h
··· 36 36 size_t num_vco; 37 37 #define SUPPORTS_OFFLINE_REQ BIT(0) 38 38 #define SUPPORTS_16BIT_ALPHA BIT(1) 39 + #define SUPPORTS_FSM_MODE BIT(2) 39 40 u8 flags; 40 41 41 42 struct clk_regmap clkr;
+3 -28
drivers/clk/qcom/clk-pll.c
··· 23 23 #include <asm/div64.h> 24 24 25 25 #include "clk-pll.h" 26 + #include "common.h" 26 27 27 28 #define PLL_OUTCTRL BIT(0) 28 29 #define PLL_BYPASSNL BIT(1) 29 30 #define PLL_RESET_N BIT(2) 30 - #define PLL_LOCK_COUNT_SHIFT 8 31 - #define PLL_LOCK_COUNT_MASK 0x3f 32 - #define PLL_BIAS_COUNT_SHIFT 14 33 - #define PLL_BIAS_COUNT_MASK 0x3f 34 - #define PLL_VOTE_FSM_ENA BIT(20) 35 - #define PLL_VOTE_FSM_RESET BIT(21) 36 31 37 32 static int clk_pll_enable(struct clk_hw *hw) 38 33 { ··· 223 228 }; 224 229 EXPORT_SYMBOL_GPL(clk_pll_vote_ops); 225 230 226 - static void 227 - clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count) 228 - { 229 - u32 val; 230 - u32 mask; 231 - 232 - /* De-assert reset to FSM */ 233 - regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0); 234 - 235 - /* Program bias count and lock count */ 236 - val = 1 << PLL_BIAS_COUNT_SHIFT | lock_count << PLL_LOCK_COUNT_SHIFT; 237 - mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT; 238 - mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT; 239 - regmap_update_bits(regmap, pll->mode_reg, mask, val); 240 - 241 - /* Enable PLL FSM voting */ 242 - regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_ENA, 243 - PLL_VOTE_FSM_ENA); 244 - } 245 - 246 231 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap, 247 232 const struct pll_config *config) 248 233 { ··· 255 280 { 256 281 clk_pll_configure(pll, regmap, config); 257 282 if (fsm_mode) 258 - clk_pll_set_fsm_mode(pll, regmap, 8); 283 + qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8); 259 284 } 260 285 EXPORT_SYMBOL_GPL(clk_pll_configure_sr); 261 286 ··· 264 289 { 265 290 clk_pll_configure(pll, regmap, config); 266 291 if (fsm_mode) 267 - clk_pll_set_fsm_mode(pll, regmap, 0); 292 + qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0); 268 293 } 269 294 EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp); 270 295
+21
drivers/clk/qcom/common.c
··· 74 74 } 75 75 EXPORT_SYMBOL_GPL(qcom_cc_map); 76 76 77 + void 78 + qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count) 79 + { 80 + u32 val; 81 + u32 mask; 82 + 83 + /* De-assert reset to FSM */ 84 + regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0); 85 + 86 + /* Program bias count and lock count */ 87 + val = bias_count << PLL_BIAS_COUNT_SHIFT | 88 + lock_count << PLL_LOCK_COUNT_SHIFT; 89 + mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT; 90 + mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT; 91 + regmap_update_bits(map, reg, mask, val); 92 + 93 + /* Enable PLL FSM voting */ 94 + regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA); 95 + } 96 + EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode); 97 + 77 98 static void qcom_cc_del_clk_provider(void *data) 78 99 { 79 100 of_clk_del_provider(data);
+9
drivers/clk/qcom/common.h
··· 22 22 struct clk_hw; 23 23 struct parent_map; 24 24 25 + #define PLL_LOCK_COUNT_SHIFT 8 26 + #define PLL_LOCK_COUNT_MASK 0x3f 27 + #define PLL_BIAS_COUNT_SHIFT 14 28 + #define PLL_BIAS_COUNT_MASK 0x3f 29 + #define PLL_VOTE_FSM_ENA BIT(20) 30 + #define PLL_VOTE_FSM_RESET BIT(21) 31 + 25 32 struct qcom_cc_desc { 26 33 const struct regmap_config *config; 27 34 struct clk_regmap **clks; ··· 41 34 42 35 extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, 43 36 unsigned long rate); 37 + extern void 38 + qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count); 44 39 extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, 45 40 u8 src); 46 41