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Merge tag 'amd-drm-fixes-5.15-2021-09-29' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes

amd-drm-fixes-5.15-2021-09-29:

amdgpu:
- gart pin count fix
- eDP flicker fix
- GFX9 MQD fix
- Display fixes
- Tiling flags fix for pre-GFX9
- SDMA resume fix for S0ix

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210930023013.5207-1-alexander.deucher@amd.com

Daniel Vetter 3ff43f9d abb7700d

+53 -11
+31
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
··· 837 837 return 0; 838 838 } 839 839 840 + /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */ 841 + static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) 842 + { 843 + u64 micro_tile_mode; 844 + 845 + /* Zero swizzle mode means linear */ 846 + if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0) 847 + return 0; 848 + 849 + micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE); 850 + switch (micro_tile_mode) { 851 + case 0: /* DISPLAY */ 852 + case 3: /* RENDER */ 853 + return 0; 854 + default: 855 + drm_dbg_kms(afb->base.dev, 856 + "Micro tile mode %llu not supported for scanout\n", 857 + micro_tile_mode); 858 + return -EINVAL; 859 + } 860 + } 861 + 840 862 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp, 841 863 unsigned int *width, unsigned int *height) 842 864 { ··· 1125 1103 const struct drm_mode_fb_cmd2 *mode_cmd, 1126 1104 struct drm_gem_object *obj) 1127 1105 { 1106 + struct amdgpu_device *adev = drm_to_adev(dev); 1128 1107 int ret, i; 1129 1108 1130 1109 /* ··· 1144 1121 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface); 1145 1122 if (ret) 1146 1123 return ret; 1124 + 1125 + if (!dev->mode_config.allow_fb_modifiers) { 1126 + drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, 1127 + "GFX9+ requires FB check based on format modifier\n"); 1128 + ret = check_tiling_flags_gfx6(rfb); 1129 + if (ret) 1130 + return ret; 1131 + } 1147 1132 1148 1133 if (dev->mode_config.allow_fb_modifiers && 1149 1134 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
+1 -1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 3599 3599 3600 3600 /* set static priority for a queue/ring */ 3601 3601 gfx_v9_0_mqd_set_priority(ring, mqd); 3602 - mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); 3602 + mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); 3603 3603 3604 3604 /* map_queues packet doesn't need activate the queue, 3605 3605 * so only kiq need set this field.
+2 -1
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
··· 1098 1098 { 1099 1099 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1100 1100 1101 + gmc_v10_0_gart_disable(adev); 1102 + 1101 1103 if (amdgpu_sriov_vf(adev)) { 1102 1104 /* full access mode, so don't touch any GMC register */ 1103 1105 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); ··· 1108 1106 1109 1107 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1110 1108 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1111 - gmc_v10_0_gart_disable(adev); 1112 1109 1113 1110 return 0; 1114 1111 }
+2 -1
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
··· 1794 1794 { 1795 1795 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1796 1796 1797 + gmc_v9_0_gart_disable(adev); 1798 + 1797 1799 if (amdgpu_sriov_vf(adev)) { 1798 1800 /* full access mode, so don't touch any GMC register */ 1799 1801 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); ··· 1804 1802 1805 1803 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1806 1804 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1807 - gmc_v9_0_gart_disable(adev); 1808 1805 1809 1806 return 0; 1810 1807 }
+8
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
··· 868 868 msleep(1000); 869 869 } 870 870 871 + /* TODO: check whether can submit a doorbell request to raise 872 + * a doorbell fence to exit gfxoff. 873 + */ 874 + if (adev->in_s0ix) 875 + amdgpu_gfx_off_ctrl(adev, false); 876 + 871 877 sdma_v5_2_soft_reset(adev); 872 878 /* unhalt the MEs */ 873 879 sdma_v5_2_enable(adev, true); ··· 882 876 883 877 /* start the gfx rings and rlc compute queues */ 884 878 r = sdma_v5_2_gfx_resume(adev); 879 + if (adev->in_s0ix) 880 + amdgpu_gfx_off_ctrl(adev, true); 885 881 if (r) 886 882 return r; 887 883 r = sdma_v5_2_rlc_resume(adev);
+2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 1115 1115 1116 1116 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1117 1117 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1118 + init_data.asic_id.chip_id = adev->pdev->device; 1118 1119 1119 1120 init_data.asic_id.vram_width = adev->gmc.vram_width; 1120 1121 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ ··· 1720 1719 linear_lut[i] = 0xFFFF * i / 15; 1721 1720 1722 1721 params.set = 0; 1722 + params.backlight_ramping_override = false; 1723 1723 params.backlight_ramping_start = 0xCCCC; 1724 1724 params.backlight_ramping_reduction = 0xCCCCCCCC; 1725 1725 params.backlight_lut_array_size = 16;