Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6

* 'master' of master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6:
Blackfin arch: add proper const volatile to addr argument to the read functions
Blackfin arch: Add definition of dma_mapping_error
Blackfin arch: move cond_syscall() behind __KERNEL__ like all other architectures
Blackfin arch: match kernel startup messaage with new linker script
Blackfin arch: add missing braces around array bfin serial init
Blackfin arch: update printk to use KERN_EMERG and reformat crash output
Blackfin arch: update ANOMALY handling

arch/blackfin/kernel/setup.c

···
 
 	printk(KERN_INFO "Memory map:\n"
 	       KERN_INFO "  text      = 0x%p-0x%p\n"
-	       KERN_INFO "  init      = 0x%p-0x%p\n"
+	       KERN_INFO "  rodata    = 0x%p-0x%p\n"
 	       KERN_INFO "  data      = 0x%p-0x%p\n"
-	       KERN_INFO "  stack     = 0x%p-0x%p\n"
+	       KERN_INFO "    stack   = 0x%p-0x%p\n"
+	       KERN_INFO "  init      = 0x%p-0x%p\n"
 	       KERN_INFO "  bss       = 0x%p-0x%p\n"
 	       KERN_INFO "  available = 0x%p-0x%p\n"
 #ifdef CONFIG_MTD_UCLINUX
···
 	       KERN_INFO "  DMA Zone  = 0x%p-0x%p\n"
 #endif
 	       , _stext, _etext,
-	       __init_begin, __init_end,
+	       __start_rodata, __end_rodata,
 	       _sdata, _edata,
 	       (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000),
+	       __init_begin, __init_end,
 	       __bss_start, __bss_stop,
 	       (void*)_ramstart, (void*)memory_end
 #ifdef CONFIG_MTD_UCLINUX

arch/blackfin/kernel/traps.c

···
 	unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE;
 
 #ifdef CONFIG_KGDB
-# define CHK_DEBUGGER_TRAP() do { CHK_DEBUGGER(trapnr, sig, info.si_code, fp,); } while (0)
-# define CHK_DEBUGGER_TRAP_MAYBE() do { if (kgdb_connected) CHK_DEBUGGER_TRAP(); } while (0)
+# define CHK_DEBUGGER_TRAP() \
+	do { \
+		CHK_DEBUGGER(trapnr, sig, info.si_code, fp); \
+	} while (0)
+# define CHK_DEBUGGER_TRAP_MAYBE() \
+	do { \
+		if (kgdb_connected) \
+			CHK_DEBUGGER_TRAP(); \
+	} while (0)
 #else
 # define CHK_DEBUGGER_TRAP() do { } while (0)
 # define CHK_DEBUGGER_TRAP_MAYBE() do { } while (0)
···
 		info.si_code = ILL_CPLB_MULHIT;
 #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
 		sig = SIGSEGV;
-		printk(KERN_EMERG "\n\nNULL pointer access (probably)\n");
+		printk(KERN_EMERG "\n"
+			KERN_EMERG "NULL pointer access (probably)\n");
 #else
 		sig = SIGILL;
 		printk(KERN_EMERG EXC_0x27);
···
 		if (current->mm) {
 			fp->pc = current->mm->start_code;
 		} else {
-			printk(KERN_EMERG "I can't return to memory that doesn't exist - bad things happen\n");
+			printk(KERN_EMERG
+				"I can't return to memory that doesn't exist"
+				" - bad things happen\n");
 			panic("Help - I've fallen and can't get up\n");
 		}
 	}
···
 void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
 {
 	if (current->pid) {
-		printk("\nCURRENT PROCESS:\n\n");
-		printk("COMM=%s PID=%d\n", current->comm, current->pid);
+		printk(KERN_EMERG "\n" KERN_EMERG "CURRENT PROCESS:\n"
+			KERN_EMERG "\n");
+		printk(KERN_EMERG "COMM=%s PID=%d\n",
+			current->comm, current->pid);
 	} else {
 		printk
-		    ("\nNo Valid pid - Either things are really messed up, or you are in the kernel\n");
+		    (KERN_EMERG "\n" KERN_EMERG
+		     "No Valid pid - Either things are really messed up,"
+		     " or you are in the kernel\n");
 	}
 
 	if (current->mm) {
-		printk("TEXT = 0x%p-0x%p  DATA = 0x%p-0x%p\n"
+		printk(KERN_EMERG "TEXT = 0x%p-0x%p  DATA = 0x%p-0x%p\n"
 		       "BSS = 0x%p-0x%p   USER-STACK = 0x%p\n\n",
 		       (void*)current->mm->start_code,
 		       (void*)current->mm->end_code,
···
 		       (void*)current->mm->start_stack);
 	}
 
-	printk("return address: 0x%p; contents of [PC-16...PC+8]:\n", retaddr);
+	printk(KERN_EMERG "return address: [0x%p]; contents of:", retaddr);
 	if (retaddr != 0 && retaddr <= (void*)physical_mem_end
 #if L1_CODE_LENGTH != 0
 	    /* FIXME: Copy the code out of L1 Instruction SRAM through dma
···
 	         && retaddr < (void*)(L1_CODE_START + L1_CODE_LENGTH))
 #endif
 	) {
-		int i = 0;
+		int i = ((unsigned int)retaddr & 0xFFFFFFF0) - 32;
 		unsigned short x = 0;
-		for (i = -16; i < 8; i++) {
-			if (get_user(x, (unsigned short *)retaddr + i))
+		for (; i < ((unsigned int)retaddr & 0xFFFFFFF0 ) + 32 ;
+			i += 2) {
+			if ( !(i & 0xF) )
+				printk(KERN_EMERG "\n" KERN_EMERG
+					"0x%08x: ", i);
+
+			if (get_user(x, (unsigned short *)i))
 				break;
 #ifndef CONFIG_DEBUG_HWERR
 			/* If one of the last few instructions was a STI
···
 			 * and we just noticed
 			 */
 			if (x >= 0x0040 && x <= 0x0047 && i <= 0)
-				panic("\n\nWARNING : You should reconfigure the kernel to turn on\n"
-					" 'Hardware error interrupt debugging'\n"
-					" The rest of this error is meanless\n");
+				panic("\n\nWARNING : You should reconfigure"
+					" the kernel to turn on\n"
+					" 'Hardware error interrupt"
+					" debugging'\n"
+					" The rest of this error"
+					" is meanless\n");
 #endif
-
-			if (i == -8)
-				printk("\n");
-			if (i == 0)
-				printk("X\n");
-			printk("%04x ", x);
+			if ( i == (unsigned int)retaddr )
+				printk("[%04x]", x);
+			else
+				printk(" %04x ", x);
 		}
+		printk("\n" KERN_EMERG "\n");
 	} else
-		printk("Cannot look at the [PC] for it is in unreadable L1 SRAM - sorry\n");
+		printk(KERN_EMERG
+			"Cannot look at the [PC] for it is"
+			"in unreadable L1 SRAM - sorry\n");
 
-	printk("\n\n");
 
-	printk("RETE:  %08lx  RETN: %08lx  RETX: %08lx  RETS: %08lx\n",
-	       fp->rete, fp->retn, fp->retx, fp->rets);
-	printk("IPEND: %04lx  SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
-	printk("SEQSTAT: %08lx    SP: %08lx\n", (long)fp->seqstat, (long)fp);
-	printk("R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n",
-	       fp->r0, fp->r1, fp->r2, fp->r3);
-	printk("R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n",
-	       fp->r4, fp->r5, fp->r6, fp->r7);
-	printk("P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n",
-	       fp->p0, fp->p1, fp->p2, fp->p3);
-	printk("P4: %08lx    P5: %08lx    FP: %08lx\n", fp->p4, fp->p5, fp->fp);
-	printk("A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n",
-	       fp->a0w, fp->a0x, fp->a1w, fp->a1x);
+	printk(KERN_EMERG
+		"RETE:  %08lx  RETN: %08lx  RETX: %08lx  RETS: %08lx\n",
+		fp->rete, fp->retn, fp->retx, fp->rets);
+	printk(KERN_EMERG "IPEND: %04lx  SYSCFG: %04lx\n",
+		fp->ipend, fp->syscfg);
+	printk(KERN_EMERG "SEQSTAT: %08lx    SP: %08lx\n",
+		(long)fp->seqstat, (long)fp);
+	printk(KERN_EMERG "R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n",
+		fp->r0, fp->r1, fp->r2, fp->r3);
+	printk(KERN_EMERG "R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n",
+		fp->r4, fp->r5, fp->r6, fp->r7);
+	printk(KERN_EMERG "P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n",
+		fp->p0, fp->p1, fp->p2, fp->p3);
+	printk(KERN_EMERG
+		"P4: %08lx    P5: %08lx    FP: %08lx\n",
+		fp->p4, fp->p5, fp->fp);
+	printk(KERN_EMERG
+		"A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n",
+		fp->a0w, fp->a0x, fp->a1w, fp->a1x);
 
-	printk("LB0: %08lx  LT0: %08lx  LC0: %08lx\n", fp->lb0, fp->lt0,
-	       fp->lc0);
-	printk("LB1: %08lx  LT1: %08lx  LC1: %08lx\n", fp->lb1, fp->lt1,
-	       fp->lc1);
-	printk("B0: %08lx  L0: %08lx  M0: %08lx  I0: %08lx\n", fp->b0, fp->l0,
-	       fp->m0, fp->i0);
-	printk("B1: %08lx  L1: %08lx  M1: %08lx  I1: %08lx\n", fp->b1, fp->l1,
-	       fp->m1, fp->i1);
-	printk("B2: %08lx  L2: %08lx  M2: %08lx  I2: %08lx\n", fp->b2, fp->l2,
-	       fp->m2, fp->i2);
-	printk("B3: %08lx  L3: %08lx  M3: %08lx  I3: %08lx\n", fp->b3, fp->l3,
-	       fp->m3, fp->i3);
+	printk(KERN_EMERG "LB0: %08lx  LT0: %08lx  LC0: %08lx\n",
+		fp->lb0, fp->lt0, fp->lc0);
+	printk(KERN_EMERG "LB1: %08lx  LT1: %08lx  LC1: %08lx\n",
+		fp->lb1, fp->lt1, fp->lc1);
+	printk(KERN_EMERG "B0: %08lx  L0: %08lx  M0: %08lx  I0: %08lx\n",
+		fp->b0, fp->l0, fp->m0, fp->i0);
+	printk(KERN_EMERG "B1: %08lx  L1: %08lx  M1: %08lx  I1: %08lx\n",
+		fp->b1, fp->l1, fp->m1, fp->i1);
+	printk(KERN_EMERG "B2: %08lx  L2: %08lx  M2: %08lx  I2: %08lx\n",
+		fp->b2, fp->l2, fp->m2, fp->i2);
+	printk(KERN_EMERG "B3: %08lx  L3: %08lx  M3: %08lx  I3: %08lx\n",
+		fp->b3, fp->l3, fp->m3, fp->i3);
 
-	printk("\nUSP: %08lx   ASTAT: %08lx\n", rdusp(), fp->astat);
+	printk(KERN_EMERG "\n" KERN_EMERG "USP: %08lx   ASTAT: %08lx\n",
+		rdusp(), fp->astat);
 	if ((long)fp->seqstat & SEQSTAT_EXCAUSE) {
-		printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void*)bfin_read_DCPLB_FAULT_ADDR());
-		printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void*)bfin_read_ICPLB_FAULT_ADDR());
+		printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n",
+			(void *)bfin_read_DCPLB_FAULT_ADDR());
+		printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n",
+			(void *)bfin_read_ICPLB_FAULT_ADDR());
 	}
 
 	printk("\n\n");

arch/blackfin/lib/memcmp.S

···
 
 	LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1;
 .Lquad_loop_s:
+#ifdef ANOMALY_05000202
+	R0 = [P0++];
+	R1 = [I0++];
+#else
 	MNOP || R0 = [P0++] || R1 = [I0++];
+#endif
 	CC = R0 == R1;
 	IF !CC JUMP .Lquad_different;
 .Lquad_loop_e:

arch/blackfin/lib/memcpy.S

···
 .Lmore_than_seven:
 	/* There's at least eight bytes to copy. */
 	P2 += -1;	/* because we unroll one iteration */
-	LSETUP(.Lword_loop, .Lword_loop) LC0=P2;
+	LSETUP(.Lword_loops, .Lword_loope) LC0=P2;
 	R0 = R1;
 	I1 = P1;
 	R3 = [I1++];
-.Lword_loop:
+#ifdef ANOMALY_05000202
+.Lword_loops:
+	[P0++] = R3;
+.Lword_loope:
+	R3 = [I1++];
+#else
+.Lword_loops:
+.Lword_loope:
 	MNOP || [P0++] = R3 || R3 = [I1++];
-
+#endif
 	[P0++] = R3;
 	/* Any remaining bytes to copy? */
 	R3 = 0x3;

arch/blackfin/lib/memmove.S

···
 	P2 = R2;                  /* set remainder */
 	R1 = [I0++];
 
-	LSETUP (.Lquad_loop, .Lquad_loop) LC0=P1;
-.Lquad_loop: MNOP || [P0++] = R1 || R1 = [I0++];
+	LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1;
+#ifdef ANOMALY_05000202
+.Lquad_loops:
+	[P0++] = R1;
+.Lquad_loope:
+	R1 = [I0++];
+#else
+.Lquad_loops:
+.Lquad_loope:
+	 MNOP || [P0++] = R1 || R1 = [I0++];
+#endif
 	[P0++] = R1;
 
 	CC = P2 == 0;             /* any remaining bytes? */
···
 	R1 = B[P3--] (Z);
 	CC = P2 == 0;
 	IF CC JUMP .Lno_loop;
+#ifdef ANOMALY_05000245
+	NOP;
+	NOP;
+#endif
 	LSETUP (.Lol_s, .Lol_e) LC0 = P2;
 .Lol_s:    B[P0--] = R1;
 .Lol_e:    R1 = B[P3--] (Z);

arch/blackfin/mach-common/cache.S

···
 	R2 = R0 & R2;
 	P0 = R2;
 	P1 = R1;
-	CSYNC;
+	CSYNC(R3);
 	IFLUSH [P0];
 1:
 	IFLUSH [P0++];
 	CC = P0 < P1 (iu);
 	IF CC JUMP 1b (bp);
 	IFLUSH [P0];
-	SSYNC;
+	SSYNC(R3);
 	RTS;
 ENDPROC(_blackfin_icache_flush_range)
 
···
 	R2 = R0 & R2;
 	P0 = R2;
 	P1 = R1;
-	CSYNC;
+	CSYNC(R3);
 	IFLUSH [P0];
 1:
 	FLUSH [P0];
···
 	IF CC JUMP 1b (bp);
 	IFLUSH [P0];
 	FLUSH [P0];
-	SSYNC;
+	SSYNC(R3);
 	RTS;
 ENDPROC(_blackfin_icache_dcache_flush_range)
 
···
 	R2 = R0 & R2;
 	P0 = R2;
 	P1 = R1;
-	CSYNC;
+	CSYNC(R3);
 	FLUSHINV[P0];
 1:
 	FLUSHINV[P0++];
···
 	 * so do one more.
 	 */
 	FLUSHINV[P0];
-	SSYNC;
+	SSYNC(R3);
 	RTS;
 ENDPROC(_blackfin_dcache_invalidate_range)
 
···
 	R2 = R0 & R2;
 	P0 = R2;
 	P1 = R1;
-	CSYNC;
+	CSYNC(R3);
 	FLUSH[P0];
 1:
 	FLUSH[P0++];
···
 	 * one more.
 	 */
 	FLUSH[P0];
-	SSYNC;
+	SSYNC(R3);
 	RTS;
 ENDPROC(_blackfin_dcache_flush_range)
 
 ENTRY(_blackfin_dflush_page)
 	P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
 	P0 = R0;
-	CSYNC;
+	CSYNC(R3);
 	FLUSH[P0];
 	LSETUP (.Lfl1, .Lfl1) LC0 = P1;
 .Lfl1:	FLUSH [P0++];
-	SSYNC;
+	SSYNC(R3);
 	RTS;
 ENDPROC(_blackfin_dflush_page)

arch/blackfin/mach-common/interrupt.S

···
 	fp = 0;
 #endif
 
-#ifdef	ANOMALY_05000283
+#if defined (ANOMALY_05000283) || defined (ANOMALY_05000315)
 	cc = r7 == r7;
 	p5.h = 0xffc0;
 	p5.l = 0x0014;

include/asm-blackfin/blackfin.h

···
 #elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
 static inline void SSYNC (void)
 {
-	__builtin_bfin_ssync();
+	__asm__ __volatile__ ("nop; nop; nop;\n\t"
+			"ssync;\n\t"
+			::);
 }
 #elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
 static inline void SSYNC (void)
···
 #elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
 static inline void CSYNC (void)
 {
-	__builtin_bfin_csync();
+	__asm__ __volatile__ ("nop; nop; nop;\n\t"
+			"ssync;\n\t"
+			::);
 }
 #elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
 static inline void CSYNC (void)
···
 	__asm__ __volatile__ ("csync;\n\t");
 }
 #endif
+
+#else  /* __ASSEMBLY__ */
+
+/* SSYNC & CSYNC implementations for assembly files */
+
+#define ssync(x) SSYNC(x)
+#define csync(x) CSYNC(x)
+
+#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
+#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
+
+#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
+#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
+#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
+
+#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+#define SSYNC(scratch) nop; nop; nop; SSYNC;
+#define CSYNC(scratch) nop; nop; nop; CSYNC;
+
+#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
+#define SSYNC(scratch) SSYNC;
+#define CSYNC(scratch) CSYNC;
+
+#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
 
 #endif /* __ASSEMBLY__ */
 

include/asm-blackfin/dma-mapping.h

···
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
 
+#define dma_mapping_error
+
 /*
  * Map a single buffer of the indicated size for DMA in streaming mode.
  * The 32-bit bus address to use is returned.

include/asm-blackfin/io.h

···
  */
 #ifndef __ASSEMBLY__
 
-static inline unsigned char readb(void __iomem *addr)
+static inline unsigned char readb(const volatile void __iomem *addr)
 {
 	unsigned int val;
 	int tmp;
···
 	return (unsigned char) val;
 }
 
-static inline unsigned short readw(void __iomem *addr)
+static inline unsigned short readw(const volatile void __iomem *addr)
 {
 	unsigned int val;
 	int tmp;
···
 	return (unsigned short) val;
 }
 
-static inline unsigned int readl(void __iomem *addr)
+static inline unsigned int readl(const volatile void __iomem *addr)
 {
 	unsigned int val;
 	int tmp;

include/asm-blackfin/mach-bf533/anomaly.h

···
 #endif
 
 /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
-#if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
+#if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \
+		|| defined(CONFIG_BF_REV_0_3))
 #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
                             slot1 and store of a P register in slot 2 is not
                             supported */
···
                             control */
 #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
                             killed in a particular stage*/
+#define ANOMALY_05000311 /* Erroneous flag pin operations under specific
+			    sequences */
 #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
 			    registers are interrupted */
-#define ANOMALY_05000311 /* Erroneous flag pin operations under specific sequences*/
-
-#endif
+#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer  */
+#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On
+			  *  Next System MMR Access */
+#define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V
+			  *  and 1.15V Not Allowed for LQFP Packages */
+#endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
 
 /* These issues only occur on 0.3 or 0.4 BF533 */
 #if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
···
                             internal voltage regulator (VDDint) to increase. */
 #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
                             internal voltage regulator (VDDint) to decrease */
-#endif
+#endif /* issues only occur on 0.3 or 0.4 BF533 */
 
 /* These issues are only on 0.4 silicon */
 #if (defined(CONFIG_BF_REV_0_4))
 #define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
 #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
                             (TDM) */
-#endif
+#endif /* issues are only on 0.4 silicon */
 
 /* These issues are only on 0.3 silicon */
 #if defined(CONFIG_BF_REV_0_3)
···
 #define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
                             Sync Transmit Mode */
 #define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
+#endif /* only on 0.3 silicon */
+
+#if defined(CONFIG_BF_REV_0_2)
+#define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not
+			  *  supported */
+#define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at
+			  *  power on */
+#define ANOMALY_05000116 /* Trace Buffers may record discontinuities into
+			  *  emulation mode and/or exception, NMI, reset
+			  *  handlers */
+#define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be
+			  *  incorrect if data cache or DMA is active */
+#define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1,
+			  *  or 1:1 */
+#define ANOMALY_05000125 /* Erroneous exception when enabling cache */
+#define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect
+			  *  during booting */
+#define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */
+#define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill
+			  * block in the loader file */
+#define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an
+			  *  overflow */
+#define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence
+			  *  of consecutive dual dag events */
+#define ANOMALY_05000142 /* Interrupts may be lost when a programmable input
+			  *  flag is configured to be edge sensitive */
+#define ANOMALY_05000143 /* A read from external memory may return a wrong
+			  *  value with data cache enabled */
+#define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing
+			  *  external memory */
+#define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to
+			  *  generate a waveform from PPI_CLK */
+#define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor
+			  *  chain */
+#define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA
+			  *  Error */
+#define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory
+			  *  device, the upper 8-bits of each word must be
+			  *  0x00 */
+#define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */
+#define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode
+			  *  outside of valid channels */
+#define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a
+			  *  certain PPI mode is in use */
+#define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to
+			  *  the next system MMR access thinking it should be
+			  *  32-bit. */
+#define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame
+			  *  sync in certain conditions */
+#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
+#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost
+			  *  write-through cache data writes */
+#define ANOMALY_05000173 /* DMA vs Core accesses to external memory */
+#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
+#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
+#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
+			  *  accumulator saturation */
+#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
+			  *  registers */
+#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
+#define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in
+			  *  Transmit Modes */
+#define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs
+			  *  POLC */
+#define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */
+
 #endif
 
 #endif /*  _MACH_ANOMALY_H_ */

include/asm-blackfin/mach-bf533/bfin_serial_5xx.h

···
 };
 
 struct bfin_serial_res bfin_serial_resource[] = {
+	{
 	0xFFC00400,
 	IRQ_UART_RX,
 #ifdef CONFIG_SERIAL_BFIN_DMA
···
 	CONFIG_UART0_CTS_PIN,
 	CONFIG_UART0_RTS_PIN,
 #endif
+	}
 };
 
 

include/asm-blackfin/mach-bf537/anomaly.h

···
                             control */
 #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
                             killed in a particular stage*/
+#define ANOMALY_05000310 /* False hardware errors caused by fetches at the
+			  *  boundary of reserved memory */
 #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
 			    registers are interrupted */
+#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */
+#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not
+			  *  received properly */
 #endif
 
 #if defined(CONFIG_BF_REV_0_2)
···
                             DMA system instability */
 #define ANOMALY_05000280 /* SPI Master boot mode does not work well with
                             Atmel Dataflash devices */
-
+#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context
+			  *  is not restored */
+#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
+			  *  control */
+#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When
+			  *  Killed in a Particular Stage */
+#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment
+			  *  (Not Available On Older Silicon) */
+#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
+#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously
+			  *  On Next System MMR Access */
+#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex
+			  *  mode */
+#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with
+			  *  status No Carrier */
 #endif  /* CONFIG_BF_REV_0_2 */
 
 #endif /* _MACH_ANOMALY_H_ */

include/asm-blackfin/mach-bf561/bfin_serial_5xx.h

···
 };
 
 struct bfin_serial_res bfin_serial_resource[] = {
+	{
 	0xFFC00400,
 	IRQ_UART_RX,
 #ifdef CONFIG_SERIAL_BFIN_DMA
···
 	CONFIG_UART0_CTS_PIN,
 	CONFIG_UART0_RTS_PIN,
 #endif
+	}
 };
 
 

include/asm-blackfin/mach-common/cdef_LPBlackfin.h

···
 #define bfin_read_SRAM_BASE_ADDRESS()        bfin_read32(SRAM_BASE_ADDRESS)
 #define bfin_write_SRAM_BASE_ADDRESS(val)    bfin_write32(SRAM_BASE_ADDRESS,val)
 #define bfin_read_DMEM_CONTROL()             bfin_read32(DMEM_CONTROL)
+#ifdef ANOMALY_05000125
+static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val)
+{
+	unsigned long flags, iwr;
+
+	local_irq_save(flags);
+	__asm__(".align 8\n");
+	bfin_write32(IMEM_CONTROL, val);
+	__builtin_bfin_ssync();
+	local_irq_restore(flags);
+}
+#else
 #define bfin_write_DMEM_CONTROL(val)         bfin_write32(DMEM_CONTROL,val)
+#endif
 #define bfin_read_DCPLB_STATUS()             bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)         bfin_write32(DCPLB_STATUS,val)
 #define bfin_read_DCPLB_FAULT_ADDR()         bfin_read32(DCPLB_FAULT_ADDR)
···
 #define DTEST_DATA3            0xFFE0040C
 */
 #define bfin_read_IMEM_CONTROL()             bfin_read32(IMEM_CONTROL)
+#ifdef ANOMALY_05000125
+static __inline__ void bfin_write_IMEM_CONTROL(unsigned int val)
+{
+	unsigned long flags, iwr;
+
+	local_irq_save(flags);
+	__asm__(".align 8\n");
+	bfin_write32(IMEM_CONTROL, val);
+	__builtin_bfin_ssync();
+	local_irq_restore(flags);
+
+}
+#else
 #define bfin_write_IMEM_CONTROL(val)         bfin_write32(IMEM_CONTROL,val)
+#endif
 #define bfin_read_ICPLB_STATUS()             bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)         bfin_write32(ICPLB_STATUS,val)
 #define bfin_read_ICPLB_FAULT_ADDR()         bfin_read32(ICPLB_FAULT_ADDR)

include/asm-blackfin/unistd.h

···
 #define __ARCH_WANT_SYS_NICE
 #define __ARCH_WANT_SYS_RT_SIGACTION
 #define __ARCH_WANT_SYS_RT_SIGSUSPEND
-#endif
 
 /*
  * "Conditional" syscalls
···
  * but it doesn't work on all toolchains, so we just do it by hand
  */
 #define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall");
+
+#endif	/* __KERNEL__ */
 
 #endif				/* __ASM_BFIN_UNISTD_H */