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dt-bindings: clock: qcom: document SAR2130P Global Clock Controller

Add bindings for the Global Clock Controller (GCC) present on the
Qualcomm SAR2130P platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-2-ecad2a1432ba@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson 3ee31553 133e4a44

+250
+65
Documentation/devicetree/bindings/clock/qcom,sar2130p-gcc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Global Clock & Reset Controller on sar2130p 8 + 9 + maintainers: 10 + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 11 + 12 + description: | 13 + Qualcomm global clock control module provides the clocks, resets and 14 + power domains on sar2130p. 15 + 16 + See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h 17 + 18 + properties: 19 + compatible: 20 + const: qcom,sar2130p-gcc 21 + 22 + clocks: 23 + items: 24 + - description: XO reference clock 25 + - description: Sleep clock 26 + - description: PCIe 0 pipe clock 27 + - description: PCIe 1 pipe clock 28 + - description: Primary USB3 PHY wrapper pipe clock 29 + 30 + protected-clocks: 31 + maxItems: 240 32 + 33 + power-domains: 34 + maxItems: 1 35 + 36 + required: 37 + - compatible 38 + - clocks 39 + - '#power-domain-cells' 40 + 41 + allOf: 42 + - $ref: qcom,gcc.yaml# 43 + 44 + unevaluatedProperties: false 45 + 46 + examples: 47 + - | 48 + #include <dt-bindings/clock/qcom,rpmh.h> 49 + #include <dt-bindings/power/qcom,rpmhpd.h> 50 + 51 + gcc: clock-controller@100000 { 52 + compatible = "qcom,sar2130p-gcc"; 53 + reg = <0x100000 0x1f4200>; 54 + clocks = <&rpmhcc RPMH_CXO_CLK>, 55 + <&sleep_clk>, 56 + <&pcie_0_pipe_clk>, 57 + <&pcie_1_pipe_clk>, 58 + <&usb_0_ssphy>; 59 + power-domains = <&rpmhpd RPMHPD_CX>; 60 + 61 + #clock-cells = <1>; 62 + #reset-cells = <1>; 63 + #power-domain-cells = <1>; 64 + }; 65 + ...
+185
include/dt-bindings/clock/qcom,sar2130p-gcc.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 + /* 3 + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SAR2130P_H 7 + #define _DT_BINDINGS_CLK_QCOM_GCC_SAR2130P_H 8 + 9 + /* GCC clocks */ 10 + #define GCC_GPLL0 0 11 + #define GCC_GPLL0_OUT_EVEN 1 12 + #define GCC_GPLL1 2 13 + #define GCC_GPLL9 3 14 + #define GCC_GPLL9_OUT_EVEN 4 15 + #define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 5 16 + #define GCC_AGGRE_USB3_PRIM_AXI_CLK 6 17 + #define GCC_BOOT_ROM_AHB_CLK 7 18 + #define GCC_CAMERA_AHB_CLK 8 19 + #define GCC_CAMERA_HF_AXI_CLK 9 20 + #define GCC_CAMERA_SF_AXI_CLK 10 21 + #define GCC_CAMERA_XO_CLK 11 22 + #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 12 23 + #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 13 24 + #define GCC_DDRSS_GPU_AXI_CLK 14 25 + #define GCC_DDRSS_PCIE_SF_CLK 15 26 + #define GCC_DISP_AHB_CLK 16 27 + #define GCC_DISP_HF_AXI_CLK 17 28 + #define GCC_GP1_CLK 18 29 + #define GCC_GP1_CLK_SRC 19 30 + #define GCC_GP2_CLK 20 31 + #define GCC_GP2_CLK_SRC 21 32 + #define GCC_GP3_CLK 22 33 + #define GCC_GP3_CLK_SRC 23 34 + #define GCC_GPU_CFG_AHB_CLK 24 35 + #define GCC_GPU_GPLL0_CLK_SRC 25 36 + #define GCC_GPU_GPLL0_DIV_CLK_SRC 26 37 + #define GCC_GPU_MEMNOC_GFX_CLK 27 38 + #define GCC_GPU_SNOC_DVM_GFX_CLK 28 39 + #define GCC_IRIS_SS_HF_AXI1_CLK 29 40 + #define GCC_IRIS_SS_SPD_AXI1_CLK 30 41 + #define GCC_PCIE_0_AUX_CLK 31 42 + #define GCC_PCIE_0_AUX_CLK_SRC 32 43 + #define GCC_PCIE_0_CFG_AHB_CLK 33 44 + #define GCC_PCIE_0_MSTR_AXI_CLK 34 45 + #define GCC_PCIE_0_PHY_RCHNG_CLK 35 46 + #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 36 47 + #define GCC_PCIE_0_PIPE_CLK 37 48 + #define GCC_PCIE_0_PIPE_CLK_SRC 38 49 + #define GCC_PCIE_0_SLV_AXI_CLK 39 50 + #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 40 51 + #define GCC_PCIE_1_AUX_CLK 41 52 + #define GCC_PCIE_1_AUX_CLK_SRC 42 53 + #define GCC_PCIE_1_CFG_AHB_CLK 43 54 + #define GCC_PCIE_1_MSTR_AXI_CLK 44 55 + #define GCC_PCIE_1_PHY_RCHNG_CLK 45 56 + #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 46 57 + #define GCC_PCIE_1_PIPE_CLK 47 58 + #define GCC_PCIE_1_PIPE_CLK_SRC 48 59 + #define GCC_PCIE_1_SLV_AXI_CLK 49 60 + #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 50 61 + #define GCC_PDM2_CLK 51 62 + #define GCC_PDM2_CLK_SRC 52 63 + #define GCC_PDM_AHB_CLK 53 64 + #define GCC_PDM_XO4_CLK 54 65 + #define GCC_QMIP_CAMERA_NRT_AHB_CLK 55 66 + #define GCC_QMIP_CAMERA_RT_AHB_CLK 56 67 + #define GCC_QMIP_GPU_AHB_CLK 57 68 + #define GCC_QMIP_PCIE_AHB_CLK 58 69 + #define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 59 70 + #define GCC_QMIP_VIDEO_CVP_AHB_CLK 60 71 + #define GCC_QMIP_VIDEO_LSR_AHB_CLK 61 72 + #define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 62 73 + #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 63 74 + #define GCC_QUPV3_WRAP0_CORE_2X_CLK 64 75 + #define GCC_QUPV3_WRAP0_CORE_CLK 65 76 + #define GCC_QUPV3_WRAP0_S0_CLK 66 77 + #define GCC_QUPV3_WRAP0_S0_CLK_SRC 67 78 + #define GCC_QUPV3_WRAP0_S1_CLK 68 79 + #define GCC_QUPV3_WRAP0_S1_CLK_SRC 69 80 + #define GCC_QUPV3_WRAP0_S2_CLK 70 81 + #define GCC_QUPV3_WRAP0_S2_CLK_SRC 71 82 + #define GCC_QUPV3_WRAP0_S3_CLK 72 83 + #define GCC_QUPV3_WRAP0_S3_CLK_SRC 73 84 + #define GCC_QUPV3_WRAP0_S4_CLK 74 85 + #define GCC_QUPV3_WRAP0_S4_CLK_SRC 75 86 + #define GCC_QUPV3_WRAP0_S5_CLK 76 87 + #define GCC_QUPV3_WRAP0_S5_CLK_SRC 77 88 + #define GCC_QUPV3_WRAP1_CORE_2X_CLK 78 89 + #define GCC_QUPV3_WRAP1_CORE_CLK 79 90 + #define GCC_QUPV3_WRAP1_S0_CLK 80 91 + #define GCC_QUPV3_WRAP1_S0_CLK_SRC 81 92 + #define GCC_QUPV3_WRAP1_S1_CLK 82 93 + #define GCC_QUPV3_WRAP1_S1_CLK_SRC 83 94 + #define GCC_QUPV3_WRAP1_S2_CLK 84 95 + #define GCC_QUPV3_WRAP1_S2_CLK_SRC 85 96 + #define GCC_QUPV3_WRAP1_S3_CLK 86 97 + #define GCC_QUPV3_WRAP1_S3_CLK_SRC 87 98 + #define GCC_QUPV3_WRAP1_S4_CLK 88 99 + #define GCC_QUPV3_WRAP1_S4_CLK_SRC 89 100 + #define GCC_QUPV3_WRAP1_S5_CLK 90 101 + #define GCC_QUPV3_WRAP1_S5_CLK_SRC 91 102 + #define GCC_QUPV3_WRAP_0_M_AHB_CLK 92 103 + #define GCC_QUPV3_WRAP_0_S_AHB_CLK 93 104 + #define GCC_QUPV3_WRAP_1_M_AHB_CLK 94 105 + #define GCC_QUPV3_WRAP_1_S_AHB_CLK 95 106 + #define GCC_SDCC1_AHB_CLK 96 107 + #define GCC_SDCC1_APPS_CLK 97 108 + #define GCC_SDCC1_APPS_CLK_SRC 98 109 + #define GCC_SDCC1_ICE_CORE_CLK 99 110 + #define GCC_SDCC1_ICE_CORE_CLK_SRC 100 111 + #define GCC_USB30_PRIM_MASTER_CLK 101 112 + #define GCC_USB30_PRIM_MASTER_CLK_SRC 102 113 + #define GCC_USB30_PRIM_MOCK_UTMI_CLK 103 114 + #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 104 115 + #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 105 116 + #define GCC_USB30_PRIM_SLEEP_CLK 106 117 + #define GCC_USB3_PRIM_PHY_AUX_CLK 107 118 + #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 108 119 + #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 109 120 + #define GCC_USB3_PRIM_PHY_PIPE_CLK 110 121 + #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 111 122 + #define GCC_VIDEO_AHB_CLK 112 123 + #define GCC_VIDEO_AXI0_CLK 113 124 + #define GCC_VIDEO_AXI1_CLK 114 125 + #define GCC_VIDEO_XO_CLK 115 126 + #define GCC_GPLL4 116 127 + #define GCC_GPLL5 117 128 + #define GCC_GPLL7 118 129 + #define GCC_DDRSS_SPAD_CLK 119 130 + #define GCC_DDRSS_SPAD_CLK_SRC 120 131 + #define GCC_VIDEO_AXI0_SREG 121 132 + #define GCC_VIDEO_AXI1_SREG 122 133 + #define GCC_IRIS_SS_HF_AXI1_SREG 123 134 + #define GCC_IRIS_SS_SPD_AXI1_SREG 124 135 + 136 + /* GCC resets */ 137 + #define GCC_CAMERA_BCR 0 138 + #define GCC_DISPLAY_BCR 1 139 + #define GCC_GPU_BCR 2 140 + #define GCC_PCIE_0_BCR 3 141 + #define GCC_PCIE_0_LINK_DOWN_BCR 4 142 + #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 143 + #define GCC_PCIE_0_PHY_BCR 6 144 + #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 145 + #define GCC_PCIE_1_BCR 8 146 + #define GCC_PCIE_1_LINK_DOWN_BCR 9 147 + #define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 148 + #define GCC_PCIE_1_PHY_BCR 11 149 + #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 150 + #define GCC_PCIE_PHY_BCR 13 151 + #define GCC_PCIE_PHY_CFG_AHB_BCR 14 152 + #define GCC_PCIE_PHY_COM_BCR 15 153 + #define GCC_PDM_BCR 16 154 + #define GCC_QUPV3_WRAPPER_0_BCR 17 155 + #define GCC_QUPV3_WRAPPER_1_BCR 18 156 + #define GCC_QUSB2PHY_PRIM_BCR 19 157 + #define GCC_QUSB2PHY_SEC_BCR 20 158 + #define GCC_SDCC1_BCR 21 159 + #define GCC_USB30_PRIM_BCR 22 160 + #define GCC_USB3_DP_PHY_PRIM_BCR 23 161 + #define GCC_USB3_DP_PHY_SEC_BCR 24 162 + #define GCC_USB3_PHY_PRIM_BCR 25 163 + #define GCC_USB3_PHY_SEC_BCR 26 164 + #define GCC_USB3PHY_PHY_PRIM_BCR 27 165 + #define GCC_USB3PHY_PHY_SEC_BCR 28 166 + #define GCC_VIDEO_AXI0_CLK_ARES 29 167 + #define GCC_VIDEO_AXI1_CLK_ARES 30 168 + #define GCC_VIDEO_BCR 31 169 + #define GCC_IRIS_SS_HF_AXI_CLK_ARES 32 170 + #define GCC_IRIS_SS_SPD_AXI_CLK_ARES 33 171 + #define GCC_DDRSS_SPAD_CLK_ARES 34 172 + 173 + /* GCC power domains */ 174 + #define PCIE_0_GDSC 0 175 + #define PCIE_0_PHY_GDSC 1 176 + #define PCIE_1_GDSC 2 177 + #define PCIE_1_PHY_GDSC 3 178 + #define USB30_PRIM_GDSC 4 179 + #define USB3_PHY_GDSC 5 180 + #define HLOS1_VOTE_MM_SNOC_MMU_TBU_HF0_GDSC 6 181 + #define HLOS1_VOTE_MM_SNOC_MMU_TBU_SF0_GDSC 7 182 + #define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 8 183 + #define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 9 184 + 185 + #endif