tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'memory-controller-drv-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.20
Add MediaTek MT6795 Helio X10 SMI support.
* tag 'memory-controller-drv-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: mtk-smi: Add support for MT6795 Helio X10
dt-bindings: memory: mtk-smi: Add MT6795 Helio X10 bindings
Link: https://lore.kernel.org/r/20220624081828.33649-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+19
+1
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
+1
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
+1
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
+1
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
+17
drivers/memory/mtk-smi.c
+17
drivers/memory/mtk-smi.c
···
21
21
/* SMI COMMON */
22
22
#define SMI_L1LEN 0x100
23
23
24
+
#define SMI_L1_ARB 0x200
24
25
#define SMI_BUS_SEL 0x220
25
26
#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
26
27
/* All are MMU0 defaultly. Only specialize mmu1 here. */
27
28
#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
28
29
30
+
#define SMI_READ_FIFO_TH 0x230
29
31
#define SMI_M4U_TH 0x234
30
32
#define SMI_FIFO_TH1 0x238
31
33
#define SMI_FIFO_TH2 0x23c
···
362
360
{.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},
363
361
{.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
364
362
{.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779},
363
+
{.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173},
365
364
{.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167},
366
365
{.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
367
366
{.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
···
547
544
}
548
545
};
549
546
547
+
static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = {
548
+
{SMI_L1_ARB, 0x1b},
549
+
{SMI_M4U_TH, 0xce810c85},
550
+
{SMI_FIFO_TH1, 0x43214c8},
551
+
{SMI_READ_FIFO_TH, 0x191f},
552
+
};
553
+
550
554
static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = {
551
555
{SMI_L1LEN, 0xb},
552
556
{SMI_M4U_TH, 0xe100e10},
···
576
566
.has_gals = true,
577
567
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
578
568
F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
569
+
};
570
+
571
+
static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = {
572
+
.type = MTK_SMI_GEN2,
573
+
.bus_sel = F_MMU1_LARB(0),
574
+
.init = mtk_smi_common_mt6795_init,
579
575
};
580
576
581
577
static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
···
628
612
{.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},
629
613
{.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
630
614
{.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779},
615
+
{.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795},
631
616
{.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2},
632
617
{.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
633
618
{.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},