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ARCv2: [axs103_smp] Reduce clk for SMP FPGA configs

Newer bitfiles needs the reduced clk even for SMP builds

Cc: <stable@vger.kernel.org> #4.2
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

authored by

Vineet Gupta and committed by
Linus Torvalds 3ebb0540 ded0e250

+2
+2
arch/arc/plat-axs10x/axs10x.c
··· 402 unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; 403 if (num_cores > 2) 404 arc_set_core_freq(50 * 1000000); 405 #endif 406 407 switch (arc_get_core_freq()/1000000) {
··· 402 unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; 403 if (num_cores > 2) 404 arc_set_core_freq(50 * 1000000); 405 + else if (num_cores == 2) 406 + arc_set_core_freq(75 * 1000000); 407 #endif 408 409 switch (arc_get_core_freq()/1000000) {