tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: mediatek: Add MT8195 apmixedsys clock support
Add MT8195 apmixedsys clock controller which provides Plls
generated from SoC 26m and ssusb clock gate control.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-7-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Chun-Jie Chen
and committed by
Stephen Boyd
3e9121f1
6203815b
+154
+8
drivers/clk/mediatek/Kconfig
+8
drivers/clk/mediatek/Kconfig
···
575
575
help
576
576
This driver supports MediaTek MT8192 vencsys clocks.
577
577
578
+
config COMMON_CLK_MT8195
579
+
bool "Clock driver for MediaTek MT8195"
580
+
depends on ARM64 || COMPILE_TEST
581
+
select COMMON_CLK_MEDIATEK
582
+
default ARCH_MEDIATEK
583
+
help
584
+
This driver supports MediaTek MT8195 clocks.
585
+
578
586
config COMMON_CLK_MT8516
579
587
bool "Clock driver for MediaTek MT8516"
580
588
depends on ARCH_MEDIATEK || COMPILE_TEST
+1
drivers/clk/mediatek/Makefile
+1
drivers/clk/mediatek/Makefile
···
80
80
obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o
81
81
obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
82
82
obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
83
+
obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o
83
84
obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
84
85
obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
+145
drivers/clk/mediatek/clk-mt8195-apmixedsys.c
+145
drivers/clk/mediatek/clk-mt8195-apmixedsys.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
//
3
+
// Copyright (c) 2021 MediaTek Inc.
4
+
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5
+
6
+
#include "clk-gate.h"
7
+
#include "clk-mtk.h"
8
+
9
+
#include <dt-bindings/clock/mt8195-clk.h>
10
+
#include <linux/of_device.h>
11
+
#include <linux/platform_device.h>
12
+
13
+
static const struct mtk_gate_regs apmixed_cg_regs = {
14
+
.set_ofs = 0x8,
15
+
.clr_ofs = 0x8,
16
+
.sta_ofs = 0x8,
17
+
};
18
+
19
+
#define GATE_APMIXED(_id, _name, _parent, _shift) \
20
+
GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
21
+
22
+
static const struct mtk_gate apmixed_clks[] = {
23
+
GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M, "pll_ssusb26m", "clk26m", 1),
24
+
};
25
+
26
+
#define MT8195_PLL_FMAX (3800UL * MHZ)
27
+
#define MT8195_PLL_FMIN (1500UL * MHZ)
28
+
#define MT8195_INTEGER_BITS 8
29
+
30
+
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
31
+
_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
32
+
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
33
+
_pcw_reg, _pcw_shift, _pcw_chg_reg, \
34
+
_en_reg, _pll_en_bit) { \
35
+
.id = _id, \
36
+
.name = _name, \
37
+
.reg = _reg, \
38
+
.pwr_reg = _pwr_reg, \
39
+
.en_mask = _en_mask, \
40
+
.flags = _flags, \
41
+
.rst_bar_mask = _rst_bar_mask, \
42
+
.fmax = MT8195_PLL_FMAX, \
43
+
.fmin = MT8195_PLL_FMIN, \
44
+
.pcwbits = _pcwbits, \
45
+
.pcwibits = MT8195_INTEGER_BITS, \
46
+
.pd_reg = _pd_reg, \
47
+
.pd_shift = _pd_shift, \
48
+
.tuner_reg = _tuner_reg, \
49
+
.tuner_en_reg = _tuner_en_reg, \
50
+
.tuner_en_bit = _tuner_en_bit, \
51
+
.pcw_reg = _pcw_reg, \
52
+
.pcw_shift = _pcw_shift, \
53
+
.pcw_chg_reg = _pcw_chg_reg, \
54
+
.en_reg = _en_reg, \
55
+
.pll_en_bit = _pll_en_bit, \
56
+
}
57
+
58
+
static const struct mtk_pll_data plls[] = {
59
+
PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
60
+
0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
61
+
PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
62
+
0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
63
+
PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
64
+
0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9),
65
+
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
66
+
0, 0, 22, 0x0718, 24, 0, 0, 0, 0x0718, 0, 0x0718, 0, 9),
67
+
PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x00a0, 0x00b0, 0,
68
+
0, 0, 22, 0x00a8, 24, 0, 0, 0, 0x00a8, 0, 0x00a8, 0, 9),
69
+
PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x00c0, 0x00d0, 0,
70
+
0, 0, 22, 0x00c8, 24, 0, 0, 0, 0x00c8, 0, 0x00c8, 0, 9),
71
+
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0, 0xff000000,
72
+
HAVE_RST_BAR, BIT(23), 22, 0x00e8, 24, 0, 0, 0, 0x00e8, 0, 0x00e8, 0, 9),
73
+
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0, 0xff000000,
74
+
HAVE_RST_BAR, BIT(23), 22, 0x01d8, 24, 0, 0, 0, 0x01d8, 0, 0x01d8, 0, 9),
75
+
PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x0890, 0x08a0, 0,
76
+
0, 0, 22, 0x0898, 24, 0, 0, 0, 0x0898, 0, 0x0898, 0, 9),
77
+
PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0,
78
+
0, 0, 22, 0x0108, 24, 0, 0, 0, 0x0108, 0, 0x0108, 0, 9),
79
+
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x01f0, 0x0700, 0xff000000,
80
+
HAVE_RST_BAR, BIT(23), 22, 0x01f8, 24, 0, 0, 0, 0x01f8, 0, 0x01f8, 0, 9),
81
+
PLL(CLK_APMIXED_HDMIPLL1, "hdmipll1", 0x08c0, 0x08d0, 0,
82
+
0, 0, 22, 0x08c8, 24, 0, 0, 0, 0x08c8, 0, 0x08c8, 0, 9),
83
+
PLL(CLK_APMIXED_HDMIPLL2, "hdmipll2", 0x0870, 0x0880, 0,
84
+
0, 0, 22, 0x0878, 24, 0, 0, 0, 0x0878, 0, 0x0878, 0, 9),
85
+
PLL(CLK_APMIXED_HDMIRX_APLL, "hdmirx_apll", 0x08e0, 0x0dd4, 0,
86
+
0, 0, 32, 0x08e8, 24, 0, 0, 0, 0x08ec, 0, 0x08e8, 0, 9),
87
+
PLL(CLK_APMIXED_USB1PLL, "usb1pll", 0x01a0, 0x01b0, 0,
88
+
0, 0, 22, 0x01a8, 24, 0, 0, 0, 0x01a8, 0, 0x01a8, 0, 9),
89
+
PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x07e0, 0x07f0, 0,
90
+
0, 0, 22, 0x07e8, 24, 0, 0, 0, 0x07e8, 0, 0x07e8, 0, 9),
91
+
PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0,
92
+
0, 0, 32, 0x07c8, 24, 0x0470, 0x0000, 12, 0x07cc, 0, 0x07c8, 0, 9),
93
+
PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0,
94
+
0, 0, 32, 0x0788, 24, 0x0474, 0x0000, 13, 0x078c, 0, 0x0788, 0, 9),
95
+
PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0,
96
+
0, 0, 32, 0x0768, 24, 0x0478, 0x0000, 14, 0x076c, 0, 0x0768, 0, 9),
97
+
PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0,
98
+
0, 0, 32, 0x0748, 24, 0x047C, 0x0000, 15, 0x074c, 0, 0x0748, 0, 9),
99
+
PLL(CLK_APMIXED_APLL5, "apll5", 0x07a0, 0x0dd0, 0x100000,
100
+
0, 0, 32, 0x07a8, 24, 0x0480, 0x0000, 16, 0x07ac, 0, 0x07a8, 0, 9),
101
+
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0,
102
+
0, 0, 22, 0x0348, 24, 0, 0, 0, 0x0348, 0, 0x0348, 0, 9),
103
+
PLL(CLK_APMIXED_DGIPLL, "dgipll", 0x0150, 0x0160, 0,
104
+
0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
105
+
};
106
+
107
+
static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
108
+
{ .compatible = "mediatek,mt8195-apmixedsys", },
109
+
{}
110
+
};
111
+
112
+
static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
113
+
{
114
+
struct clk_onecell_data *clk_data;
115
+
struct device_node *node = pdev->dev.of_node;
116
+
int r;
117
+
118
+
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
119
+
if (!clk_data)
120
+
return -ENOMEM;
121
+
122
+
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
123
+
r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
124
+
if (r)
125
+
goto free_apmixed_data;
126
+
127
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
128
+
if (r)
129
+
goto free_apmixed_data;
130
+
131
+
return r;
132
+
133
+
free_apmixed_data:
134
+
mtk_free_clk_data(clk_data);
135
+
return r;
136
+
}
137
+
138
+
static struct platform_driver clk_mt8195_apmixed_drv = {
139
+
.probe = clk_mt8195_apmixed_probe,
140
+
.driver = {
141
+
.name = "clk-mt8195-apmixed",
142
+
.of_match_table = of_match_clk_mt8195_apmixed,
143
+
},
144
+
};
145
+
builtin_platform_driver(clk_mt8195_apmixed_drv);