tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ARM: dts: ixp4xx: Group PCI interrupt properties together

Move the PCI 'interrupt-map-mask' and '#interrupt-cells' properties
alongside the 'interrupt-map' property in each board dts. This avoids
having incomplete set of interrupt properties which may fail validation.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>

authored by

Rob Herring and committed by
Linus Walleij 3e70cee4 7a4d10a1

+24 -2
+2
arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts
··· 63 63 * We have slots (IDSEL) 1 and 2 with one assigned IRQ 64 64 * each handling all IRQs. 65 65 */ 66 + #interrupt-cells = <1>; 67 + interrupt-map-mask = <0xf800 0 0 7>; 66 68 interrupt-map = 67 69 /* IDSEL 1 */ 68 70 <0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */
+2
arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
··· 120 120 * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt 121 121 * per slot. This interrupt is shared (OR:ed) by all four pins. 122 122 */ 123 + #interrupt-cells = <1>; 124 + interrupt-map-mask = <0xf800 0 0 7>; 123 125 interrupt-map = 124 126 /* IDSEL 1 */ 125 127 <0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */
+2
arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
··· 106 106 * Written based on the FSG-3 PCI boardfile. 107 107 * We have slots 12, 13 & 14 (IDSEL) with one IRQ each. 108 108 */ 109 + #interrupt-cells = <1>; 110 + interrupt-map-mask = <0xf800 0 0 7>; 109 111 interrupt-map = 110 112 /* IDSEL 12 */ 111 113 <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
+2
arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts
··· 115 115 * 116 116 * We have up to 4 slots (IDSEL) with 4 swizzled IRQs. 117 117 */ 118 + #interrupt-cells = <1>; 119 + interrupt-map-mask = <0xf800 0 0 7>; 118 120 interrupt-map = 119 121 /* IDSEL 1 */ 120 122 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
+2
arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts
··· 115 115 * Taken from NAS 100D PCI boardfile (nas100d-pci.c) 116 116 * We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3. 117 117 */ 118 + #interrupt-cells = <1>; 119 + interrupt-map-mask = <0xf800 0 0 7>; 118 120 interrupt-map = 119 121 /* IDSEL 1 */ 120 122 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
+2
arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts
··· 68 68 * We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ 69 69 * for 12 & 13 and one for 14. 70 70 */ 71 + #interrupt-cells = <1>; 72 + interrupt-map-mask = <0xf800 0 0 7>; 71 73 interrupt-map = 72 74 /* IDSEL 12 */ 73 75 <0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */
+2
arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
··· 122 122 * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant 123 123 * We have slots (IDSEL) 1, 2 and 3. 124 124 */ 125 + #interrupt-cells = <1>; 126 + interrupt-map-mask = <0xf800 0 0 7>; 125 127 interrupt-map = 126 128 /* IDSEL 1 */ 127 129 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
+2
arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts
··· 123 123 * We have up to 2 slots (IDSEL) with 2 swizzled IRQs. 124 124 * Derived from the GTWX5715 PCI boardfile. 125 125 */ 126 + #interrupt-cells = <1>; 127 + interrupt-map-mask = <0xf800 0 0 7>; 126 128 interrupt-map = 127 129 /* IDSEL 0 */ 128 130 <0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */
+2
arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts
··· 62 62 * We have slots (IDSEL) 1 and 2 with one assigned IRQ 63 63 * each handling all IRQs. 64 64 */ 65 + #interrupt-cells = <1>; 66 + interrupt-map-mask = <0xf800 0 0 7>; 65 67 interrupt-map = 66 68 /* IDSEL 1 */ 67 69 <0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */
+2
arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
··· 131 131 * have instead assumed that they are rotated (swizzled) like 132 132 * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc. 133 133 */ 134 + #interrupt-cells = <1>; 135 + interrupt-map-mask = <0xf800 0 0 7>; 134 136 interrupt-map = 135 137 /* IDSEL 1 */ 136 138 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
+2
arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi
··· 106 106 * PCI slots on the BIXMB425BD base card. 107 107 * We have up to 4 slots (IDSEL) with 4 swizzled IRQs. 108 108 */ 109 + #interrupt-cells = <1>; 110 + interrupt-map-mask = <0xf800 0 0 7>; 109 111 interrupt-map = 110 112 /* IDSEL 1 */ 111 113 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
-2
arch/arm/boot/dts/intel-ixp4xx.dtsi
··· 78 78 dma-ranges = 79 79 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; 80 80 81 - #interrupt-cells = <1>; 82 - interrupt-map-mask = <0xf800 0 0 7>; 83 81 /* Each unique DTS using PCI must specify the swizzling */ 84 82 }; 85 83