Merge tag 'mvebu-dt64-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt

mvebu dt64 for 6.2 (part 1)

Update cache properties for various Marvell SoCs
Reserved memory for optee firmware
Turris Mox (Armada 3720 based Socs)
- Define slot-power-limit-milliwatt for PCIe
- Add missing interrupt for RTC

* tag 'mvebu-dt64-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
arm64: dts: marvell: add optee FW definitions
arm64: dts: Update cache properties for marvell
arm64: dts: armada-3720-turris-mox: Add missing interrupt for RTC
arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe

Link: https://lore.kernel.org/r/87fse39aer.fsf@BL-laptop
Signed-off-by: Arnd Bergmann <[e-mail]>

arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi

···
 
 		l2: l2-cache {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 

arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts

···
 	/delete-property/ mrvl,i2c-fast-mode;
 	status = "okay";
 
+	/* MCP7940MT-I/MNY RTC */
 	rtc@6f {
 		compatible = "microchip,mcp7940x";
 		reg = <0x6f>;
+		interrupt-parent = <&gpiosb>;
+		interrupts = <5 0>; /* GPIO2_5 */
 	};
 };
 
···
 	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
 	status = "okay";
 	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
+	slot-power-limit-milliwatt = <10000>;
 	/*
 	 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
 	 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and

arch/arm64/boot/dts/marvell/armada-37xx.dtsi

···
 			reg = <0 0x4000000 0 0x200000>;
 			no-map;
 		};
+
+		tee@4400000 {
+			reg = <0 0x4400000 0 0x1000000>;
+			no-map;
+		};
 	};
 
 	cpus {

arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi

···
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 		};
 	};
 

arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi

···
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 		};
 
 		l2_1: l2-cache1 {
···
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 		};
 	};
 };

arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi

···
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 		};
 
 		l2_1: l2-cache1 {
···
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 		};
 	};
 };

arch/arm64/boot/dts/marvell/armada-ap80x.dtsi

···
 			reg = <0x0 0x4000000 0x0 0x200000>;
 			no-map;
 		};
+
+		tee@4400000 {
+			reg = <0 0x4400000 0 0x1000000>;
+			no-map;
+		};
 	};
 
 	AP_NAME {