Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

phy: Add Marvell 88E1116R phy ID

This phy is on Xilinx ZC702 zynq development board.

Signed-off-by: Anirudha Sarangi <anirudh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Michal Simek and committed by
David S. Miller
3da09a51 f5e1cabf

+66
+65
drivers/net/phy/marvell.c
··· 116 116 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800 117 117 #define MII_M1011_PHY_STATUS_LINK 0x0400 118 118 119 + #define MII_M1116R_CONTROL_REG_MAC 21 120 + 119 121 120 122 MODULE_DESCRIPTION("Marvell PHY driver"); 121 123 MODULE_AUTHOR("Andy Fleming"); ··· 372 370 return err; 373 371 374 372 return m88e1121_config_aneg(phydev); 373 + } 374 + 375 + static int m88e1116r_config_init(struct phy_device *phydev) 376 + { 377 + int temp; 378 + int err; 379 + 380 + temp = phy_read(phydev, MII_BMCR); 381 + temp |= BMCR_RESET; 382 + err = phy_write(phydev, MII_BMCR, temp); 383 + if (err < 0) 384 + return err; 385 + 386 + mdelay(500); 387 + 388 + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0); 389 + if (err < 0) 390 + return err; 391 + 392 + temp = phy_read(phydev, MII_M1011_PHY_SCR); 393 + temp |= (7 << 12); /* max number of gigabit attempts */ 394 + temp |= (1 << 11); /* enable downshift */ 395 + temp |= MII_M1011_PHY_SCR_AUTO_CROSS; 396 + err = phy_write(phydev, MII_M1011_PHY_SCR, temp); 397 + if (err < 0) 398 + return err; 399 + 400 + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2); 401 + if (err < 0) 402 + return err; 403 + temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC); 404 + temp |= (1 << 5); 405 + temp |= (1 << 4); 406 + err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp); 407 + if (err < 0) 408 + return err; 409 + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0); 410 + if (err < 0) 411 + return err; 412 + 413 + temp = phy_read(phydev, MII_BMCR); 414 + temp |= BMCR_RESET; 415 + err = phy_write(phydev, MII_BMCR, temp); 416 + if (err < 0) 417 + return err; 418 + 419 + mdelay(500); 420 + 421 + return 0; 375 422 } 376 423 377 424 static int m88e1111_config_init(struct phy_device *phydev) ··· 991 940 .config_intr = &marvell_config_intr, 992 941 .driver = { .owner = THIS_MODULE }, 993 942 }, 943 + { 944 + .phy_id = MARVELL_PHY_ID_88E1116R, 945 + .phy_id_mask = MARVELL_PHY_ID_MASK, 946 + .name = "Marvell 88E1116R", 947 + .features = PHY_GBIT_FEATURES, 948 + .flags = PHY_HAS_INTERRUPT, 949 + .config_init = &m88e1116r_config_init, 950 + .config_aneg = &genphy_config_aneg, 951 + .read_status = &genphy_read_status, 952 + .ack_interrupt = &marvell_ack_interrupt, 953 + .config_intr = &marvell_config_intr, 954 + .driver = { .owner = THIS_MODULE }, 955 + }, 994 956 }; 995 957 996 958 static int __init marvell_init(void) ··· 1031 967 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK }, 1032 968 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK }, 1033 969 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK }, 970 + { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK }, 1034 971 { } 1035 972 }; 1036 973
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include/linux/marvell_phy.h
··· 14 14 #define MARVELL_PHY_ID_88E1149R 0x01410e50 15 15 #define MARVELL_PHY_ID_88E1240 0x01410e30 16 16 #define MARVELL_PHY_ID_88E1318S 0x01410e90 17 + #define MARVELL_PHY_ID_88E1116R 0x01410e40 17 18 18 19 /* struct phy_device dev_flags definitions */ 19 20 #define MARVELL_PHY_M1145_FLAGS_RESISTANCE 0x00000001