tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'imx-clk-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
Pull i.MX updates from Shawn Guo:
"The i.MX clock updates for 4.4:
- A couple of fixes on i.MX31 and i.MX35 clock initialization functions
which makes mxc_timer_init() currently be called twice for DT boot.
- Increase i.MX6UL AXI bus clock rate to 264MHz which is the optimal
design target.
- Add a few missing clocks, ADC clock for i.MX7D, OCOTP clock for
Vybrid, and SPDIF_GCLK for i.MX6.
- A series from Lucas to fix early debug UART clock setup. This is
currently a one-off fix for i.MX platform, and can be extended to
become a generic solution later."
* tag 'imx-clk-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx6: Add SPDIF_GCLK clock in clock tree
clk: imx7d: add ADC root clock
clk: imx31: Do not call mxc_timer_init twice when booting with DT
clk: imx7d: retain early UART clocks during kernel init
clk: imx6: retain early UART clocks during kernel init
clk: imx5: retain early UART clocks during kernel init
clk: imx35: retain early UART clocks during kernel init
clk: imx31: retain early UART clocks during kernel init
clk: imx27: retain early UART clocks during kernel init
clk: imx25: retain early UART clocks during kernel init
clk: imx: add common logic to detect early UART usage
clk: imx35: Do not call mxc_timer_init twice when booting with DT
clk: clk-vf610: Add clock for Vybrid OCOTP controller
clk: imx: increase AXI clock rate to 264MHz for i.MX6UL
+219
-36
+12
drivers/clk/imx/clk-imx25.c
+12
drivers/clk/imx/clk-imx25.c
···
86
86
87
87
static struct clk *clk[clk_max];
88
88
89
+
static struct clk ** const uart_clks[] __initconst = {
90
+
&clk[uart_ipg_per],
91
+
&clk[uart1_ipg],
92
+
&clk[uart2_ipg],
93
+
&clk[uart3_ipg],
94
+
&clk[uart4_ipg],
95
+
&clk[uart5_ipg],
96
+
NULL
97
+
};
98
+
89
99
static int __init __mx25_clocks_init(unsigned long osc_rate,
90
100
void __iomem *ccm_base)
91
101
{
···
242
232
* is used on some imx25 board designs to clock the audio codec.
243
233
*/
244
234
clk_set_parent(clk[cko_sel], clk[ipg]);
235
+
236
+
imx_register_uart_clocks(uart_clks);
245
237
246
238
return 0;
247
239
}
+13
drivers/clk/imx/clk-imx27.c
+13
drivers/clk/imx/clk-imx27.c
···
47
47
static struct clk *clk[IMX27_CLK_MAX];
48
48
static struct clk_onecell_data clk_data;
49
49
50
+
static struct clk ** const uart_clks[] __initconst = {
51
+
&clk[IMX27_CLK_PER1_GATE],
52
+
&clk[IMX27_CLK_UART1_IPG_GATE],
53
+
&clk[IMX27_CLK_UART2_IPG_GATE],
54
+
&clk[IMX27_CLK_UART3_IPG_GATE],
55
+
&clk[IMX27_CLK_UART4_IPG_GATE],
56
+
&clk[IMX27_CLK_UART5_IPG_GATE],
57
+
&clk[IMX27_CLK_UART6_IPG_GATE],
58
+
NULL
59
+
};
60
+
50
61
static void __init _mx27_clocks_init(unsigned long fref)
51
62
{
52
63
BUG_ON(!ccm);
···
173
162
clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0");
174
163
175
164
clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
165
+
166
+
imx_register_uart_clocks(uart_clks);
176
167
177
168
imx_print_silicon_rev("i.MX27", mx27_revision());
178
169
}
+28
-7
drivers/clk/imx/clk-imx31.c
+28
-7
drivers/clk/imx/clk-imx31.c
···
62
62
static struct clk *clk[clk_max];
63
63
static struct clk_onecell_data clk_data;
64
64
65
-
int __init mx31_clocks_init(unsigned long fref)
65
+
static struct clk ** const uart_clks[] __initconst = {
66
+
&clk[ipg],
67
+
&clk[uart1_gate],
68
+
&clk[uart2_gate],
69
+
&clk[uart3_gate],
70
+
&clk[uart4_gate],
71
+
&clk[uart5_gate],
72
+
NULL
73
+
};
74
+
75
+
static void __init _mx31_clocks_init(unsigned long fref)
66
76
{
67
77
void __iomem *base;
68
78
struct device_node *np;
···
142
132
143
133
imx_check_clocks(clk, ARRAY_SIZE(clk));
144
134
135
+
clk_set_parent(clk[csi], clk[upll]);
136
+
clk_prepare_enable(clk[emi_gate]);
137
+
clk_prepare_enable(clk[iim_gate]);
138
+
mx31_revision();
139
+
clk_disable_unprepare(clk[iim_gate]);
140
+
145
141
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
146
142
147
143
if (np) {
···
155
139
clk_data.clk_num = ARRAY_SIZE(clk);
156
140
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
157
141
}
142
+
}
143
+
144
+
int __init mx31_clocks_init(void)
145
+
{
146
+
u32 fref = 26000000; /* default */
147
+
148
+
_mx31_clocks_init(fref);
158
149
159
150
clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
160
151
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
···
217
194
clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
218
195
clk_register_clkdev(clk[iim_gate], "iim", NULL);
219
196
220
-
clk_set_parent(clk[csi], clk[upll]);
221
-
clk_prepare_enable(clk[emi_gate]);
222
-
clk_prepare_enable(clk[iim_gate]);
223
-
mx31_revision();
224
-
clk_disable_unprepare(clk[iim_gate]);
225
197
198
+
imx_register_uart_clocks(uart_clks);
226
199
mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31);
227
200
228
201
return 0;
···
237
218
break;
238
219
}
239
220
240
-
return mx31_clocks_init(fref);
221
+
_mx31_clocks_init(fref);
222
+
223
+
return 0;
241
224
}
+37
-22
drivers/clk/imx/clk-imx35.c
+37
-22
drivers/clk/imx/clk-imx35.c
···
84
84
85
85
static struct clk *clk[clk_max];
86
86
87
-
int __init mx35_clocks_init(void)
87
+
static struct clk ** const uart_clks[] __initconst = {
88
+
&clk[ipg],
89
+
&clk[uart1_gate],
90
+
&clk[uart2_gate],
91
+
&clk[uart3_gate],
92
+
NULL
93
+
};
94
+
95
+
static void __init _mx35_clocks_init(void)
88
96
{
89
97
void __iomem *base;
90
98
u32 pdr0, consumer_sel, hsp_sel;
···
228
220
229
221
imx_check_clocks(clk, ARRAY_SIZE(clk));
230
222
223
+
clk_prepare_enable(clk[spba_gate]);
224
+
clk_prepare_enable(clk[gpio1_gate]);
225
+
clk_prepare_enable(clk[gpio2_gate]);
226
+
clk_prepare_enable(clk[gpio3_gate]);
227
+
clk_prepare_enable(clk[iim_gate]);
228
+
clk_prepare_enable(clk[emi_gate]);
229
+
clk_prepare_enable(clk[max_gate]);
230
+
clk_prepare_enable(clk[iomuxc_gate]);
231
+
232
+
/*
233
+
* SCC is needed to boot via mmc after a watchdog reset. The clock code
234
+
* before conversion to common clk also enabled UART1 (which isn't
235
+
* handled here and not needed for mmc) and IIM (which is enabled
236
+
* unconditionally above).
237
+
*/
238
+
clk_prepare_enable(clk[scc_gate]);
239
+
240
+
imx_register_uart_clocks(uart_clks);
241
+
242
+
imx_print_silicon_rev("i.MX35", mx35_revision());
243
+
}
244
+
245
+
int __init mx35_clocks_init(void)
246
+
{
247
+
_mx35_clocks_init();
248
+
231
249
clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
232
250
clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
233
251
clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
···
313
279
clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
314
280
clk_register_clkdev(clk[admux_gate], "audmux", NULL);
315
281
316
-
clk_prepare_enable(clk[spba_gate]);
317
-
clk_prepare_enable(clk[gpio1_gate]);
318
-
clk_prepare_enable(clk[gpio2_gate]);
319
-
clk_prepare_enable(clk[gpio3_gate]);
320
-
clk_prepare_enable(clk[iim_gate]);
321
-
clk_prepare_enable(clk[emi_gate]);
322
-
clk_prepare_enable(clk[max_gate]);
323
-
clk_prepare_enable(clk[iomuxc_gate]);
324
-
325
-
/*
326
-
* SCC is needed to boot via mmc after a watchdog reset. The clock code
327
-
* before conversion to common clk also enabled UART1 (which isn't
328
-
* handled here and not needed for mmc) and IIM (which is enabled
329
-
* unconditionally above).
330
-
*/
331
-
clk_prepare_enable(clk[scc_gate]);
332
-
333
-
imx_print_silicon_rev("i.MX35", mx35_revision());
334
-
335
282
mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31);
336
283
337
284
return 0;
···
320
305
321
306
static void __init mx35_clocks_init_dt(struct device_node *ccm_node)
322
307
{
308
+
_mx35_clocks_init();
309
+
323
310
clk_data.clks = clk;
324
311
clk_data.clk_num = ARRAY_SIZE(clk);
325
312
of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
326
-
327
-
mx35_clocks_init();
328
313
}
329
314
CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);
+16
drivers/clk/imx/clk-imx51-imx53.c
+16
drivers/clk/imx/clk-imx51-imx53.c
···
130
130
static struct clk *clk[IMX5_CLK_END];
131
131
static struct clk_onecell_data clk_data;
132
132
133
+
static struct clk ** const uart_clks[] __initconst = {
134
+
&clk[IMX5_CLK_UART1_IPG_GATE],
135
+
&clk[IMX5_CLK_UART1_PER_GATE],
136
+
&clk[IMX5_CLK_UART2_IPG_GATE],
137
+
&clk[IMX5_CLK_UART2_PER_GATE],
138
+
&clk[IMX5_CLK_UART3_IPG_GATE],
139
+
&clk[IMX5_CLK_UART3_PER_GATE],
140
+
&clk[IMX5_CLK_UART4_IPG_GATE],
141
+
&clk[IMX5_CLK_UART4_PER_GATE],
142
+
&clk[IMX5_CLK_UART5_IPG_GATE],
143
+
&clk[IMX5_CLK_UART5_PER_GATE],
144
+
NULL
145
+
};
146
+
133
147
static void __init mx5_clocks_common_init(void __iomem *ccm_base)
134
148
{
135
149
clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
···
324
310
clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
325
311
clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
326
312
clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
313
+
314
+
imx_register_uart_clocks(uart_clks);
327
315
}
328
316
329
317
static void __init mx50_clocks_init(struct device_node *np)
+11
-1
drivers/clk/imx/clk-imx6q.c
+11
-1
drivers/clk/imx/clk-imx6q.c
···
119
119
static unsigned int share_count_ssi2;
120
120
static unsigned int share_count_ssi3;
121
121
static unsigned int share_count_mipi_core_cfg;
122
+
static unsigned int share_count_spdif;
122
123
123
124
static inline int clk_on_imx6q(void)
124
125
{
···
130
129
{
131
130
return of_machine_is_compatible("fsl,imx6dl");
132
131
}
132
+
133
+
static struct clk ** const uart_clks[] __initconst = {
134
+
&clk[IMX6QDL_CLK_UART_IPG],
135
+
&clk[IMX6QDL_CLK_UART_SERIAL],
136
+
NULL
137
+
};
133
138
134
139
static void __init imx6q_clocks_init(struct device_node *ccm_node)
135
140
{
···
463
456
clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4);
464
457
clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
465
458
clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
466
-
clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
459
+
clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif);
460
+
clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
467
461
clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
468
462
clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
469
463
clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
···
549
541
/* All existing boards with PCIe use LVDS1 */
550
542
if (IS_ENABLED(CONFIG_PCI_IMX6))
551
543
clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
544
+
545
+
imx_register_uart_clocks(uart_clks);
552
546
}
553
547
CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
+11
-1
drivers/clk/imx/clk-imx6sl.c
+11
-1
drivers/clk/imx/clk-imx6sl.c
···
97
97
static unsigned int share_count_ssi1;
98
98
static unsigned int share_count_ssi2;
99
99
static unsigned int share_count_ssi3;
100
+
static unsigned int share_count_spdif;
100
101
101
102
static struct clk *clks[IMX6SL_CLK_END];
102
103
static struct clk_onecell_data clk_data;
···
184
183
if (arm_div_for_wait == ARM_WAIT_DIV_396M)
185
184
imx6sl_enable_pll_arm(false);
186
185
}
186
+
187
+
static struct clk ** const uart_clks[] __initconst = {
188
+
&clks[IMX6SL_CLK_UART],
189
+
&clks[IMX6SL_CLK_UART_SERIAL],
190
+
NULL
191
+
};
187
192
188
193
static void __init imx6sl_clocks_init(struct device_node *ccm_node)
189
194
{
···
398
391
clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
399
392
clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
400
393
clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
401
-
clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
394
+
clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif);
395
+
clks[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
402
396
clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
403
397
clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
404
398
clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
···
447
439
448
440
clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],
449
441
clks[IMX6SL_CLK_PLL2_PFD2]);
442
+
443
+
imx_register_uart_clocks(uart_clks);
450
444
}
451
445
CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
+9
drivers/clk/imx/clk-imx6sx.c
+9
drivers/clk/imx/clk-imx6sx.c
···
135
135
static u32 share_count_ssi2;
136
136
static u32 share_count_ssi3;
137
137
138
+
static struct clk ** const uart_clks[] __initconst = {
139
+
&clks[IMX6SX_CLK_UART_IPG],
140
+
&clks[IMX6SX_CLK_UART_SERIAL],
141
+
NULL
142
+
};
143
+
138
144
static void __init imx6sx_clocks_init(struct device_node *ccm_node)
139
145
{
140
146
struct device_node *np;
···
460
454
clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
461
455
clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio);
462
456
clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
457
+
clks[IMX6SX_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio);
463
458
clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
464
459
clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
465
460
clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
···
564
557
565
558
clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
566
559
clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
560
+
561
+
imx_register_uart_clocks(uart_clks);
567
562
}
568
563
CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
+18
drivers/clk/imx/clk-imx6ul.c
+18
drivers/clk/imx/clk-imx6ul.c
···
407
407
clk_data.clk_num = ARRAY_SIZE(clks);
408
408
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
409
409
410
+
/*
411
+
* Lower the AHB clock rate before changing the parent clock source,
412
+
* as AHB clock rate can NOT be higher than 133MHz, but its parent
413
+
* will be switched from 396MHz PFD to 528MHz PLL in order to increase
414
+
* AXI clock rate, so we need to lower AHB rate first to make sure at
415
+
* any time, AHB rate is <= 133MHz.
416
+
*/
417
+
clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
418
+
419
+
/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
420
+
clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
421
+
clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);
422
+
clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);
423
+
clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);
424
+
425
+
/* Make sure AHB rate is 132MHz */
426
+
clk_set_rate(clks[IMX6UL_CLK_AHB], 132000000);
427
+
410
428
/* set perclk to from OSC */
411
429
clk_set_parent(clks[IMX6UL_CLK_PERCLK_SEL], clks[IMX6UL_CLK_OSC]);
412
430
+14
drivers/clk/imx/clk-imx7d.c
+14
drivers/clk/imx/clk-imx7d.c
···
363
363
364
364
static struct clk_onecell_data clk_data;
365
365
366
+
static struct clk ** const uart_clks[] __initconst = {
367
+
&clks[IMX7D_UART1_ROOT_CLK],
368
+
&clks[IMX7D_UART2_ROOT_CLK],
369
+
&clks[IMX7D_UART3_ROOT_CLK],
370
+
&clks[IMX7D_UART4_ROOT_CLK],
371
+
&clks[IMX7D_UART5_ROOT_CLK],
372
+
&clks[IMX7D_UART6_ROOT_CLK],
373
+
&clks[IMX7D_UART7_ROOT_CLK],
374
+
NULL
375
+
};
376
+
366
377
static void __init imx7d_clocks_init(struct device_node *ccm_node)
367
378
{
368
379
struct device_node *np;
···
829
818
clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate2("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
830
819
clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate2("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
831
820
clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate2("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
821
+
clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate2("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
832
822
833
823
clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
834
824
···
867
855
868
856
/* set uart module clock's parent clock source that must be great then 80MHz */
869
857
clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
858
+
859
+
imx_register_uart_clocks(uart_clks);
870
860
871
861
}
872
862
CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);
+1
drivers/clk/imx/clk-vf610.c
+1
drivers/clk/imx/clk-vf610.c
···
387
387
388
388
clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));
389
389
clk[VF610_CLK_DAP] = imx_clk_gate("dap", "platform_bus", CCM_CCSR, 24);
390
+
clk[VF610_CLK_OCOTP] = imx_clk_gate("ocotp", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(5));
390
391
391
392
imx_check_clocks(clk, ARRAY_SIZE(clk));
392
393
+38
drivers/clk/imx/clk.c
+38
drivers/clk/imx/clk.c
···
73
73
*val ^= CSCMR1_FIXUP;
74
74
return;
75
75
}
76
+
77
+
static int imx_keep_uart_clocks __initdata;
78
+
static struct clk ** const *imx_uart_clocks __initdata;
79
+
80
+
static int __init imx_keep_uart_clocks_param(char *str)
81
+
{
82
+
imx_keep_uart_clocks = 1;
83
+
84
+
return 0;
85
+
}
86
+
__setup_param("earlycon", imx_keep_uart_earlycon,
87
+
imx_keep_uart_clocks_param, 0);
88
+
__setup_param("earlyprintk", imx_keep_uart_earlyprintk,
89
+
imx_keep_uart_clocks_param, 0);
90
+
91
+
void __init imx_register_uart_clocks(struct clk ** const clks[])
92
+
{
93
+
if (imx_keep_uart_clocks) {
94
+
int i;
95
+
96
+
imx_uart_clocks = clks;
97
+
for (i = 0; imx_uart_clocks[i]; i++)
98
+
clk_prepare_enable(*imx_uart_clocks[i]);
99
+
}
100
+
}
101
+
102
+
static int __init imx_clk_disable_uart(void)
103
+
{
104
+
if (imx_keep_uart_clocks && imx_uart_clocks) {
105
+
int i;
106
+
107
+
for (i = 0; imx_uart_clocks[i]; i++)
108
+
clk_disable_unprepare(*imx_uart_clocks[i]);
109
+
}
110
+
111
+
return 0;
112
+
}
113
+
late_initcall_sync(imx_clk_disable_uart);
+1
drivers/clk/imx/clk.h
+1
drivers/clk/imx/clk.h
+2
-1
include/dt-bindings/clock/imx6qdl-clock.h
+2
-1
include/dt-bindings/clock/imx6qdl-clock.h
+2
-1
include/dt-bindings/clock/imx6sl-clock.h
+2
-1
include/dt-bindings/clock/imx6sl-clock.h
+2
-1
include/dt-bindings/clock/imx6sx-clock.h
+2
-1
include/dt-bindings/clock/imx6sx-clock.h
+2
-1
include/dt-bindings/clock/imx7d-clock.h
+2
-1
include/dt-bindings/clock/imx7d-clock.h
+2
-1
include/dt-bindings/clock/vf610-clock.h
+2
-1
include/dt-bindings/clock/vf610-clock.h