drm/amd/powerplay: drop unused code around thermal range setting

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Leftover of previous cleanups.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Evan Quan and committed by

Alex Deucher 5 years ago 3cd7e415 1e1964b7

+3 -113

6 changed files

expand all

drivers

gpu

drm

amd

powerplay

arcturus_ppt.c

inc

amdgpu_smu.h

navi10_ppt.c

sienna_cichlid_ppt.c

smu_internal.h

smu_v11_0.c

-32

drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

··· 2314 2314 log_buf); 2315 2315 } 2316 2316 2317 - static int arcturus_set_thermal_range(struct smu_context *smu, 2318 - struct smu_temperature_range range) 2319 - { 2320 - struct amdgpu_device *adev = smu->adev; 2321 - int low = SMU_THERMAL_MINIMUM_ALERT_TEMP; 2322 - int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP; 2323 - uint32_t val; 2324 - struct smu_table_context *table_context = &smu->smu_table; 2325 - struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table; 2326 - 2327 - low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, 2328 - range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); 2329 - high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp); 2330 - 2331 - if (low > high) 2332 - return -EINVAL; 2333 - 2334 - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 2335 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 2336 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 2337 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); 2338 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); 2339 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); 2340 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); 2341 - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 2342 - 2343 - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 2344 - 2345 - return 0; 2346 - } 2347 - 2348 2317 static const struct pptable_funcs arcturus_ppt_funcs = { 2349 2318 /* translate smu index into arcturus specific index */ 2350 2319 .get_smu_msg_index = arcturus_get_smu_msg_index, ··· 2396 2427 .set_df_cstate = arcturus_set_df_cstate, 2397 2428 .allow_xgmi_power_down = arcturus_allow_xgmi_power_down, 2398 2429 .log_thermal_throttling_event = arcturus_log_thermal_throttling_event, 2399 - .set_thermal_range = arcturus_set_thermal_range, 2400 2430 }; 2401 2431 2402 2432 void arcturus_set_ppt_funcs(struct smu_context *smu)

-2

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

··· 480 480 int (*set_cpu_power_state)(struct smu_context *smu); 481 481 bool (*is_dpm_running)(struct smu_context *smu); 482 482 int (*tables_init)(struct smu_context *smu, struct smu_table *tables); 483 - int (*set_thermal_fan_table)(struct smu_context *smu); 484 483 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed); 485 484 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 486 485 int (*set_watermarks_table)(struct smu_context *smu, void *watermarks, ··· 571 572 int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu); 572 573 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 573 574 void (*log_thermal_throttling_event)(struct smu_context *smu); 574 - int (*set_thermal_range)(struct smu_context *smu, struct smu_temperature_range range); 575 575 }; 576 576 577 577 typedef enum {

-32

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

··· 2340 2340 return navi10_dummy_pstate_control(smu, true); 2341 2341 } 2342 2342 2343 - static int navi10_set_thermal_range(struct smu_context *smu, 2344 - struct smu_temperature_range range) 2345 - { 2346 - struct amdgpu_device *adev = smu->adev; 2347 - int low = SMU_THERMAL_MINIMUM_ALERT_TEMP; 2348 - int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP; 2349 - uint32_t val; 2350 - struct smu_table_context *table_context = &smu->smu_table; 2351 - struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table; 2352 - 2353 - low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, 2354 - range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); 2355 - high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp); 2356 - 2357 - if (low > high) 2358 - return -EINVAL; 2359 - 2360 - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 2361 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 2362 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 2363 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); 2364 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); 2365 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); 2366 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); 2367 - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 2368 - 2369 - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 2370 - 2371 - return 0; 2372 - } 2373 - 2374 2343 static const struct pptable_funcs navi10_ppt_funcs = { 2375 2344 .tables_init = navi10_tables_init, 2376 2345 .alloc_dpm_context = navi10_allocate_dpm_context, ··· 2421 2452 .run_btc = navi10_run_btc, 2422 2453 .disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround, 2423 2454 .set_power_source = smu_v11_0_set_power_source, 2424 - .set_thermal_range = navi10_set_thermal_range, 2425 2455 }; 2426 2456 2427 2457 void navi10_set_ppt_funcs(struct smu_context *smu)

-32

drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

··· 1818 1818 return val != 0x0; 1819 1819 } 1820 1820 1821 - static int sienna_cichlid_set_thermal_range(struct smu_context *smu, 1822 - struct smu_temperature_range range) 1823 - { 1824 - struct amdgpu_device *adev = smu->adev; 1825 - int low = SMU_THERMAL_MINIMUM_ALERT_TEMP; 1826 - int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP; 1827 - uint32_t val; 1828 - struct smu_table_context *table_context = &smu->smu_table; 1829 - struct smu_11_0_7_powerplay_table *powerplay_table = table_context->power_play_table; 1830 - 1831 - low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, 1832 - range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); 1833 - high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp); 1834 - 1835 - if (low > high) 1836 - return -EINVAL; 1837 - 1838 - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 1839 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 1840 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 1841 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); 1842 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); 1843 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); 1844 - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); 1845 - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1846 - 1847 - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 1848 - 1849 - return 0; 1850 - } 1851 - 1852 1821 static void sienna_cichlid_dump_pptable(struct smu_context *smu) 1853 1822 { 1854 1823 struct smu_table_context *table_context = &smu->smu_table; ··· 2556 2587 .mode1_reset = smu_v11_0_mode1_reset, 2557 2588 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, 2558 2589 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 2559 - .set_thermal_range = sienna_cichlid_set_thermal_range, 2560 2590 }; 2561 2591 2562 2592 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)

-2

drivers/gpu/drm/amd/powerplay/smu_internal.h

··· 60 60 #define smu_populate_umd_state_clk(smu) smu_ppt_funcs(populate_umd_state_clk, 0, smu) 61 61 #define smu_set_default_od8_settings(smu) smu_ppt_funcs(set_default_od8_settings, 0, smu) 62 62 #define smu_tables_init(smu, tab) smu_ppt_funcs(tables_init, 0, smu, tab) 63 - #define smu_set_thermal_fan_table(smu) smu_ppt_funcs(set_thermal_fan_table, 0, smu) 64 63 #define smu_enable_thermal_alert(smu) smu_ppt_funcs(enable_thermal_alert, 0, smu) 65 64 #define smu_disable_thermal_alert(smu) smu_ppt_funcs(disable_thermal_alert, 0, smu) 66 65 #define smu_smc_read_sensor(smu, sensor, data, size) smu_ppt_funcs(read_sensor, -EINVAL, smu, sensor, data, size) ··· 89 90 #define smu_asic_set_performance_level(smu, level) smu_ppt_funcs(set_performance_level, -EINVAL, smu, level) 90 91 #define smu_dump_pptable(smu) smu_ppt_funcs(dump_pptable, 0, smu) 91 92 #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap) 92 - #define smu_set_thermal_range(smu, range) smu_ppt_funcs(set_thermal_range, 0, smu, range) 93 93 #define smu_disable_umc_cdr_12gbps_workaround(smu) smu_ppt_funcs(disable_umc_cdr_12gbps_workaround, 0, smu) 94 94 #define smu_set_power_source(smu, power_src) smu_ppt_funcs(set_power_source, 0, smu, power_src) 95 95 #define smu_i2c_eeprom_init(smu, control) smu_ppt_funcs(i2c_eeprom_init, 0, smu, control)

+3 -13

drivers/gpu/drm/amd/powerplay/smu_v11_0.c

··· 1087 1087 1088 1088 int smu_v11_0_enable_thermal_alert(struct smu_context *smu) 1089 1089 { 1090 - int ret = 0; 1091 - struct amdgpu_device *adev = smu->adev; 1090 + if (smu->smu_table.thermal_controller_type) 1091 + return amdgpu_irq_get(smu->adev, &smu->irq_source, 0); 1092 1092 1093 - if (smu->smu_table.thermal_controller_type) { 1094 - ret = amdgpu_irq_get(adev, &smu->irq_source, 0); 1095 - if (ret) 1096 - return ret; 1097 - 1098 - ret = smu_set_thermal_fan_table(smu); 1099 - if (ret) 1100 - return ret; 1101 - } 1102 - 1103 - return ret; 1093 + return 0; 1104 1094 } 1105 1095 1106 1096 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)