commit 3cd73eedde34c5fd88d62d8523c4260970fdc6fb · tjh.dev/kernel

+1 -17

drivers/net/au1000_eth.c

··· 52 52 #include <linux/mii.h> 53 53 #include <linux/skbuff.h> 54 54 #include <linux/delay.h> 55 + #include <linux/crc32.h> 55 56 #include <asm/mipsregs.h> 56 57 #include <asm/irq.h> 57 58 #include <asm/io.h> ··· 2069 2068 au1000_init(dev); 2070 2069 dev->trans_start = jiffies; 2071 2070 netif_wake_queue(dev); 2072 - } 2073 - 2074 - 2075 - static unsigned const ethernet_polynomial = 0x04c11db7U; 2076 - static inline u32 ether_crc(int length, unsigned char *data) 2077 - { 2078 - int crc = -1; 2079 - 2080 - while(--length >= 0) { 2081 - unsigned char current_octet = *data++; 2082 - int bit; 2083 - for (bit = 0; bit < 8; bit++, current_octet >>= 1) 2084 - crc = (crc << 1) ^ 2085 - ((crc < 0) ^ (current_octet & 1) ? 2086 - ethernet_polynomial : 0); 2087 - } 2088 - return crc; 2089 2071 } 2090 2072 2091 2073 static void set_rx_mode(struct net_device *dev)

+19 -12

drivers/net/ne.c

··· 139 139 140 140 #if defined(CONFIG_PLAT_MAPPI) 141 141 # define DCR_VAL 0x4b 142 - #elif defined(CONFIG_PLAT_OAKS32R) 143 - # define DCR_VAL 0x48 142 + #elif defined(CONFIG_PLAT_OAKS32R) || \ 143 + defined(CONFIG_TOSHIBA_RBTX4927) || defined(CONFIG_TOSHIBA_RBTX4938) 144 + # define DCR_VAL 0x48 /* 8-bit mode */ 144 145 #else 145 146 # define DCR_VAL 0x49 146 147 #endif ··· 397 396 /* We must set the 8390 for word mode. */ 398 397 outb_p(DCR_VAL, ioaddr + EN0_DCFG); 399 398 start_page = NESM_START_PG; 400 - stop_page = NESM_STOP_PG; 399 + 400 + /* 401 + * Realtek RTL8019AS datasheet says that the PSTOP register 402 + * shouldn't exceed 0x60 in 8-bit mode. 403 + * This chip can be identified by reading the signature from 404 + * the remote byte count registers (otherwise write-only)... 405 + */ 406 + if ((DCR_VAL & 0x01) == 0 && /* 8-bit mode */ 407 + inb(ioaddr + EN0_RCNTLO) == 0x50 && 408 + inb(ioaddr + EN0_RCNTHI) == 0x70) 409 + stop_page = 0x60; 410 + else 411 + stop_page = NESM_STOP_PG; 401 412 } else { 402 413 start_page = NE1SM_START_PG; 403 - stop_page = NE1SM_STOP_PG; 414 + stop_page = NE1SM_STOP_PG; 404 415 } 405 416 406 417 #if defined(CONFIG_PLAT_MAPPI) || defined(CONFIG_PLAT_OAKS32R) ··· 522 509 ei_status.name = name; 523 510 ei_status.tx_start_page = start_page; 524 511 ei_status.stop_page = stop_page; 525 - #if defined(CONFIG_TOSHIBA_RBTX4927) || defined(CONFIG_TOSHIBA_RBTX4938) 526 - wordlength = 1; 527 - #endif 528 512 529 - #ifdef CONFIG_PLAT_OAKS32R 530 - ei_status.word16 = 0; 531 - #else 532 - ei_status.word16 = (wordlength == 2); 533 - #endif 513 + /* Use 16-bit mode only if this wasn't overridden by DCR_VAL */ 514 + ei_status.word16 = (wordlength == 2 && (DCR_VAL & 0x01)); 534 515 535 516 ei_status.rx_start_page = start_page + TX_PAGES; 536 517 #ifdef PACKETBUF_MEMSIZE

+117 -100

drivers/net/sky2.c

··· 51 51 #include "sky2.h" 52 52 53 53 #define DRV_NAME "sky2" 54 - #define DRV_VERSION "1.2" 54 + #define DRV_VERSION "1.3" 55 55 #define PFX DRV_NAME " " 56 56 57 57 /* ··· 79 79 #define NAPI_WEIGHT 64 80 80 #define PHY_RETRIES 1000 81 81 82 + #define RING_NEXT(x,s) (((x)+1) & ((s)-1)) 83 + 82 84 static const u32 default_msg = 83 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK 84 86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR ··· 97 95 static int disable_msi = 0; 98 96 module_param(disable_msi, int, 0); 99 97 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 98 + 99 + static int idle_timeout = 100; 100 + module_param(idle_timeout, int, 0); 101 + MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)"); 100 102 101 103 static const struct pci_device_id sky2_id_table[] = { 102 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, ··· 304 298 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 305 299 u16 ctrl, ct1000, adv, pg, ledctrl, ledover; 306 300 307 - if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) { 301 + if (sky2->autoneg == AUTONEG_ENABLE && 302 + (hw->chip_id != CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) { 308 303 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 309 304 310 305 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | ··· 333 326 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); 334 327 335 328 if (sky2->autoneg == AUTONEG_ENABLE && 336 - hw->chip_id == CHIP_ID_YUKON_XL) { 329 + (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) { 337 330 ctrl &= ~PHY_M_PC_DSC_MSK; 338 331 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; 339 332 } ··· 449 442 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 450 443 451 444 /* set LED Function Control register */ 452 - gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 453 - PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 454 - PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 455 - PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 445 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 446 + (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 447 + PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 448 + PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 449 + PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 456 450 457 451 /* set Polarity Control register */ 458 452 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, ··· 467 459 /* restore page register */ 468 460 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 469 461 break; 462 + case CHIP_ID_YUKON_EC_U: 463 + pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 464 + 465 + /* select page 3 to access LED control register */ 466 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 467 + 468 + /* set LED Function Control register */ 469 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 470 + (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 471 + PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ 472 + PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 473 + PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ 474 + 475 + /* set Blink Rate in LED Timer Control Register */ 476 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, 477 + ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); 478 + /* restore page register */ 479 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 480 + break; 470 481 471 482 default: 472 483 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ ··· 494 467 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 495 468 } 496 469 497 - if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { 470 + if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) { 498 471 /* apply fixes in PHY AFE */ 499 - gm_phy_write(hw, port, 22, 255); 472 + pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 473 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 474 + 500 475 /* increase differential signal amplitude in 10BASE-T */ 501 - gm_phy_write(hw, port, 24, 0xaa99); 502 - gm_phy_write(hw, port, 23, 0x2011); 476 + gm_phy_write(hw, port, 0x18, 0xaa99); 477 + gm_phy_write(hw, port, 0x17, 0x2011); 503 478 504 479 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 505 - gm_phy_write(hw, port, 24, 0xa204); 506 - gm_phy_write(hw, port, 23, 0x2002); 480 + gm_phy_write(hw, port, 0x18, 0xa204); 481 + gm_phy_write(hw, port, 0x17, 0x2002); 507 482 508 483 /* set page register to 0 */ 509 - gm_phy_write(hw, port, 22, 0); 484 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 510 485 } else { 511 486 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 512 487 ··· 582 553 583 554 if (sky2->duplex == DUPLEX_FULL) 584 555 reg |= GM_GPCR_DUP_FULL; 556 + 557 + /* turn off pause in 10/100mbps half duplex */ 558 + else if (sky2->speed != SPEED_1000 && 559 + hw->chip_id != CHIP_ID_YUKON_EC_U) 560 + sky2->tx_pause = sky2->rx_pause = 0; 585 561 } else 586 562 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; 587 563 ··· 753 719 { 754 720 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; 755 721 756 - sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE; 722 + sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE); 757 723 return le; 758 724 } 759 725 ··· 769 735 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) 770 736 { 771 737 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; 772 - sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE; 738 + sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); 773 739 return le; 774 740 } 775 741 ··· 1112 1078 /* Modular subtraction in ring */ 1113 1079 static inline int tx_dist(unsigned tail, unsigned head) 1114 1080 { 1115 - return (head - tail) % TX_RING_SIZE; 1081 + return (head - tail) & (TX_RING_SIZE - 1); 1116 1082 } 1117 1083 1118 1084 /* Number of list elements available for next tx */ ··· 1289 1255 le->opcode = OP_BUFFER | HW_OWNER; 1290 1256 1291 1257 fre = sky2->tx_ring 1292 - + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE; 1258 + + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE); 1293 1259 pci_unmap_addr_set(fre, mapaddr, mapping); 1294 1260 } 1295 1261 ··· 1349 1315 1350 1316 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1351 1317 struct tx_ring_info *fre; 1352 - fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE; 1318 + fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE); 1353 1319 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr), 1354 1320 skb_shinfo(skb)->frags[i].size, 1355 1321 PCI_DMA_TODEVICE); ··· 1532 1498 sky2_write8(hw, SK_REG(port, LNK_LED_REG), 1533 1499 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); 1534 1500 1535 - if (hw->chip_id == CHIP_ID_YUKON_XL) { 1501 + if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) { 1536 1502 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 1503 + u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */ 1504 + 1505 + switch(sky2->speed) { 1506 + case SPEED_10: 1507 + led |= PHY_M_LEDC_INIT_CTRL(7); 1508 + break; 1509 + 1510 + case SPEED_100: 1511 + led |= PHY_M_LEDC_STA1_CTRL(7); 1512 + break; 1513 + 1514 + case SPEED_1000: 1515 + led |= PHY_M_LEDC_STA0_CTRL(7); 1516 + break; 1517 + } 1537 1518 1538 1519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 1539 - gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 1540 - PHY_M_LEDC_INIT_CTRL(sky2->speed == 1541 - SPEED_10 ? 7 : 0) | 1542 - PHY_M_LEDC_STA1_CTRL(sky2->speed == 1543 - SPEED_100 ? 7 : 0) | 1544 - PHY_M_LEDC_STA0_CTRL(sky2->speed == 1545 - SPEED_1000 ? 7 : 0)); 1520 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led); 1546 1521 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 1547 1522 } 1548 1523 ··· 1626 1583 sky2->speed = sky2_phy_speed(hw, aux); 1627 1584 1628 1585 /* Pause bits are offset (9..8) */ 1629 - if (hw->chip_id == CHIP_ID_YUKON_XL) 1586 + if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) 1630 1587 aux >>= 6; 1631 1588 1632 1589 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; ··· 1902 1859 static int sky2_status_intr(struct sky2_hw *hw, int to_do) 1903 1860 { 1904 1861 int work_done = 0; 1862 + u16 hwidx = sky2_read16(hw, STAT_PUT_IDX); 1905 1863 1906 1864 rmb(); 1907 1865 1908 - for(;;) { 1866 + while (hw->st_idx != hwidx) { 1909 1867 struct sky2_status_le *le = hw->st_le + hw->st_idx; 1910 1868 struct net_device *dev; 1911 1869 struct sky2_port *sky2; 1912 1870 struct sk_buff *skb; 1913 1871 u32 status; 1914 1872 u16 length; 1915 - u8 link, opcode; 1916 1873 1917 - opcode = le->opcode; 1918 - if (!opcode) 1919 - break; 1920 - opcode &= ~HW_OWNER; 1874 + hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE); 1921 1875 1922 - hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE; 1923 - le->opcode = 0; 1924 - 1925 - link = le->link; 1926 - BUG_ON(link >= 2); 1927 - dev = hw->dev[link]; 1876 + BUG_ON(le->link >= 2); 1877 + dev = hw->dev[le->link]; 1928 1878 1929 1879 sky2 = netdev_priv(dev); 1930 1880 length = le->length; 1931 1881 status = le->status; 1932 1882 1933 - switch (opcode) { 1883 + switch (le->opcode & ~HW_OWNER) { 1934 1884 case OP_RXSTAT: 1935 1885 skb = sky2_receive(sky2, length, status); 1936 1886 if (!skb) ··· 1963 1927 1964 1928 case OP_TXINDEXLE: 1965 1929 /* TX index reports status for both ports */ 1966 - sky2_tx_done(hw->dev[0], status & 0xffff); 1930 + BUILD_BUG_ON(TX_RING_SIZE > 0x1000); 1931 + sky2_tx_done(hw->dev[0], status & 0xfff); 1967 1932 if (hw->dev[1]) 1968 1933 sky2_tx_done(hw->dev[1], 1969 1934 ((status >> 24) & 0xff) ··· 1974 1937 default: 1975 1938 if (net_ratelimit()) 1976 1939 printk(KERN_WARNING PFX 1977 - "unknown status opcode 0x%x\n", opcode); 1978 - break; 1940 + "unknown status opcode 0x%x\n", le->opcode); 1941 + goto exit_loop; 1979 1942 } 1980 1943 } 1981 1944 ··· 2126 2089 */ 2127 2090 static void sky2_idle(unsigned long arg) 2128 2091 { 2129 - struct net_device *dev = (struct net_device *) arg; 2092 + struct sky2_hw *hw = (struct sky2_hw *) arg; 2093 + struct net_device *dev = hw->dev[0]; 2130 2094 2131 - local_irq_disable(); 2132 2095 if (__netif_rx_schedule_prep(dev)) 2133 2096 __netif_rx_schedule(dev); 2134 - local_irq_enable(); 2097 + 2098 + mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout)); 2135 2099 } 2136 2100 2137 2101 ··· 2143 2105 int work_done = 0; 2144 2106 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); 2145 2107 2146 - restart_poll: 2147 - if (unlikely(status & ~Y2_IS_STAT_BMU)) { 2148 - if (status & Y2_IS_HW_ERR) 2149 - sky2_hw_intr(hw); 2108 + if (status & Y2_IS_HW_ERR) 2109 + sky2_hw_intr(hw); 2150 2110 2151 - if (status & Y2_IS_IRQ_PHY1) 2152 - sky2_phy_intr(hw, 0); 2111 + if (status & Y2_IS_IRQ_PHY1) 2112 + sky2_phy_intr(hw, 0); 2153 2113 2154 - if (status & Y2_IS_IRQ_PHY2) 2155 - sky2_phy_intr(hw, 1); 2114 + if (status & Y2_IS_IRQ_PHY2) 2115 + sky2_phy_intr(hw, 1); 2156 2116 2157 - if (status & Y2_IS_IRQ_MAC1) 2158 - sky2_mac_intr(hw, 0); 2117 + if (status & Y2_IS_IRQ_MAC1) 2118 + sky2_mac_intr(hw, 0); 2159 2119 2160 - if (status & Y2_IS_IRQ_MAC2) 2161 - sky2_mac_intr(hw, 1); 2120 + if (status & Y2_IS_IRQ_MAC2) 2121 + sky2_mac_intr(hw, 1); 2162 2122 2163 - if (status & Y2_IS_CHK_RX1) 2164 - sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1); 2123 + if (status & Y2_IS_CHK_RX1) 2124 + sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1); 2165 2125 2166 - if (status & Y2_IS_CHK_RX2) 2167 - sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2); 2126 + if (status & Y2_IS_CHK_RX2) 2127 + sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2); 2168 2128 2169 - if (status & Y2_IS_CHK_TXA1) 2170 - sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1); 2129 + if (status & Y2_IS_CHK_TXA1) 2130 + sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1); 2171 2131 2172 - if (status & Y2_IS_CHK_TXA2) 2173 - sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2); 2174 - } 2132 + if (status & Y2_IS_CHK_TXA2) 2133 + sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2); 2175 2134 2176 - if (status & Y2_IS_STAT_BMU) { 2177 - work_done += sky2_status_intr(hw, work_limit - work_done); 2178 - *budget -= work_done; 2179 - dev0->quota -= work_done; 2180 - 2181 - if (work_done >= work_limit) 2182 - return 1; 2183 - 2135 + if (status & Y2_IS_STAT_BMU) 2184 2136 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 2185 - } 2186 2137 2187 - mod_timer(&hw->idle_timer, jiffies + HZ); 2138 + work_done = sky2_status_intr(hw, work_limit); 2139 + *budget -= work_done; 2140 + dev0->quota -= work_done; 2188 2141 2189 - local_irq_disable(); 2190 - __netif_rx_complete(dev0); 2142 + if (work_done >= work_limit) 2143 + return 1; 2144 + 2145 + netif_rx_complete(dev0); 2191 2146 2192 2147 status = sky2_read32(hw, B0_Y2_SP_LISR); 2193 - 2194 - if (unlikely(status)) { 2195 - /* More work pending, try and keep going */ 2196 - if (__netif_rx_schedule_prep(dev0)) { 2197 - __netif_rx_reschedule(dev0, work_done); 2198 - status = sky2_read32(hw, B0_Y2_SP_EISR); 2199 - local_irq_enable(); 2200 - goto restart_poll; 2201 - } 2202 - } 2203 - 2204 - local_irq_enable(); 2205 2148 return 0; 2206 2149 } 2207 2150 ··· 2261 2242 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], 2262 2243 hw->chip_id, hw->chip_rev); 2263 2244 return -EOPNOTSUPP; 2264 - } 2265 - 2266 - /* This chip is new and not tested yet */ 2267 - if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 2268 - pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n", 2269 - pci_name(hw->pdev)); 2270 - pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n"); 2271 2245 } 2272 2246 2273 2247 /* disable ASF */ ··· 3314 3302 3315 3303 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 3316 3304 3317 - setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) dev); 3305 + setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw); 3306 + if (idle_timeout > 0) 3307 + mod_timer(&hw->idle_timer, 3308 + jiffies + msecs_to_jiffies(idle_timeout)); 3318 3309 3319 3310 pci_set_drvdata(pdev, hw); 3320 3311 ··· 3357 3342 del_timer_sync(&hw->idle_timer); 3358 3343 3359 3344 sky2_write32(hw, B0_IMSK, 0); 3345 + synchronize_irq(hw->pdev->irq); 3346 + 3360 3347 dev0 = hw->dev[0]; 3361 3348 dev1 = hw->dev[1]; 3362 3349 if (dev1)

+3

drivers/net/sky2.h

··· 378 378 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */ 379 379 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */ 380 380 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */ 381 + 382 + CHIP_REV_YU_EC_U_A0 = 0, 383 + CHIP_REV_YU_EC_U_A1 = 1, 381 384 }; 382 385 383 386 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */

+3 -9

drivers/net/spider_net.c

··· 1652 1652 { SPIDER_NET_GFTRESTRT, SPIDER_NET_RESTART_VALUE }, 1653 1653 1654 1654 { SPIDER_NET_GMRWOLCTRL, 0 }, 1655 + { SPIDER_NET_GTESTMD, 0x10000000 }, 1656 + { SPIDER_NET_GTTQMSK, 0x00400040 }, 1655 1657 { SPIDER_NET_GTESTMD, 0 }, 1656 1658 1657 1659 { SPIDER_NET_GMACINTEN, 0 }, ··· 1794 1792 if (phy->def->ops->setup_forced) 1795 1793 phy->def->ops->setup_forced(phy, SPEED_1000, DUPLEX_FULL); 1796 1794 1797 - /* the following two writes could be moved to sungem_phy.c */ 1798 - /* enable fiber mode */ 1799 - spider_net_write_phy(card->netdev, 1, MII_NCONFIG, 0x9020); 1800 - /* LEDs active in both modes, autosense prio = fiber */ 1801 - spider_net_write_phy(card->netdev, 1, MII_NCONFIG, 0x945f); 1802 - 1803 - /* switch off fibre autoneg */ 1804 - spider_net_write_phy(card->netdev, 1, MII_NCONFIG, 0xfc01); 1805 - spider_net_write_phy(card->netdev, 1, 0x0b, 0x0004); 1795 + phy->def->ops->enable_fiber(phy); 1806 1796 1807 1797 phy->def->ops->read_link(phy); 1808 1798 pr_info("Found %s with %i Mbps, %s-duplex.\n", phy->def->name,

+2

drivers/net/spider_net.h

··· 120 120 #define SPIDER_NET_GMRUAFILnR 0x00000500 121 121 #define SPIDER_NET_GMRUA0FIL15R 0x00000578 122 122 123 + #define SPIDER_NET_GTTQMSK 0x00000934 124 + 123 125 /* RX DMA controller registers, all 0x00000a.. are for DMA controller A, 124 126 * 0x00000b.. for DMA controller B, etc. */ 125 127 #define SPIDER_NET_GDADCHA 0x00000a00

+45

drivers/net/sungem_phy.c

··· 329 329 return 0; 330 330 } 331 331 332 + static int bcm5421_enable_fiber(struct mii_phy* phy) 333 + { 334 + /* enable fiber mode */ 335 + phy_write(phy, MII_NCONFIG, 0x9020); 336 + /* LEDs active in both modes, autosense prio = fiber */ 337 + phy_write(phy, MII_NCONFIG, 0x945f); 338 + 339 + /* switch off fibre autoneg */ 340 + phy_write(phy, MII_NCONFIG, 0xfc01); 341 + phy_write(phy, 0x0b, 0x0004); 342 + 343 + return 0; 344 + } 345 + 346 + static int bcm5461_enable_fiber(struct mii_phy* phy) 347 + { 348 + phy_write(phy, MII_NCONFIG, 0xfc0c); 349 + phy_write(phy, MII_BMCR, 0x4140); 350 + phy_write(phy, MII_NCONFIG, 0xfc0b); 351 + phy_write(phy, MII_BMCR, 0x0140); 352 + 353 + return 0; 354 + } 355 + 332 356 static int bcm54xx_setup_aneg(struct mii_phy *phy, u32 advertise) 333 357 { 334 358 u16 ctl, adv; ··· 786 762 .setup_forced = bcm54xx_setup_forced, 787 763 .poll_link = genmii_poll_link, 788 764 .read_link = bcm54xx_read_link, 765 + .enable_fiber = bcm5421_enable_fiber, 789 766 }; 790 767 791 768 static struct mii_phy_def bcm5421_phy_def = { ··· 815 790 .features = MII_GBIT_FEATURES, 816 791 .magic_aneg = 1, 817 792 .ops = &bcm5421k2_phy_ops 793 + }; 794 + 795 + static struct mii_phy_ops bcm5461_phy_ops = { 796 + .init = bcm5421_init, 797 + .suspend = generic_suspend, 798 + .setup_aneg = bcm54xx_setup_aneg, 799 + .setup_forced = bcm54xx_setup_forced, 800 + .poll_link = genmii_poll_link, 801 + .read_link = bcm54xx_read_link, 802 + .enable_fiber = bcm5461_enable_fiber, 803 + }; 804 + 805 + static struct mii_phy_def bcm5461_phy_def = { 806 + .phy_id = 0x002060c0, 807 + .phy_id_mask = 0xfffffff0, 808 + .name = "BCM5461", 809 + .features = MII_GBIT_FEATURES, 810 + .magic_aneg = 1, 811 + .ops = &bcm5461_phy_ops 818 812 }; 819 813 820 814 /* Broadcom BCM 5462 built-in Vesta */ ··· 901 857 &bcm5411_phy_def, 902 858 &bcm5421_phy_def, 903 859 &bcm5421k2_phy_def, 860 + &bcm5461_phy_def, 904 861 &bcm5462V_phy_def, 905 862 &marvell_phy_def, 906 863 &genmii_phy_def,

+1

drivers/net/sungem_phy.h

··· 12 12 int (*setup_forced)(struct mii_phy *phy, int speed, int fd); 13 13 int (*poll_link)(struct mii_phy *phy); 14 14 int (*read_link)(struct mii_phy *phy); 15 + int (*enable_fiber)(struct mii_phy *phy); 15 16 }; 16 17 17 18 /* Structure used to statically define an mii/gii based PHY */

+27 -18

drivers/net/wireless/bcm43xx/bcm43xx_main.c

··· 939 939 return 0; 940 940 } 941 941 942 - static void bcm43xx_geo_init(struct bcm43xx_private *bcm) 942 + static int bcm43xx_geo_init(struct bcm43xx_private *bcm) 943 943 { 944 - struct ieee80211_geo geo; 944 + struct ieee80211_geo *geo; 945 945 struct ieee80211_channel *chan; 946 946 int have_a = 0, have_bg = 0; 947 947 int i; ··· 949 949 struct bcm43xx_phyinfo *phy; 950 950 const char *iso_country; 951 951 952 - memset(&geo, 0, sizeof(geo)); 952 + geo = kzalloc(sizeof(*geo), GFP_KERNEL); 953 + if (!geo) 954 + return -ENOMEM; 955 + 953 956 for (i = 0; i < bcm->nr_80211_available; i++) { 954 957 phy = &(bcm->core_80211_ext[i].phy); 955 958 switch (phy->type) { ··· 970 967 iso_country = bcm43xx_locale_iso(bcm->sprom.locale); 971 968 972 969 if (have_a) { 973 - for (i = 0, channel = 0; channel < 201; channel++) { 974 - chan = &geo.a[i++]; 970 + for (i = 0, channel = IEEE80211_52GHZ_MIN_CHANNEL; 971 + channel <= IEEE80211_52GHZ_MAX_CHANNEL; channel++) { 972 + chan = &geo->a[i++]; 975 973 chan->freq = bcm43xx_channel_to_freq_a(channel); 976 974 chan->channel = channel; 977 975 } 978 - geo.a_channels = i; 976 + geo->a_channels = i; 979 977 } 980 978 if (have_bg) { 981 - for (i = 0, channel = 1; channel < 15; channel++) { 982 - chan = &geo.bg[i++]; 979 + for (i = 0, channel = IEEE80211_24GHZ_MIN_CHANNEL; 980 + channel <= IEEE80211_24GHZ_MAX_CHANNEL; channel++) { 981 + chan = &geo->bg[i++]; 983 982 chan->freq = bcm43xx_channel_to_freq_bg(channel); 984 983 chan->channel = channel; 985 984 } 986 - geo.bg_channels = i; 985 + geo->bg_channels = i; 987 986 } 988 - memcpy(geo.name, iso_country, 2); 987 + memcpy(geo->name, iso_country, 2); 989 988 if (0 /*TODO: Outdoor use only */) 990 - geo.name[2] = 'O'; 989 + geo->name[2] = 'O'; 991 990 else if (0 /*TODO: Indoor use only */) 992 - geo.name[2] = 'I'; 991 + geo->name[2] = 'I'; 993 992 else 994 - geo.name[2] = ' '; 995 - geo.name[3] = '\0'; 993 + geo->name[2] = ' '; 994 + geo->name[3] = '\0'; 996 995 997 - ieee80211_set_geo(bcm->ieee, &geo); 996 + ieee80211_set_geo(bcm->ieee, geo); 997 + kfree(geo); 998 + 999 + return 0; 998 1000 } 999 1001 1000 1002 /* DummyTransmission function, as documented on ··· 3487 3479 goto err_80211_unwind; 3488 3480 bcm43xx_wireless_core_disable(bcm); 3489 3481 } 3482 + err = bcm43xx_geo_init(bcm); 3483 + if (err) 3484 + goto err_80211_unwind; 3490 3485 bcm43xx_pctl_set_crystal(bcm, 0); 3491 3486 3492 3487 /* Set the MAC address in the networking subsystem */ 3493 - if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A) 3488 + if (is_valid_ether_addr(bcm->sprom.et1macaddr)) 3494 3489 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6); 3495 3490 else 3496 3491 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6); 3497 - 3498 - bcm43xx_geo_init(bcm); 3499 3492 3500 3493 snprintf(bcm->nick, IW_ESSID_MAX_SIZE, 3501 3494 "Broadcom %04X", bcm->chip_id);

+4 -2

drivers/net/wireless/bcm43xx/bcm43xx_main.h

··· 118 118 static inline 119 119 int bcm43xx_is_valid_channel_a(u8 channel) 120 120 { 121 - return (channel <= 200); 121 + return (channel >= IEEE80211_52GHZ_MIN_CHANNEL 122 + && channel <= IEEE80211_52GHZ_MAX_CHANNEL); 122 123 } 123 124 static inline 124 125 int bcm43xx_is_valid_channel_bg(u8 channel) 125 126 { 126 - return (channel >= 1 && channel <= 14); 127 + return (channel >= IEEE80211_24GHZ_MIN_CHANNEL 128 + && channel <= IEEE80211_24GHZ_MAX_CHANNEL); 127 129 } 128 130 static inline 129 131 int bcm43xx_is_valid_channel(struct bcm43xx_private *bcm,

+1 -1

drivers/net/wireless/bcm43xx/bcm43xx_phy.c

··· 1287 1287 if (radio->revision == 8) 1288 1288 bcm43xx_phy_write(bcm, 0x0805, 0x3230); 1289 1289 bcm43xx_phy_init_pctl(bcm); 1290 - if (bcm->chip_id == 0x4306 && bcm->chip_package != 2) { 1290 + if (bcm->chip_id == 0x4306 && bcm->chip_package == 2) { 1291 1291 bcm43xx_phy_write(bcm, 0x0429, 1292 1292 bcm43xx_phy_read(bcm, 0x0429) & 0xBFFF); 1293 1293 bcm43xx_phy_write(bcm, 0x04C3,

+5 -2

drivers/net/wireless/bcm43xx/bcm43xx_wx.c

··· 182 182 mode = BCM43xx_INITIAL_IWMODE; 183 183 184 184 bcm43xx_lock_mmio(bcm, flags); 185 - if (bcm->ieee->iw_mode != mode) 186 - bcm43xx_set_iwmode(bcm, mode); 185 + if (bcm->initialized) { 186 + if (bcm->ieee->iw_mode != mode) 187 + bcm43xx_set_iwmode(bcm, mode); 188 + } else 189 + bcm->ieee->iw_mode = mode; 187 190 bcm43xx_unlock_mmio(bcm, flags); 188 191 189 192 return 0;

+8 -10

include/linux/netdevice.h

··· 831 831 __netif_rx_schedule(dev); 832 832 } 833 833 834 - 835 - static inline void __netif_rx_reschedule(struct net_device *dev, int undo) 836 - { 837 - dev->quota += undo; 838 - list_add_tail(&dev->poll_list, &__get_cpu_var(softnet_data).poll_list); 839 - __raise_softirq_irqoff(NET_RX_SOFTIRQ); 840 - } 841 - 842 - /* Try to reschedule poll. Called by dev->poll() after netif_rx_complete(). */ 834 + /* Try to reschedule poll. Called by dev->poll() after netif_rx_complete(). 835 + * Do not inline this? 836 + */ 843 837 static inline int netif_rx_reschedule(struct net_device *dev, int undo) 844 838 { 845 839 if (netif_rx_schedule_prep(dev)) { 846 840 unsigned long flags; 841 + 842 + dev->quota += undo; 843 + 847 844 local_irq_save(flags); 848 - __netif_rx_reschedule(dev, undo); 845 + list_add_tail(&dev->poll_list, &__get_cpu_var(softnet_data).poll_list); 846 + __raise_softirq_irqoff(NET_RX_SOFTIRQ); 849 847 local_irq_restore(flags); 850 848 return 1; 851 849 }

+4 -2

include/net/ieee80211.h

··· 955 955 956 956 #define IEEE80211_24GHZ_MIN_CHANNEL 1 957 957 #define IEEE80211_24GHZ_MAX_CHANNEL 14 958 - #define IEEE80211_24GHZ_CHANNELS 14 958 + #define IEEE80211_24GHZ_CHANNELS (IEEE80211_24GHZ_MAX_CHANNEL - \ 959 + IEEE80211_24GHZ_MIN_CHANNEL + 1) 959 960 960 961 #define IEEE80211_52GHZ_MIN_CHANNEL 34 961 962 #define IEEE80211_52GHZ_MAX_CHANNEL 165 962 - #define IEEE80211_52GHZ_CHANNELS 131 963 + #define IEEE80211_52GHZ_CHANNELS (IEEE80211_52GHZ_MAX_CHANNEL - \ 964 + IEEE80211_52GHZ_MIN_CHANNEL + 1) 963 965 964 966 enum { 965 967 IEEE80211_CH_PASSIVE_ONLY = (1 << 0),

+2 -1

include/net/ieee80211softmac.h

··· 204 204 205 205 /* couple of flags */ 206 206 u8 scanning:1, /* protects scanning from being done multiple times at once */ 207 - associated:1; 207 + associated:1, 208 + running:1; 208 209 209 210 struct ieee80211softmac_scaninfo *scaninfo; 210 211 struct ieee80211softmac_assoc_info associnfo;

+15 -2

net/ieee80211/softmac/ieee80211softmac_assoc.c

··· 51 51 spin_lock_irqsave(&mac->lock, flags); 52 52 mac->associnfo.associating = 1; 53 53 mac->associated = 0; /* just to make sure */ 54 - spin_unlock_irqrestore(&mac->lock, flags); 55 54 56 55 /* Set a timer for timeout */ 57 56 /* FIXME: make timeout configurable */ 58 - schedule_delayed_work(&mac->associnfo.timeout, 5 * HZ); 57 + if (likely(mac->running)) 58 + schedule_delayed_work(&mac->associnfo.timeout, 5 * HZ); 59 + spin_unlock_irqrestore(&mac->lock, flags); 59 60 } 60 61 61 62 void ··· 320 319 u16 status = le16_to_cpup(&resp->status); 321 320 struct ieee80211softmac_network *network = NULL; 322 321 unsigned long flags; 322 + 323 + if (unlikely(!mac->running)) 324 + return -ENODEV; 323 325 324 326 spin_lock_irqsave(&mac->lock, flags); 325 327 ··· 381 377 { 382 378 struct ieee80211softmac_device *mac = ieee80211_priv(dev); 383 379 unsigned long flags; 380 + 381 + if (unlikely(!mac->running)) 382 + return -ENODEV; 383 + 384 384 if (memcmp(disassoc->header.addr2, mac->associnfo.bssid, ETH_ALEN)) 385 385 return 0; 386 + 386 387 if (memcmp(disassoc->header.addr1, mac->dev->dev_addr, ETH_ALEN)) 387 388 return 0; 389 + 388 390 dprintk(KERN_INFO PFX "got disassoc frame\n"); 389 391 netif_carrier_off(dev); 390 392 spin_lock_irqsave(&mac->lock, flags); ··· 409 399 { 410 400 struct ieee80211softmac_device *mac = ieee80211_priv(dev); 411 401 struct ieee80211softmac_network *network; 402 + 403 + if (unlikely(!mac->running)) 404 + return -ENODEV; 412 405 413 406 network = ieee80211softmac_get_network_by_bssid(mac, resp->header.addr3); 414 407 if (!network) {

+14 -2

net/ieee80211/softmac/ieee80211softmac_auth.c

··· 86 86 87 87 /* Lock and set flags */ 88 88 spin_lock_irqsave(&mac->lock, flags); 89 + if (unlikely(!mac->running)) { 90 + /* Prevent reschedule on workqueue flush */ 91 + spin_unlock_irqrestore(&mac->lock, flags); 92 + return; 93 + } 89 94 net->authenticated = 0; 90 95 net->authenticating = 1; 91 96 /* add a timeout call so we eventually give up waiting for an auth reply */ ··· 129 124 unsigned long flags; 130 125 u8 * data; 131 126 127 + if (unlikely(!mac->running)) 128 + return -ENODEV; 129 + 132 130 /* Find correct auth queue item */ 133 131 spin_lock_irqsave(&mac->lock, flags); 134 132 list_for_each(list_ptr, &mac->auth_queue) { ··· 306 298 307 299 /* can't transmit data right now... */ 308 300 netif_carrier_off(mac->dev); 309 - /* let's try to re-associate */ 310 - schedule_work(&mac->associnfo.work); 311 301 spin_unlock_irqrestore(&mac->lock, flags); 312 302 } 313 303 ··· 344 338 struct ieee80211softmac_network *net = NULL; 345 339 struct ieee80211softmac_device *mac = ieee80211_priv(dev); 346 340 341 + if (unlikely(!mac->running)) 342 + return -ENODEV; 343 + 347 344 if (!deauth) { 348 345 dprintk("deauth without deauth packet. eek!\n"); 349 346 return 0; ··· 369 360 } 370 361 371 362 ieee80211softmac_deauth_from_net(mac, net); 363 + 364 + /* let's try to re-associate */ 365 + schedule_work(&mac->associnfo.work); 372 366 return 0; 373 367 }

+4

net/ieee80211/softmac/ieee80211softmac_module.c

··· 89 89 ieee80211softmac_wait_for_scan(sm); 90 90 91 91 spin_lock_irqsave(&sm->lock, flags); 92 + sm->running = 0; 93 + 92 94 /* Free all pending assoc work items */ 93 95 cancel_delayed_work(&sm->associnfo.work); 94 96 ··· 206 204 assert(0); 207 205 if (mac->txrates_change) 208 206 mac->txrates_change(dev, change, &oldrates); 207 + 208 + mac->running = 1; 209 209 } 210 210 EXPORT_SYMBOL_GPL(ieee80211softmac_start); 211 211

+8

net/ieee80211/softmac/ieee80211softmac_scan.c

··· 115 115 // TODO: is this if correct, or should we do this only if scanning from assoc request? 116 116 if (sm->associnfo.req_essid.len) 117 117 ieee80211softmac_send_mgt_frame(sm, &sm->associnfo.req_essid, IEEE80211_STYPE_PROBE_REQ, 0); 118 + 119 + spin_lock_irqsave(&sm->lock, flags); 120 + if (unlikely(!sm->running)) { 121 + /* Prevent reschedule on workqueue flush */ 122 + spin_unlock_irqrestore(&sm->lock, flags); 123 + break; 124 + } 118 125 schedule_delayed_work(&si->softmac_scan, IEEE80211SOFTMAC_PROBE_DELAY); 126 + spin_unlock_irqrestore(&sm->lock, flags); 119 127 return; 120 128 } else { 121 129 dprintk(PFX "Not probing Channel %d (not allowed here)\n", si->channels[current_channel_idx].channel);