tjh.dev / kernel
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sh: Remove stale microdev board

This board was an early prototype platform for early SH4 CPUs and related
to the already removed SH5 cayman platform.

The microdev board itself has been kept in the tree for this long despite
being in a bad shape even 20 years ago when it got merged, with no working
PCI support and ugly workarounds for its I/O port implementation that
try to emulate PC style peripheral access despite being quite different
in reality.

As far as I can tell, the ethernet, display, USB and PCI devices on it
already broke at some point (afbb9d8d5266b, 46bc85872040a), so I think
we can just removeit entirely.

Link: https://lore.kernel.org/lkml/09094baf-dadf-4bce-9f63-f2a1f255f9a8@app.fastmail.com/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Link: https://lore.kernel.org/r/20230914155523.3839811-1-arnd@kernel.org
Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>

authored by

Arnd Bergmann and committed by
John Paul Adrian Glaubitz 3ca64d06 0bb80ecc

+1 -773
+1 -2
arch/sh/Kconfig
··· 124 124 125 125 config NO_IOPORT_MAP 126 126 def_bool !PCI 127 - depends on !SH_SH4202_MICRODEV && !SH_SHMIN && !SH_HP6XX && \ 128 - !SH_SOLUTION_ENGINE 127 + depends on !SH_SHMIN && !SH_HP6XX && !SH_SOLUTION_ENGINE 129 128 130 129 config IO_TRAPPED 131 130 bool
-7
arch/sh/boards/Kconfig
··· 289 289 Select if configuring for a Renesas EDOSK7760 290 290 evaluation board. 291 291 292 - config SH_SH4202_MICRODEV 293 - bool "SH4-202 MicroDev" 294 - depends on CPU_SUBTYPE_SH4_202 295 - help 296 - Select SH4-202 MicroDev if configuring for a SuperH MicroDev board 297 - with an SH4-202 CPU. 298 - 299 292 config SH_LANDISK 300 293 bool "LANDISK" 301 294 depends on CPU_SUBTYPE_SH7751R
-1
arch/sh/boards/Makefile
··· 33 33 obj-$(CONFIG_SH_SDK7786) += mach-sdk7786/ 34 34 obj-$(CONFIG_SH_X3PROTO) += mach-x3proto/ 35 35 obj-$(CONFIG_SH_SH7763RDP) += mach-sh7763rdp/ 36 - obj-$(CONFIG_SH_SH4202_MICRODEV)+= mach-microdev/ 37 36 obj-$(CONFIG_SH_LANDISK) += mach-landisk/ 38 37 obj-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2/ 39 38 obj-$(CONFIG_SH_RSK) += mach-rsk/
-6
arch/sh/boards/mach-microdev/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - # 3 - # Makefile for the SuperH MicroDev specific parts of the kernel 4 - # 5 - 6 - obj-y := setup.o irq.o io.o fdc37c93xapm.o
-157
arch/sh/boards/mach-microdev/fdc37c93xapm.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Setup for the SMSC FDC37C93xAPM 4 - * 5 - * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) 6 - * Copyright (C) 2003, 2004 SuperH, Inc. 7 - * Copyright (C) 2004, 2005 Paul Mundt 8 - * 9 - * SuperH SH4-202 MicroDev board support. 10 - */ 11 - #include <linux/init.h> 12 - #include <linux/ioport.h> 13 - #include <linux/io.h> 14 - #include <linux/err.h> 15 - #include <mach/microdev.h> 16 - 17 - #define SMSC_CONFIG_PORT_ADDR (0x3F0) 18 - #define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR 19 - #define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1) 20 - 21 - #define SMSC_ENTER_CONFIG_KEY 0x55 22 - #define SMSC_EXIT_CONFIG_KEY 0xaa 23 - 24 - #define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */ 25 - #define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */ 26 - #define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */ 27 - #define SMSC_ACTIVATE_INDEX 0x30 /* Activate */ 28 - #define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */ 29 - #define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */ 30 - #define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */ 31 - #define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */ 32 - #define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */ 33 - #define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */ 34 - 35 - #define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */ 36 - #define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */ 37 - #define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */ 38 - #define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */ 39 - #define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */ 40 - #define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */ 41 - #define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */ 42 - 43 - #define SMSC_READ_INDEXED(index) ({ \ 44 - outb((index), SMSC_INDEX_PORT_ADDR); \ 45 - inb(SMSC_DATA_PORT_ADDR); }) 46 - #define SMSC_WRITE_INDEXED(val, index) ({ \ 47 - outb((index), SMSC_INDEX_PORT_ADDR); \ 48 - outb((val), SMSC_DATA_PORT_ADDR); }) 49 - 50 - #define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */ 51 - #define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */ 52 - #define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */ 53 - #define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */ 54 - 55 - #define SERIAL1_PRIMARY_BASE 0x03f8 56 - #define SERIAL2_PRIMARY_BASE 0x02f8 57 - 58 - #define MSB(x) ( (x) >> 8 ) 59 - #define LSB(x) ( (x) & 0xff ) 60 - 61 - /* General-Purpose base address on CPU-board FPGA */ 62 - #define MICRODEV_FPGA_GP_BASE 0xa6100000ul 63 - 64 - static int __init smsc_superio_setup(void) 65 - { 66 - 67 - unsigned char devid, devrev; 68 - 69 - /* Initially the chip is in run state */ 70 - /* Put it into configuration state */ 71 - outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); 72 - 73 - /* Read device ID info */ 74 - devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX); 75 - devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX); 76 - 77 - if ((devid == 0x30) && (devrev == 0x01)) 78 - printk("SMSC FDC37C93xAPM SuperIO device detected\n"); 79 - else 80 - return -ENODEV; 81 - 82 - /* Select the keyboard device */ 83 - SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX); 84 - /* enable it */ 85 - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); 86 - /* enable the interrupts */ 87 - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX); 88 - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX); 89 - 90 - /* Select the Serial #1 device */ 91 - SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX); 92 - /* enable it */ 93 - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); 94 - /* program with port addresses */ 95 - SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); 96 - SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); 97 - SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX); 98 - /* enable the interrupts */ 99 - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX); 100 - 101 - /* Select the Serial #2 device */ 102 - SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX); 103 - /* enable it */ 104 - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); 105 - /* program with port addresses */ 106 - SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); 107 - SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); 108 - SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX); 109 - /* enable the interrupts */ 110 - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX); 111 - 112 - /* Select the IDE#1 device */ 113 - SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX); 114 - /* enable it */ 115 - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); 116 - /* program with port addresses */ 117 - SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); 118 - SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); 119 - SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0); 120 - SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1); 121 - SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX); 122 - SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX); 123 - /* select the interrupt */ 124 - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX); 125 - 126 - /* Select the IDE#2 device */ 127 - SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX); 128 - /* enable it */ 129 - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); 130 - /* program with port addresses */ 131 - SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); 132 - SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); 133 - SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0); 134 - SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1); 135 - /* select the interrupt */ 136 - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX); 137 - 138 - /* Select the configuration registers */ 139 - SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX); 140 - /* enable the appropriate GPIO pins for IDE functionality: 141 - * bit[0] In/Out 1==input; 0==output 142 - * bit[1] Polarity 1==invert; 0==no invert 143 - * bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable 144 - * bit[3:4] Function Select 00==original; 01==Alternate Function #1 145 - */ 146 - SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */ 147 - SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */ 148 - SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */ 149 - SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */ 150 - SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */ 151 - 152 - /* Exit the configuration state */ 153 - outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); 154 - 155 - return 0; 156 - } 157 - device_initcall(smsc_superio_setup);
-123
arch/sh/boards/mach-microdev/io.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * linux/arch/sh/boards/superh/microdev/io.c 4 - * 5 - * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) 6 - * Copyright (C) 2003, 2004 SuperH, Inc. 7 - * Copyright (C) 2004 Paul Mundt 8 - * 9 - * SuperH SH4-202 MicroDev board support. 10 - */ 11 - 12 - #include <linux/init.h> 13 - #include <linux/pci.h> 14 - #include <linux/wait.h> 15 - #include <asm/io.h> 16 - #include <mach/microdev.h> 17 - 18 - /* 19 - * we need to have a 'safe' address to re-direct all I/O requests 20 - * that we do not explicitly wish to handle. This safe address 21 - * must have the following properies: 22 - * 23 - * * writes are ignored (no exception) 24 - * * reads are benign (no side-effects) 25 - * * accesses of width 1, 2 and 4-bytes are all valid. 26 - * 27 - * The Processor Version Register (PVR) has these properties. 28 - */ 29 - #define PVR 0xff000030 /* Processor Version Register */ 30 - 31 - 32 - #define IO_IDE2_BASE 0x170ul /* I/O base for SMSC FDC37C93xAPM IDE #2 */ 33 - #define IO_IDE1_BASE 0x1f0ul /* I/O base for SMSC FDC37C93xAPM IDE #1 */ 34 - #define IO_ISP1161_BASE 0x290ul /* I/O port for Philips ISP1161x USB chip */ 35 - #define IO_SERIAL2_BASE 0x2f8ul /* I/O base for SMSC FDC37C93xAPM Serial #2 */ 36 - #define IO_LAN91C111_BASE 0x300ul /* I/O base for SMSC LAN91C111 Ethernet chip */ 37 - #define IO_IDE2_MISC 0x376ul /* I/O misc for SMSC FDC37C93xAPM IDE #2 */ 38 - #define IO_SUPERIO_BASE 0x3f0ul /* I/O base for SMSC FDC37C93xAPM SuperIO chip */ 39 - #define IO_IDE1_MISC 0x3f6ul /* I/O misc for SMSC FDC37C93xAPM IDE #1 */ 40 - #define IO_SERIAL1_BASE 0x3f8ul /* I/O base for SMSC FDC37C93xAPM Serial #1 */ 41 - 42 - #define IO_ISP1161_EXTENT 0x04ul /* I/O extent for Philips ISP1161x USB chip */ 43 - #define IO_LAN91C111_EXTENT 0x10ul /* I/O extent for SMSC LAN91C111 Ethernet chip */ 44 - #define IO_SUPERIO_EXTENT 0x02ul /* I/O extent for SMSC FDC37C93xAPM SuperIO chip */ 45 - #define IO_IDE_EXTENT 0x08ul /* I/O extent for IDE Task Register set */ 46 - #define IO_SERIAL_EXTENT 0x10ul 47 - 48 - #define IO_LAN91C111_PHYS 0xa7500000ul /* Physical address of SMSC LAN91C111 Ethernet chip */ 49 - #define IO_ISP1161_PHYS 0xa7700000ul /* Physical address of Philips ISP1161x USB chip */ 50 - #define IO_SUPERIO_PHYS 0xa7800000ul /* Physical address of SMSC FDC37C93xAPM SuperIO chip */ 51 - 52 - /* 53 - * map I/O ports to memory-mapped addresses 54 - */ 55 - void __iomem *microdev_ioport_map(unsigned long offset, unsigned int len) 56 - { 57 - unsigned long result; 58 - 59 - if ((offset >= IO_LAN91C111_BASE) && 60 - (offset < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) { 61 - /* 62 - * SMSC LAN91C111 Ethernet chip 63 - */ 64 - result = IO_LAN91C111_PHYS + offset - IO_LAN91C111_BASE; 65 - } else if ((offset >= IO_SUPERIO_BASE) && 66 - (offset < IO_SUPERIO_BASE + IO_SUPERIO_EXTENT)) { 67 - /* 68 - * SMSC FDC37C93xAPM SuperIO chip 69 - * 70 - * Configuration Registers 71 - */ 72 - result = IO_SUPERIO_PHYS + (offset << 1); 73 - } else if (((offset >= IO_IDE1_BASE) && 74 - (offset < IO_IDE1_BASE + IO_IDE_EXTENT)) || 75 - (offset == IO_IDE1_MISC)) { 76 - /* 77 - * SMSC FDC37C93xAPM SuperIO chip 78 - * 79 - * IDE #1 80 - */ 81 - result = IO_SUPERIO_PHYS + (offset << 1); 82 - } else if (((offset >= IO_IDE2_BASE) && 83 - (offset < IO_IDE2_BASE + IO_IDE_EXTENT)) || 84 - (offset == IO_IDE2_MISC)) { 85 - /* 86 - * SMSC FDC37C93xAPM SuperIO chip 87 - * 88 - * IDE #2 89 - */ 90 - result = IO_SUPERIO_PHYS + (offset << 1); 91 - } else if ((offset >= IO_SERIAL1_BASE) && 92 - (offset < IO_SERIAL1_BASE + IO_SERIAL_EXTENT)) { 93 - /* 94 - * SMSC FDC37C93xAPM SuperIO chip 95 - * 96 - * Serial #1 97 - */ 98 - result = IO_SUPERIO_PHYS + (offset << 1); 99 - } else if ((offset >= IO_SERIAL2_BASE) && 100 - (offset < IO_SERIAL2_BASE + IO_SERIAL_EXTENT)) { 101 - /* 102 - * SMSC FDC37C93xAPM SuperIO chip 103 - * 104 - * Serial #2 105 - */ 106 - result = IO_SUPERIO_PHYS + (offset << 1); 107 - } else if ((offset >= IO_ISP1161_BASE) && 108 - (offset < IO_ISP1161_BASE + IO_ISP1161_EXTENT)) { 109 - /* 110 - * Philips USB ISP1161x chip 111 - */ 112 - result = IO_ISP1161_PHYS + offset - IO_ISP1161_BASE; 113 - } else { 114 - /* 115 - * safe default. 116 - */ 117 - printk("Warning: unexpected port in %s( offset = 0x%lx )\n", 118 - __func__, offset); 119 - result = PVR; 120 - } 121 - 122 - return (void __iomem *)result; 123 - }
-150
arch/sh/boards/mach-microdev/irq.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * arch/sh/boards/superh/microdev/irq.c 4 - * 5 - * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) 6 - * 7 - * SuperH SH4-202 MicroDev board support. 8 - */ 9 - 10 - #include <linux/init.h> 11 - #include <linux/irq.h> 12 - #include <linux/interrupt.h> 13 - #include <asm/io.h> 14 - #include <mach/microdev.h> 15 - 16 - #define NUM_EXTERNAL_IRQS 16 /* IRL0 .. IRL15 */ 17 - 18 - static const struct { 19 - unsigned char fpgaIrq; 20 - unsigned char mapped; 21 - const char *name; 22 - } fpgaIrqTable[NUM_EXTERNAL_IRQS] = { 23 - { 0, 0, "unused" }, /* IRQ #0 IRL=15 0x200 */ 24 - { MICRODEV_FPGA_IRQ_KEYBOARD, 1, "keyboard" }, /* IRQ #1 IRL=14 0x220 */ 25 - { MICRODEV_FPGA_IRQ_SERIAL1, 1, "Serial #1"}, /* IRQ #2 IRL=13 0x240 */ 26 - { MICRODEV_FPGA_IRQ_ETHERNET, 1, "Ethernet" }, /* IRQ #3 IRL=12 0x260 */ 27 - { MICRODEV_FPGA_IRQ_SERIAL2, 0, "Serial #2"}, /* IRQ #4 IRL=11 0x280 */ 28 - { 0, 0, "unused" }, /* IRQ #5 IRL=10 0x2a0 */ 29 - { 0, 0, "unused" }, /* IRQ #6 IRL=9 0x2c0 */ 30 - { MICRODEV_FPGA_IRQ_USB_HC, 1, "USB" }, /* IRQ #7 IRL=8 0x2e0 */ 31 - { MICRODEV_IRQ_PCI_INTA, 1, "PCI INTA" }, /* IRQ #8 IRL=7 0x300 */ 32 - { MICRODEV_IRQ_PCI_INTB, 1, "PCI INTB" }, /* IRQ #9 IRL=6 0x320 */ 33 - { MICRODEV_IRQ_PCI_INTC, 1, "PCI INTC" }, /* IRQ #10 IRL=5 0x340 */ 34 - { MICRODEV_IRQ_PCI_INTD, 1, "PCI INTD" }, /* IRQ #11 IRL=4 0x360 */ 35 - { MICRODEV_FPGA_IRQ_MOUSE, 1, "mouse" }, /* IRQ #12 IRL=3 0x380 */ 36 - { MICRODEV_FPGA_IRQ_IDE2, 1, "IDE #2" }, /* IRQ #13 IRL=2 0x3a0 */ 37 - { MICRODEV_FPGA_IRQ_IDE1, 1, "IDE #1" }, /* IRQ #14 IRL=1 0x3c0 */ 38 - { 0, 0, "unused" }, /* IRQ #15 IRL=0 0x3e0 */ 39 - }; 40 - 41 - #if (MICRODEV_LINUX_IRQ_KEYBOARD != 1) 42 - # error Inconsistancy in defining the IRQ# for Keyboard! 43 - #endif 44 - 45 - #if (MICRODEV_LINUX_IRQ_ETHERNET != 3) 46 - # error Inconsistancy in defining the IRQ# for Ethernet! 47 - #endif 48 - 49 - #if (MICRODEV_LINUX_IRQ_USB_HC != 7) 50 - # error Inconsistancy in defining the IRQ# for USB! 51 - #endif 52 - 53 - #if (MICRODEV_LINUX_IRQ_MOUSE != 12) 54 - # error Inconsistancy in defining the IRQ# for PS/2 Mouse! 55 - #endif 56 - 57 - #if (MICRODEV_LINUX_IRQ_IDE2 != 13) 58 - # error Inconsistancy in defining the IRQ# for secondary IDE! 59 - #endif 60 - 61 - #if (MICRODEV_LINUX_IRQ_IDE1 != 14) 62 - # error Inconsistancy in defining the IRQ# for primary IDE! 63 - #endif 64 - 65 - static void disable_microdev_irq(struct irq_data *data) 66 - { 67 - unsigned int irq = data->irq; 68 - unsigned int fpgaIrq; 69 - 70 - if (irq >= NUM_EXTERNAL_IRQS) 71 - return; 72 - if (!fpgaIrqTable[irq].mapped) 73 - return; 74 - 75 - fpgaIrq = fpgaIrqTable[irq].fpgaIrq; 76 - 77 - /* disable interrupts on the FPGA INTC register */ 78 - __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG); 79 - } 80 - 81 - static void enable_microdev_irq(struct irq_data *data) 82 - { 83 - unsigned int irq = data->irq; 84 - unsigned long priorityReg, priorities, pri; 85 - unsigned int fpgaIrq; 86 - 87 - if (unlikely(irq >= NUM_EXTERNAL_IRQS)) 88 - return; 89 - if (unlikely(!fpgaIrqTable[irq].mapped)) 90 - return; 91 - 92 - pri = 15 - irq; 93 - 94 - fpgaIrq = fpgaIrqTable[irq].fpgaIrq; 95 - priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq); 96 - 97 - /* set priority for the interrupt */ 98 - priorities = __raw_readl(priorityReg); 99 - priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq); 100 - priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri); 101 - __raw_writel(priorities, priorityReg); 102 - 103 - /* enable interrupts on the FPGA INTC register */ 104 - __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG); 105 - } 106 - 107 - static struct irq_chip microdev_irq_type = { 108 - .name = "MicroDev-IRQ", 109 - .irq_unmask = enable_microdev_irq, 110 - .irq_mask = disable_microdev_irq, 111 - }; 112 - 113 - /* This function sets the desired irq handler to be a MicroDev type */ 114 - static void __init make_microdev_irq(unsigned int irq) 115 - { 116 - disable_irq_nosync(irq); 117 - irq_set_chip_and_handler(irq, &microdev_irq_type, handle_level_irq); 118 - disable_microdev_irq(irq_get_irq_data(irq)); 119 - } 120 - 121 - extern void __init init_microdev_irq(void) 122 - { 123 - int i; 124 - 125 - /* disable interrupts on the FPGA INTC register */ 126 - __raw_writel(~0ul, MICRODEV_FPGA_INTDSB_REG); 127 - 128 - for (i = 0; i < NUM_EXTERNAL_IRQS; i++) 129 - make_microdev_irq(i); 130 - } 131 - 132 - extern void microdev_print_fpga_intc_status(void) 133 - { 134 - volatile unsigned int * const intenb = (unsigned int*)MICRODEV_FPGA_INTENB_REG; 135 - volatile unsigned int * const intdsb = (unsigned int*)MICRODEV_FPGA_INTDSB_REG; 136 - volatile unsigned int * const intpria = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(0); 137 - volatile unsigned int * const intprib = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(8); 138 - volatile unsigned int * const intpric = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(16); 139 - volatile unsigned int * const intprid = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(24); 140 - volatile unsigned int * const intsrc = (unsigned int*)MICRODEV_FPGA_INTSRC_REG; 141 - volatile unsigned int * const intreq = (unsigned int*)MICRODEV_FPGA_INTREQ_REG; 142 - 143 - printk("-------------------------- microdev_print_fpga_intc_status() ------------------\n"); 144 - printk("FPGA_INTENB = 0x%08x\n", *intenb); 145 - printk("FPGA_INTDSB = 0x%08x\n", *intdsb); 146 - printk("FPGA_INTSRC = 0x%08x\n", *intsrc); 147 - printk("FPGA_INTREQ = 0x%08x\n", *intreq); 148 - printk("FPGA_INTPRI[3..0] = %08x:%08x:%08x:%08x\n", *intprid, *intpric, *intprib, *intpria); 149 - printk("-------------------------------------------------------------------------------\n"); 150 - }
-197
arch/sh/boards/mach-microdev/setup.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * arch/sh/boards/superh/microdev/setup.c 4 - * 5 - * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) 6 - * Copyright (C) 2003, 2004 SuperH, Inc. 7 - * Copyright (C) 2004, 2005 Paul Mundt 8 - * 9 - * SuperH SH4-202 MicroDev board support. 10 - */ 11 - #include <linux/init.h> 12 - #include <linux/platform_device.h> 13 - #include <linux/ioport.h> 14 - #include <video/s1d13xxxfb.h> 15 - #include <mach/microdev.h> 16 - #include <asm/io.h> 17 - #include <asm/machvec.h> 18 - #include <linux/sizes.h> 19 - 20 - static struct resource smc91x_resources[] = { 21 - [0] = { 22 - .start = 0x300, 23 - .end = 0x300 + SZ_4K - 1, 24 - .flags = IORESOURCE_MEM, 25 - }, 26 - [1] = { 27 - .start = MICRODEV_LINUX_IRQ_ETHERNET, 28 - .end = MICRODEV_LINUX_IRQ_ETHERNET, 29 - .flags = IORESOURCE_IRQ, 30 - }, 31 - }; 32 - 33 - static struct platform_device smc91x_device = { 34 - .name = "smc91x", 35 - .id = -1, 36 - .num_resources = ARRAY_SIZE(smc91x_resources), 37 - .resource = smc91x_resources, 38 - }; 39 - 40 - static struct s1d13xxxfb_regval s1d13806_initregs[] = { 41 - { S1DREG_MISC, 0x00 }, 42 - { S1DREG_COM_DISP_MODE, 0x00 }, 43 - { S1DREG_GPIO_CNF0, 0x00 }, 44 - { S1DREG_GPIO_CNF1, 0x00 }, 45 - { S1DREG_GPIO_CTL0, 0x00 }, 46 - { S1DREG_GPIO_CTL1, 0x00 }, 47 - { S1DREG_CLK_CNF, 0x02 }, 48 - { S1DREG_LCD_CLK_CNF, 0x01 }, 49 - { S1DREG_CRT_CLK_CNF, 0x03 }, 50 - { S1DREG_MPLUG_CLK_CNF, 0x03 }, 51 - { S1DREG_CPU2MEM_WST_SEL, 0x02 }, 52 - { S1DREG_SDRAM_REF_RATE, 0x03 }, 53 - { S1DREG_SDRAM_TC0, 0x00 }, 54 - { S1DREG_SDRAM_TC1, 0x01 }, 55 - { S1DREG_MEM_CNF, 0x80 }, 56 - { S1DREG_PANEL_TYPE, 0x25 }, 57 - { S1DREG_MOD_RATE, 0x00 }, 58 - { S1DREG_LCD_DISP_HWIDTH, 0x63 }, 59 - { S1DREG_LCD_NDISP_HPER, 0x1e }, 60 - { S1DREG_TFT_FPLINE_START, 0x06 }, 61 - { S1DREG_TFT_FPLINE_PWIDTH, 0x03 }, 62 - { S1DREG_LCD_DISP_VHEIGHT0, 0x57 }, 63 - { S1DREG_LCD_DISP_VHEIGHT1, 0x02 }, 64 - { S1DREG_LCD_NDISP_VPER, 0x00 }, 65 - { S1DREG_TFT_FPFRAME_START, 0x0a }, 66 - { S1DREG_TFT_FPFRAME_PWIDTH, 0x81 }, 67 - { S1DREG_LCD_DISP_MODE, 0x03 }, 68 - { S1DREG_LCD_MISC, 0x00 }, 69 - { S1DREG_LCD_DISP_START0, 0x00 }, 70 - { S1DREG_LCD_DISP_START1, 0x00 }, 71 - { S1DREG_LCD_DISP_START2, 0x00 }, 72 - { S1DREG_LCD_MEM_OFF0, 0x90 }, 73 - { S1DREG_LCD_MEM_OFF1, 0x01 }, 74 - { S1DREG_LCD_PIX_PAN, 0x00 }, 75 - { S1DREG_LCD_DISP_FIFO_HTC, 0x00 }, 76 - { S1DREG_LCD_DISP_FIFO_LTC, 0x00 }, 77 - { S1DREG_CRT_DISP_HWIDTH, 0x63 }, 78 - { S1DREG_CRT_NDISP_HPER, 0x1f }, 79 - { S1DREG_CRT_HRTC_START, 0x04 }, 80 - { S1DREG_CRT_HRTC_PWIDTH, 0x8f }, 81 - { S1DREG_CRT_DISP_VHEIGHT0, 0x57 }, 82 - { S1DREG_CRT_DISP_VHEIGHT1, 0x02 }, 83 - { S1DREG_CRT_NDISP_VPER, 0x1b }, 84 - { S1DREG_CRT_VRTC_START, 0x00 }, 85 - { S1DREG_CRT_VRTC_PWIDTH, 0x83 }, 86 - { S1DREG_TV_OUT_CTL, 0x10 }, 87 - { S1DREG_CRT_DISP_MODE, 0x05 }, 88 - { S1DREG_CRT_DISP_START0, 0x00 }, 89 - { S1DREG_CRT_DISP_START1, 0x00 }, 90 - { S1DREG_CRT_DISP_START2, 0x00 }, 91 - { S1DREG_CRT_MEM_OFF0, 0x20 }, 92 - { S1DREG_CRT_MEM_OFF1, 0x03 }, 93 - { S1DREG_CRT_PIX_PAN, 0x00 }, 94 - { S1DREG_CRT_DISP_FIFO_HTC, 0x00 }, 95 - { S1DREG_CRT_DISP_FIFO_LTC, 0x00 }, 96 - { S1DREG_LCD_CUR_CTL, 0x00 }, 97 - { S1DREG_LCD_CUR_START, 0x01 }, 98 - { S1DREG_LCD_CUR_XPOS0, 0x00 }, 99 - { S1DREG_LCD_CUR_XPOS1, 0x00 }, 100 - { S1DREG_LCD_CUR_YPOS0, 0x00 }, 101 - { S1DREG_LCD_CUR_YPOS1, 0x00 }, 102 - { S1DREG_LCD_CUR_BCTL0, 0x00 }, 103 - { S1DREG_LCD_CUR_GCTL0, 0x00 }, 104 - { S1DREG_LCD_CUR_RCTL0, 0x00 }, 105 - { S1DREG_LCD_CUR_BCTL1, 0x1f }, 106 - { S1DREG_LCD_CUR_GCTL1, 0x3f }, 107 - { S1DREG_LCD_CUR_RCTL1, 0x1f }, 108 - { S1DREG_LCD_CUR_FIFO_HTC, 0x00 }, 109 - { S1DREG_CRT_CUR_CTL, 0x00 }, 110 - { S1DREG_CRT_CUR_START, 0x01 }, 111 - { S1DREG_CRT_CUR_XPOS0, 0x00 }, 112 - { S1DREG_CRT_CUR_XPOS1, 0x00 }, 113 - { S1DREG_CRT_CUR_YPOS0, 0x00 }, 114 - { S1DREG_CRT_CUR_YPOS1, 0x00 }, 115 - { S1DREG_CRT_CUR_BCTL0, 0x00 }, 116 - { S1DREG_CRT_CUR_GCTL0, 0x00 }, 117 - { S1DREG_CRT_CUR_RCTL0, 0x00 }, 118 - { S1DREG_CRT_CUR_BCTL1, 0x1f }, 119 - { S1DREG_CRT_CUR_GCTL1, 0x3f }, 120 - { S1DREG_CRT_CUR_RCTL1, 0x1f }, 121 - { S1DREG_CRT_CUR_FIFO_HTC, 0x00 }, 122 - { S1DREG_BBLT_CTL0, 0x00 }, 123 - { S1DREG_BBLT_CTL1, 0x00 }, 124 - { S1DREG_BBLT_CC_EXP, 0x00 }, 125 - { S1DREG_BBLT_OP, 0x00 }, 126 - { S1DREG_BBLT_SRC_START0, 0x00 }, 127 - { S1DREG_BBLT_SRC_START1, 0x00 }, 128 - { S1DREG_BBLT_SRC_START2, 0x00 }, 129 - { S1DREG_BBLT_DST_START0, 0x00 }, 130 - { S1DREG_BBLT_DST_START1, 0x00 }, 131 - { S1DREG_BBLT_DST_START2, 0x00 }, 132 - { S1DREG_BBLT_MEM_OFF0, 0x00 }, 133 - { S1DREG_BBLT_MEM_OFF1, 0x00 }, 134 - { S1DREG_BBLT_WIDTH0, 0x00 }, 135 - { S1DREG_BBLT_WIDTH1, 0x00 }, 136 - { S1DREG_BBLT_HEIGHT0, 0x00 }, 137 - { S1DREG_BBLT_HEIGHT1, 0x00 }, 138 - { S1DREG_BBLT_BGC0, 0x00 }, 139 - { S1DREG_BBLT_BGC1, 0x00 }, 140 - { S1DREG_BBLT_FGC0, 0x00 }, 141 - { S1DREG_BBLT_FGC1, 0x00 }, 142 - { S1DREG_LKUP_MODE, 0x00 }, 143 - { S1DREG_LKUP_ADDR, 0x00 }, 144 - { S1DREG_PS_CNF, 0x10 }, 145 - { S1DREG_PS_STATUS, 0x00 }, 146 - { S1DREG_CPU2MEM_WDOGT, 0x00 }, 147 - { S1DREG_COM_DISP_MODE, 0x02 }, 148 - }; 149 - 150 - static struct s1d13xxxfb_pdata s1d13806_platform_data = { 151 - .initregs = s1d13806_initregs, 152 - .initregssize = ARRAY_SIZE(s1d13806_initregs), 153 - }; 154 - 155 - static struct resource s1d13806_resources[] = { 156 - [0] = { 157 - .start = 0x07200000, 158 - .end = 0x07200000 + SZ_2M - 1, 159 - .flags = IORESOURCE_MEM, 160 - }, 161 - [1] = { 162 - .start = 0x07000000, 163 - .end = 0x07000000 + SZ_2M - 1, 164 - .flags = IORESOURCE_MEM, 165 - }, 166 - }; 167 - 168 - static struct platform_device s1d13806_device = { 169 - .name = "s1d13806fb", 170 - .id = -1, 171 - .num_resources = ARRAY_SIZE(s1d13806_resources), 172 - .resource = s1d13806_resources, 173 - 174 - .dev = { 175 - .platform_data = &s1d13806_platform_data, 176 - }, 177 - }; 178 - 179 - static struct platform_device *microdev_devices[] __initdata = { 180 - &smc91x_device, 181 - &s1d13806_device, 182 - }; 183 - 184 - static int __init microdev_devices_setup(void) 185 - { 186 - return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices)); 187 - } 188 - device_initcall(microdev_devices_setup); 189 - 190 - /* 191 - * The Machine Vector 192 - */ 193 - static struct sh_machine_vector mv_sh4202_microdev __initmv = { 194 - .mv_name = "SH4-202 MicroDev", 195 - .mv_ioport_map = microdev_ioport_map, 196 - .mv_init_irq = init_microdev_irq, 197 - };
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arch/sh/configs/microdev_defconfig
··· 1 - CONFIG_BSD_PROCESS_ACCT=y 2 - CONFIG_LOG_BUF_SHIFT=14 3 - CONFIG_BLK_DEV_INITRD=y 4 - # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 5 - # CONFIG_BLK_DEV_BSG is not set 6 - CONFIG_CPU_SUBTYPE_SH4_202=y 7 - CONFIG_FLATMEM_MANUAL=y 8 - CONFIG_SH_SH4202_MICRODEV=y 9 - CONFIG_SH_DMA=y 10 - CONFIG_SH_DMA_API=y 11 - CONFIG_HEARTBEAT=y 12 - CONFIG_PREEMPT=y 13 - CONFIG_CMDLINE_OVERWRITE=y 14 - CONFIG_CMDLINE="console=ttySC0,115200 root=/dev/hda1" 15 - CONFIG_SUPERHYWAY=y 16 - CONFIG_NET=y 17 - CONFIG_INET=y 18 - CONFIG_IP_PNP=y 19 - # CONFIG_IPV6 is not set 20 - # CONFIG_FW_LOADER is not set 21 - CONFIG_BLK_DEV_RAM=y 22 - CONFIG_NETDEVICES=y 23 - CONFIG_NET_ETHERNET=y 24 - CONFIG_SMC91X=y 25 - # CONFIG_INPUT is not set 26 - # CONFIG_SERIO is not set 27 - # CONFIG_VT is not set 28 - CONFIG_SERIAL_SH_SCI=y 29 - CONFIG_SERIAL_SH_SCI_CONSOLE=y 30 - CONFIG_EXT2_FS=y 31 - CONFIG_EXT3_FS=y 32 - # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 33 - CONFIG_VFAT_FS=y 34 - CONFIG_PROC_KCORE=y 35 - CONFIG_TMPFS=y 36 - CONFIG_HUGETLBFS=y 37 - CONFIG_NFS_FS=y 38 - CONFIG_NFS_V3=y 39 - CONFIG_NFS_V4=y 40 - CONFIG_ROOT_NFS=y 41 - CONFIG_CRYPTO_ECB=y 42 - # CONFIG_CRYPTO_ANSI_CPRNG is not set
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arch/sh/include/mach-common/mach/microdev.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 2 - * 3 - * linux/include/asm-sh/microdev.h 4 - * 5 - * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) 6 - * 7 - * Definitions for the SuperH SH4-202 MicroDev board. 8 - */ 9 - #ifndef __ASM_SH_MICRODEV_H 10 - #define __ASM_SH_MICRODEV_H 11 - 12 - extern void init_microdev_irq(void); 13 - extern void microdev_print_fpga_intc_status(void); 14 - 15 - /* 16 - * The following are useful macros for manipulating the interrupt 17 - * controller (INTC) on the CPU-board FPGA. should be noted that there 18 - * is an INTC on the FPGA, and a separate INTC on the SH4-202 core - 19 - * these are two different things, both of which need to be prorammed to 20 - * correctly route - unfortunately, they have the same name and 21 - * abbreviations! 22 - */ 23 - #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */ 24 - #define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */ 25 - #define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */ 26 - #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */ 27 - #define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */ 28 - #define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */ 29 - #define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */ 30 - #define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */ 31 - #define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */ 32 - 33 - 34 - /* 35 - * The following are the IRQ numbers for the Linux Kernel for external 36 - * interrupts. i.e. the numbers seen by 'cat /proc/interrupt'. 37 - */ 38 - #define MICRODEV_LINUX_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ 39 - #define MICRODEV_LINUX_IRQ_SERIAL1 2 /* SuperIO Serial #1 */ 40 - #define MICRODEV_LINUX_IRQ_ETHERNET 3 /* on-board Ethnernet */ 41 - #define MICRODEV_LINUX_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ 42 - #define MICRODEV_LINUX_IRQ_USB_HC 7 /* on-board USB HC */ 43 - #define MICRODEV_LINUX_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ 44 - #define MICRODEV_LINUX_IRQ_IDE2 13 /* SuperIO IDE #2 */ 45 - #define MICRODEV_LINUX_IRQ_IDE1 14 /* SuperIO IDE #1 */ 46 - 47 - /* 48 - * The following are the IRQ numbers for the INTC on the FPGA for 49 - * external interrupts. i.e. the bits in the INTC registers in the 50 - * FPGA. 51 - */ 52 - #define MICRODEV_FPGA_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ 53 - #define MICRODEV_FPGA_IRQ_SERIAL1 3 /* SuperIO Serial #1 */ 54 - #define MICRODEV_FPGA_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ 55 - #define MICRODEV_FPGA_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ 56 - #define MICRODEV_FPGA_IRQ_IDE1 14 /* SuperIO IDE #1 */ 57 - #define MICRODEV_FPGA_IRQ_IDE2 15 /* SuperIO IDE #2 */ 58 - #define MICRODEV_FPGA_IRQ_USB_HC 16 /* on-board USB HC */ 59 - #define MICRODEV_FPGA_IRQ_ETHERNET 18 /* on-board Ethnernet */ 60 - 61 - #define MICRODEV_IRQ_PCI_INTA 8 62 - #define MICRODEV_IRQ_PCI_INTB 9 63 - #define MICRODEV_IRQ_PCI_INTC 10 64 - #define MICRODEV_IRQ_PCI_INTD 11 65 - 66 - #define __IO_PREFIX microdev 67 - #include <asm/io_generic.h> 68 - 69 - #endif /* __ASM_SH_MICRODEV_H */
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drivers/net/ethernet/smsc/smc91x.h
··· 114 114 (lp)->cfg.pxa_u16_align4) 115 115 116 116 117 - #elif defined(CONFIG_SH_SH4202_MICRODEV) 118 - 119 - #define SMC_CAN_USE_8BIT 0 120 - #define SMC_CAN_USE_16BIT 1 121 - #define SMC_CAN_USE_32BIT 0 122 - 123 - #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) 124 - #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) 125 - #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) 126 - #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) 127 - #define SMC_outw(lp, v, a, r) outw(v, (a) + (r) - 0xa0000000) 128 - #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) 129 - #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) 130 - #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) 131 - #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) 132 - #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) 133 - 134 - #define SMC_IRQ_FLAGS (0) 135 - 136 117 #elif defined(CONFIG_ATARI) 137 118 138 119 #define SMC_CAN_USE_8BIT 1