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perf vendor events power10: Add metric events JSON file for power10 platform
Add PMU metric JSON file for power10 platform.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Reviewed-by: Paul Clarke <pc@us.ibm.com>
Cc: Athira Jajeev <atrajeev@linux.vnet.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Cc: Nageswara R Sastry <rnsastry@linux.ibm.com>
Cc: linuxppc-dev@lists.ozlabs.org
Link: http://lore.kernel.org/lkml/20211108060010.177517-1-kjain@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
authored by
Kajol Jain
and committed by
Arnaldo Carvalho de Melo
3ca3af7d
438f1a9f
+676
+676
tools/perf/pmu-events/arch/powerpc/power10/metrics.json
+676
tools/perf/pmu-events/arch/powerpc/power10/metrics.json
···
1
+
[
2
+
{
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+
"BriefDescription": "Percentage of cycles that are run cycles",
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+
"MetricExpr": "PM_RUN_CYC / PM_CYC * 100",
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+
"MetricGroup": "General",
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+
"MetricName": "RUN_CYCLES_RATE",
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"ScaleUnit": "1%"
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},
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{
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"BriefDescription": "Average cycles per completed instruction",
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"MetricExpr": "PM_CYC / PM_INST_CMPL",
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"MetricGroup": "CPI",
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"MetricName": "CYCLES_PER_INSTRUCTION"
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},
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{
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"BriefDescription": "Average cycles per completed instruction when dispatch was stalled for any reason",
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"MetricExpr": "PM_DISP_STALL_CYC / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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"MetricName": "DISPATCHED_CPI"
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},
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{
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"BriefDescription": "Average cycles per completed instruction when dispatch was stalled because there was a flush",
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+
"MetricExpr": "PM_DISP_STALL_FLUSH / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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"MetricName": "DISPATCHED_FLUSH_CPI"
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+
},
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{
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"BriefDescription": "Average cycles per completed instruction when dispatch was stalled because the MMU was handling a translation miss",
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+
"MetricExpr": "PM_DISP_STALL_TRANSLATION / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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"MetricName": "DISPATCHED_TRANSLATION_CPI"
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+
},
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{
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"BriefDescription": "Average cycles per completed instruction when dispatch was stalled waiting to resolve an instruction ERAT miss",
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"MetricExpr": "PM_DISP_STALL_IERAT_ONLY_MISS / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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+
"MetricName": "DISPATCHED_IERAT_ONLY_MISS_CPI"
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+
},
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{
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"BriefDescription": "Average cycles per completed instruction when dispatch was stalled waiting to resolve an instruction TLB miss",
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+
"MetricExpr": "PM_DISP_STALL_ITLB_MISS / PM_RUN_INST_CMPL",
42
+
"MetricGroup": "CPI",
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+
"MetricName": "DISPATCHED_ITLB_MISS_CPI"
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+
},
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{
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"BriefDescription": "Average cycles per completed instruction when dispatch was stalled due to an icache miss",
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"MetricExpr": "PM_DISP_STALL_IC_MISS / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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+
"MetricName": "DISPATCHED_IC_MISS_CPI"
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+
},
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+
{
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+
"BriefDescription": "Average cycles per completed instruction when dispatch was stalled while the instruction was fetched from the local L2",
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+
"MetricExpr": "PM_DISP_STALL_IC_L2 / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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"MetricName": "DISPATCHED_IC_L2_CPI"
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+
},
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+
{
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"BriefDescription": "Average cycles per completed instruction when dispatch was stalled while the instruction was fetched from the local L3",
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"MetricExpr": "PM_DISP_STALL_IC_L3 / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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"MetricName": "DISPATCHED_IC_L3_CPI"
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+
},
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+
{
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"BriefDescription": "Average cycles per completed instruction when dispatch was stalled while the instruction was fetched from any source beyond the local L3",
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+
"MetricExpr": "PM_DISP_STALL_IC_L3MISS / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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"MetricName": "DISPATCHED_IC_L3MISS_CPI"
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+
},
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+
{
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"BriefDescription": "Average cycles per completed instruction when dispatch was stalled due to an icache miss after a branch mispredict",
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+
"MetricExpr": "PM_DISP_STALL_BR_MPRED_ICMISS / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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+
"MetricName": "DISPATCHED_BR_MPRED_ICMISS_CPI"
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+
},
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+
{
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+
"BriefDescription": "Average cycles per completed instruction when dispatch was stalled while instruction was fetched from the local L2 after suffering a branch mispredict",
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+
"MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L2 / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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+
"MetricName": "DISPATCHED_BR_MPRED_IC_L2_CPI"
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+
},
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+
{
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"BriefDescription": "Average cycles per completed instruction when dispatch was stalled while instruction was fetched from the local L3 after suffering a branch mispredict",
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+
"MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L3 / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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+
"MetricName": "DISPATCHED_BR_MPRED_IC_L3_CPI"
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+
},
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{
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"BriefDescription": "Average cycles per completed instruction when dispatch was stalled while instruction was fetched from any source beyond the local L3 after suffering a branch mispredict",
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+
"MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L3MISS / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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+
"MetricName": "DISPATCHED_BR_MPRED_IC_L3MISS_CPI"
92
+
},
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{
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"BriefDescription": "Average cycles per completed instruction when dispatch was stalled due to a branch mispredict",
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"MetricExpr": "PM_DISP_STALL_BR_MPRED / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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+
"MetricName": "DISPATCHED_BR_MPRED_CPI"
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+
},
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch for any reason",
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"MetricExpr": "PM_DISP_STALL_HELD_CYC / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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"MetricName": "DISPATCHED_HELD_CPI"
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},
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch",
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"MetricExpr": "PM_DISP_STALL_HELD_SYNC_CYC / PM_RUN_INST_CMPL",
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"MetricGroup": "CPI",
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"MetricName": "DISP_HELD_STALL_SYNC_CPI"
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},
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch while waiting on the scoreboard",
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"MetricExpr": "PM_DISP_STALL_HELD_SCOREBOARD_CYC / PM_RUN_INST_CMPL",
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"MetricGroup": "CPI",
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+
"MetricName": "DISP_HELD_STALL_SCOREBOARD_CPI"
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+
},
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch due to issue queue full",
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"MetricExpr": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
121
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"MetricName": "DISP_HELD_STALL_ISSQ_FULL_CPI"
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+
},
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch because the mapper/SRB was full",
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"MetricExpr": "PM_DISP_STALL_HELD_RENAME_CYC / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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+
"MetricName": "DISPATCHED_HELD_RENAME_CPI"
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},
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch because the STF mapper/SRB was full",
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"MetricExpr": "PM_DISP_STALL_HELD_STF_MAPPER_CYC / PM_RUN_INST_CMPL",
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"MetricGroup": "CPI",
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"MetricName": "DISPATCHED_HELD_STF_MAPPER_CPI"
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},
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch because the XVFC mapper/SRB was full",
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"MetricExpr": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC / PM_RUN_INST_CMPL",
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"MetricGroup": "CPI",
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"MetricName": "DISPATCHED_HELD_XVFC_MAPPER_CPI"
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},
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch for any other reason",
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"MetricExpr": "PM_DISP_STALL_HELD_OTHER_CYC / PM_RUN_INST_CMPL",
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"MetricGroup": "CPI",
145
+
"MetricName": "DISPATCHED_HELD_OTHER_CPI"
146
+
},
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction has been dispatched but not issued for any reason",
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"MetricExpr": "PM_ISSUE_STALL / PM_RUN_INST_CMPL",
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"MetricGroup": "CPI",
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"MetricName": "ISSUE_STALL_CPI"
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},
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting to be finished in one of the execution units",
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+
"MetricExpr": "PM_EXEC_STALL / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
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"MetricName": "EXECUTION_STALL_CPI"
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+
},
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{
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"BriefDescription": "Average cycles per completed instruction spent executing an NTC instruction that gets flushed some time after dispatch",
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+
"MetricExpr": "PM_EXEC_STALL_NTC_FLUSH / PM_RUN_INST_CMPL",
162
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"MetricGroup": "CPI",
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+
"MetricName": "NTC_FLUSH_STALL_CPI"
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+
},
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{
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"BriefDescription": "Average cycles per completed instruction when the NTF instruction finishes at dispatch",
167
+
"MetricExpr": "PM_EXEC_STALL_FIN_AT_DISP / PM_RUN_INST_CMPL",
168
+
"MetricGroup": "CPI",
169
+
"MetricName": "FIN_AT_DISP_STALL_CPI"
170
+
},
171
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{
172
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction is executing in the branch unit",
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+
"MetricExpr": "PM_EXEC_STALL_BRU / PM_RUN_INST_CMPL",
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+
"MetricGroup": "CPI",
175
+
"MetricName": "BRU_STALL_CPI"
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+
},
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction is a simple fixed point instruction that is executing in the LSU",
179
+
"MetricExpr": "PM_EXEC_STALL_SIMPLE_FX / PM_RUN_INST_CMPL",
180
+
"MetricGroup": "CPI",
181
+
"MetricName": "SIMPLE_FX_STALL_CPI"
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+
},
183
+
{
184
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction is executing in the VSU",
185
+
"MetricExpr": "PM_EXEC_STALL_VSU / PM_RUN_INST_CMPL",
186
+
"MetricGroup": "CPI",
187
+
"MetricName": "VSU_STALL_CPI"
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+
},
189
+
{
190
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting to be finished in one of the execution units",
191
+
"MetricExpr": "PM_EXEC_STALL_TRANSLATION / PM_RUN_INST_CMPL",
192
+
"MetricGroup": "CPI",
193
+
"MetricName": "TRANSLATION_STALL_CPI"
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+
},
195
+
{
196
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is a load or store that suffered a translation miss",
197
+
"MetricExpr": "PM_EXEC_STALL_DERAT_ONLY_MISS / PM_RUN_INST_CMPL",
198
+
"MetricGroup": "CPI",
199
+
"MetricName": "DERAT_ONLY_MISS_STALL_CPI"
200
+
},
201
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction is recovering from a TLB miss",
203
+
"MetricExpr": "PM_EXEC_STALL_DERAT_DTLB_MISS / PM_RUN_INST_CMPL",
204
+
"MetricGroup": "CPI",
205
+
"MetricName": "DERAT_DTLB_MISS_STALL_CPI"
206
+
},
207
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{
208
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction is executing in the LSU",
209
+
"MetricExpr": "PM_EXEC_STALL_LSU / PM_RUN_INST_CMPL",
210
+
"MetricGroup": "CPI",
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"MetricName": "LSU_STALL_CPI"
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+
},
213
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{
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction is a load that is executing in the LSU",
215
+
"MetricExpr": "PM_EXEC_STALL_LOAD / PM_RUN_INST_CMPL",
216
+
"MetricGroup": "CPI",
217
+
"MetricName": "LOAD_STALL_CPI"
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+
},
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{
220
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"BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from either the local L2 or local L3",
221
+
"MetricExpr": "PM_EXEC_STALL_DMISS_L2L3 / PM_RUN_INST_CMPL",
222
+
"MetricGroup": "CPI",
223
+
"MetricName": "DMISS_L2L3_STALL_CPI"
224
+
},
225
+
{
226
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from either the local L2 or local L3, with an RC dispatch conflict",
227
+
"MetricExpr": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT / PM_RUN_INST_CMPL",
228
+
"MetricGroup": "CPI",
229
+
"MetricName": "DMISS_L2L3_CONFLICT_STALL_CPI"
230
+
},
231
+
{
232
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from either the local L2 or local L3, without an RC dispatch conflict",
233
+
"MetricExpr": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT / PM_RUN_INST_CMPL",
234
+
"MetricGroup": "CPI",
235
+
"MetricName": "DMISS_L2L3_NOCONFLICT_STALL_CPI"
236
+
},
237
+
{
238
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from a source beyond the local L2 and local L3",
239
+
"MetricExpr": "PM_EXEC_STALL_DMISS_L3MISS / PM_RUN_INST_CMPL",
240
+
"MetricGroup": "CPI",
241
+
"MetricName": "DMISS_L3MISS_STALL_CPI"
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+
},
243
+
{
244
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from a neighbor chiplet's L2 or L3 in the same chip",
245
+
"MetricExpr": "PM_EXEC_STALL_DMISS_L21_L31 / PM_RUN_INST_CMPL",
246
+
"MetricGroup": "CPI",
247
+
"MetricName": "DMISS_L21_L31_STALL_CPI"
248
+
},
249
+
{
250
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from L4, local memory or OpenCAPI chip",
251
+
"MetricExpr": "PM_EXEC_STALL_DMISS_LMEM / PM_RUN_INST_CMPL",
252
+
"MetricGroup": "CPI",
253
+
"MetricName": "DMISS_LMEM_STALL_CPI"
254
+
},
255
+
{
256
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from a remote chip (cache, L4, memory or OpenCAPI) in the same group",
257
+
"MetricExpr": "PM_EXEC_STALL_DMISS_OFF_CHIP / PM_RUN_INST_CMPL",
258
+
"MetricGroup": "CPI",
259
+
"MetricName": "DMISS_OFF_CHIP_STALL_CPI"
260
+
},
261
+
{
262
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from a distant chip (cache, L4, memory or OpenCAPI chip)",
263
+
"MetricExpr": "PM_EXEC_STALL_DMISS_OFF_NODE / PM_RUN_INST_CMPL",
264
+
"MetricGroup": "CPI",
265
+
"MetricName": "DMISS_OFF_NODE_STALL_CPI"
266
+
},
267
+
{
268
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is executing a TLBIEL instruction",
269
+
"MetricExpr": "PM_EXEC_STALL_TLBIEL / PM_RUN_INST_CMPL",
270
+
"MetricGroup": "CPI",
271
+
"MetricName": "TLBIEL_STALL_CPI"
272
+
},
273
+
{
274
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is finishing a load after its data has been reloaded from a data source beyond the local L1, OR when the LSU is processing an L1-hit, OR when the NTF instruction merged with another load in the LMQ",
275
+
"MetricExpr": "PM_EXEC_STALL_LOAD_FINISH / PM_RUN_INST_CMPL",
276
+
"MetricGroup": "CPI",
277
+
"MetricName": "LOAD_FINISH_STALL_CPI"
278
+
},
279
+
{
280
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is a store that is executing in the LSU",
281
+
"MetricExpr": "PM_EXEC_STALL_STORE / PM_RUN_INST_CMPL",
282
+
"MetricGroup": "CPI",
283
+
"MetricName": "STORE_STALL_CPI"
284
+
},
285
+
{
286
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is in the store unit outside of handling store misses or other special store operations",
287
+
"MetricExpr": "PM_EXEC_STALL_STORE_PIPE / PM_RUN_INST_CMPL",
288
+
"MetricGroup": "CPI",
289
+
"MetricName": "STORE_PIPE_STALL_CPI"
290
+
},
291
+
{
292
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is a store whose cache line was not resident in the L1 and had to wait for allocation of the missing line into the L1",
293
+
"MetricExpr": "PM_EXEC_STALL_STORE_MISS / PM_RUN_INST_CMPL",
294
+
"MetricGroup": "CPI",
295
+
"MetricName": "STORE_MISS_STALL_CPI"
296
+
},
297
+
{
298
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is a TLBIE instruction waiting for a response from the L2",
299
+
"MetricExpr": "PM_EXEC_STALL_TLBIE / PM_RUN_INST_CMPL",
300
+
"MetricGroup": "CPI",
301
+
"MetricName": "TLBIE_STALL_CPI"
302
+
},
303
+
{
304
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is executing a PTESYNC instruction",
305
+
"MetricExpr": "PM_EXEC_STALL_PTESYNC / PM_RUN_INST_CMPL",
306
+
"MetricGroup": "CPI",
307
+
"MetricName": "PTESYNC_STALL_CPI"
308
+
},
309
+
{
310
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction cannot complete because the thread was blocked",
311
+
"MetricExpr": "PM_CMPL_STALL / PM_RUN_INST_CMPL",
312
+
"MetricGroup": "CPI",
313
+
"MetricName": "COMPLETION_STALL_CPI"
314
+
},
315
+
{
316
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction cannot complete because it was interrupted by ANY exception",
317
+
"MetricExpr": "PM_CMPL_STALL_EXCEPTION / PM_RUN_INST_CMPL",
318
+
"MetricGroup": "CPI",
319
+
"MetricName": "EXCEPTION_COMPLETION_STALL_CPI"
320
+
},
321
+
{
322
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is stuck at finish waiting for the non-speculative finish of either a STCX instruction waiting for its result or a load waiting for non-critical sectors of data and ECC",
323
+
"MetricExpr": "PM_CMPL_STALL_MEM_ECC / PM_RUN_INST_CMPL",
324
+
"MetricGroup": "CPI",
325
+
"MetricName": "MEM_ECC_COMPLETION_STALL_CPI"
326
+
},
327
+
{
328
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is a STCX instruction waiting for resolution from the nest",
329
+
"MetricExpr": "PM_CMPL_STALL_STCX / PM_RUN_INST_CMPL",
330
+
"MetricGroup": "CPI",
331
+
"MetricName": "STCX_COMPLETION_STALL_CPI"
332
+
},
333
+
{
334
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is a LWSYNC instruction waiting to complete",
335
+
"MetricExpr": "PM_CMPL_STALL_LWSYNC / PM_RUN_INST_CMPL",
336
+
"MetricGroup": "CPI",
337
+
"MetricName": "LWSYNC_COMPLETION_STALL_CPI"
338
+
},
339
+
{
340
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction is a HWSYNC instruction stuck at finish waiting for a response from the L2",
341
+
"MetricExpr": "PM_CMPL_STALL_HWSYNC / PM_RUN_INST_CMPL",
342
+
"MetricGroup": "CPI",
343
+
"MetricName": "HWSYNC_COMPLETION_STALL_CPI"
344
+
},
345
+
{
346
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction required special handling before completion",
347
+
"MetricExpr": "PM_CMPL_STALL_SPECIAL / PM_RUN_INST_CMPL",
348
+
"MetricGroup": "CPI",
349
+
"MetricName": "SPECIAL_COMPLETION_STALL_CPI"
350
+
},
351
+
{
352
+
"BriefDescription": "Average cycles per completed instruction when dispatch was stalled because fetch was being held, so there was nothing in the pipeline for this thread",
353
+
"MetricExpr": "PM_DISP_STALL_FETCH / PM_RUN_INST_CMPL",
354
+
"MetricGroup": "CPI",
355
+
"MetricName": "DISPATCHED_FETCH_CPI"
356
+
},
357
+
{
358
+
"BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch because of power management",
359
+
"MetricExpr": "PM_DISP_STALL_HELD_HALT_CYC / PM_RUN_INST_CMPL",
360
+
"MetricGroup": "CPI",
361
+
"MetricName": "DISPATCHED_HELD_HALT_CPI"
362
+
},
363
+
{
364
+
"BriefDescription": "Percentage of flushes per completed instruction",
365
+
"MetricExpr": "PM_FLUSH / PM_RUN_INST_CMPL * 100",
366
+
"MetricGroup": "Others",
367
+
"MetricName": "FLUSH_RATE",
368
+
"ScaleUnit": "1%"
369
+
},
370
+
{
371
+
"BriefDescription": "Percentage of flushes due to a branch mispredict per completed instruction",
372
+
"MetricExpr": "PM_FLUSH_MPRED / PM_RUN_INST_CMPL * 100",
373
+
"MetricGroup": "Others",
374
+
"MetricName": "BR_MPRED_FLUSH_RATE",
375
+
"ScaleUnit": "1%"
376
+
},
377
+
{
378
+
"BriefDescription": "Percentage of branch mispredictions per completed instruction",
379
+
"MetricExpr": "PM_BR_MPRED_CMPL / PM_RUN_INST_CMPL",
380
+
"MetricGroup": "Others",
381
+
"MetricName": "BRANCH_MISPREDICTION_RATE"
382
+
},
383
+
{
384
+
"BriefDescription": "Percentage of finished loads that missed in the L1",
385
+
"MetricExpr": "PM_LD_MISS_L1 / PM_LD_REF_L1 * 100",
386
+
"MetricGroup": "Others",
387
+
"MetricName": "L1_LD_MISS_RATIO",
388
+
"ScaleUnit": "1%"
389
+
},
390
+
{
391
+
"BriefDescription": "Percentage of completed instructions that were loads that missed the L1",
392
+
"MetricExpr": "PM_LD_MISS_L1 / PM_RUN_INST_CMPL * 100",
393
+
"MetricGroup": "Others",
394
+
"MetricName": "L1_LD_MISS_RATE",
395
+
"ScaleUnit": "1%"
396
+
},
397
+
{
398
+
"BriefDescription": "Percentage of completed instructions when the DPTEG required for the load/store instruction in execution was missing from the TLB",
399
+
"MetricExpr": "PM_DTLB_MISS / PM_RUN_INST_CMPL * 100",
400
+
"MetricGroup": "Others",
401
+
"MetricName": "DTLB_MISS_RATE",
402
+
"ScaleUnit": "1%"
403
+
},
404
+
{
405
+
"BriefDescription": "Average number of completed instructions dispatched per instruction completed",
406
+
"MetricExpr": "PM_INST_DISP / PM_RUN_INST_CMPL",
407
+
"MetricGroup": "General",
408
+
"MetricName": "DISPATCH_PER_INST_CMPL"
409
+
},
410
+
{
411
+
"BriefDescription": "Percentage of completed instructions that were a demand load that did not hit in the L1 or L2",
412
+
"MetricExpr": "PM_DATA_FROM_L2MISS / PM_RUN_INST_CMPL * 100",
413
+
"MetricGroup": "General",
414
+
"MetricName": "L2_LD_MISS_RATE",
415
+
"ScaleUnit": "1%"
416
+
},
417
+
{
418
+
"BriefDescription": "Percentage of completed instructions that were demand fetches that missed the L1 icache",
419
+
"MetricExpr": "PM_L1_ICACHE_MISS / PM_RUN_INST_CMPL * 100",
420
+
"MetricGroup": "Instruction_Misses",
421
+
"MetricName": "L1_INST_MISS_RATE",
422
+
"ScaleUnit": "1%"
423
+
},
424
+
{
425
+
"BriefDescription": "Percentage of completed instructions that were demand fetches that reloaded from beyond the L3 icache",
426
+
"MetricExpr": "PM_INST_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
427
+
"MetricGroup": "General",
428
+
"MetricName": "L3_INST_MISS_RATE",
429
+
"ScaleUnit": "1%"
430
+
},
431
+
{
432
+
"BriefDescription": "Average number of completed instructions per cycle",
433
+
"MetricExpr": "PM_INST_CMPL / PM_CYC",
434
+
"MetricGroup": "General",
435
+
"MetricName": "IPC"
436
+
},
437
+
{
438
+
"BriefDescription": "Average number of cycles per completed instruction group",
439
+
"MetricExpr": "PM_CYC / PM_1PLUS_PPC_CMPL",
440
+
"MetricGroup": "General",
441
+
"MetricName": "CYCLES_PER_COMPLETED_INSTRUCTIONS_SET"
442
+
},
443
+
{
444
+
"BriefDescription": "Percentage of cycles when at least 1 instruction dispatched",
445
+
"MetricExpr": "PM_1PLUS_PPC_DISP / PM_RUN_CYC * 100",
446
+
"MetricGroup": "General",
447
+
"MetricName": "CYCLES_ATLEAST_ONE_INST_DISPATCHED",
448
+
"ScaleUnit": "1%"
449
+
},
450
+
{
451
+
"BriefDescription": "Average number of finished loads per completed instruction",
452
+
"MetricExpr": "PM_LD_REF_L1 / PM_RUN_INST_CMPL",
453
+
"MetricGroup": "General",
454
+
"MetricName": "LOADS_PER_INST"
455
+
},
456
+
{
457
+
"BriefDescription": "Average number of finished stores per completed instruction",
458
+
"MetricExpr": "PM_ST_FIN / PM_RUN_INST_CMPL",
459
+
"MetricGroup": "General",
460
+
"MetricName": "STORES_PER_INST"
461
+
},
462
+
{
463
+
"BriefDescription": "Percentage of demand loads that reloaded from beyond the L2 per completed instruction",
464
+
"MetricExpr": "PM_DATA_FROM_L2MISS / PM_RUN_INST_CMPL * 100",
465
+
"MetricGroup": "dL1_Reloads",
466
+
"MetricName": "DL1_RELOAD_FROM_L2_MISS_RATE",
467
+
"ScaleUnit": "1%"
468
+
},
469
+
{
470
+
"BriefDescription": "Percentage of demand loads that reloaded from beyond the L3 per completed instruction",
471
+
"MetricExpr": "PM_DATA_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
472
+
"MetricGroup": "dL1_Reloads",
473
+
"MetricName": "DL1_RELOAD_FROM_L3_MISS_RATE",
474
+
"ScaleUnit": "1%"
475
+
},
476
+
{
477
+
"BriefDescription": "Percentage of DERAT misses with 4k page size per completed instruction",
478
+
"MetricExpr": "PM_DERAT_MISS_4K / PM_RUN_INST_CMPL * 100",
479
+
"MetricGroup": "Translation",
480
+
"MetricName": "DERAT_4K_MISS_RATE",
481
+
"ScaleUnit": "1%"
482
+
},
483
+
{
484
+
"BriefDescription": "Percentage of DERAT misses with 64k page size per completed instruction",
485
+
"MetricExpr": "PM_DERAT_MISS_64K / PM_RUN_INST_CMPL * 100",
486
+
"MetricGroup": "Translation",
487
+
"MetricName": "DERAT_64K_MISS_RATE",
488
+
"ScaleUnit": "1%"
489
+
},
490
+
{
491
+
"BriefDescription": "Average number of run cycles per completed instruction",
492
+
"MetricExpr": "PM_RUN_CYC / PM_RUN_INST_CMPL",
493
+
"MetricGroup": "General",
494
+
"MetricName": "RUN_CPI"
495
+
},
496
+
{
497
+
"BriefDescription": "Percentage of DERAT misses per completed instruction",
498
+
"MetricExpr": "PM_DERAT_MISS / PM_RUN_INST_CMPL * 100",
499
+
"MetricGroup": "Translation",
500
+
"MetricName": "DERAT_MISS_RATE",
501
+
"ScaleUnit": "1%"
502
+
},
503
+
{
504
+
"BriefDescription": "Average number of completed instructions per run cycle",
505
+
"MetricExpr": "PM_RUN_INST_CMPL / PM_RUN_CYC",
506
+
"MetricGroup": "General",
507
+
"MetricName": "RUN_IPC"
508
+
},
509
+
{
510
+
"BriefDescription": "Average number of completed instructions per instruction group",
511
+
"MetricExpr": "PM_RUN_INST_CMPL / PM_1PLUS_PPC_CMPL",
512
+
"MetricGroup": "General",
513
+
"MetricName": "AVERAGE_COMPLETED_INSTRUCTION_SET_SIZE"
514
+
},
515
+
{
516
+
"BriefDescription": "Average number of finished instructions per completed instructions",
517
+
"MetricExpr": "PM_INST_FIN / PM_RUN_INST_CMPL",
518
+
"MetricGroup": "General",
519
+
"MetricName": "INST_FIN_PER_CMPL"
520
+
},
521
+
{
522
+
"BriefDescription": "Average cycles per completed instruction when the NTF instruction is completing and the finish was overlooked",
523
+
"MetricExpr": "PM_EXEC_STALL_UNKNOWN / PM_RUN_INST_CMPL",
524
+
"MetricGroup": "General",
525
+
"MetricName": "EXEC_STALL_UNKOWN_CPI"
526
+
},
527
+
{
528
+
"BriefDescription": "Percentage of finished branches that were taken",
529
+
"MetricExpr": "PM_BR_TAKEN_CMPL / PM_BR_FIN * 100",
530
+
"MetricGroup": "General",
531
+
"MetricName": "TAKEN_BRANCHES",
532
+
"ScaleUnit": "1%"
533
+
},
534
+
{
535
+
"BriefDescription": "Percentage of completed instructions that were a demand load that did not hit in the L1, L2, or the L3",
536
+
"MetricExpr": "PM_DATA_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
537
+
"MetricGroup": "General",
538
+
"MetricName": "L3_LD_MISS_RATE",
539
+
"ScaleUnit": "1%"
540
+
},
541
+
{
542
+
"BriefDescription": "Average number of finished branches per completed instruction",
543
+
"MetricExpr": "PM_BR_FIN / PM_RUN_INST_CMPL",
544
+
"MetricGroup": "General",
545
+
"MetricName": "BRANCHES_PER_INST"
546
+
},
547
+
{
548
+
"BriefDescription": "Average number of instructions finished in the LSU per completed instruction",
549
+
"MetricExpr": "PM_LSU_FIN / PM_RUN_INST_CMPL",
550
+
"MetricGroup": "General",
551
+
"MetricName": "LSU_PER_INST"
552
+
},
553
+
{
554
+
"BriefDescription": "Average number of instructions finished in the VSU per completed instruction",
555
+
"MetricExpr": "PM_VSU_FIN / PM_RUN_INST_CMPL",
556
+
"MetricGroup": "General",
557
+
"MetricName": "VSU_PER_INST"
558
+
},
559
+
{
560
+
"BriefDescription": "Average number of TLBIE instructions finished in the LSU per completed instruction",
561
+
"MetricExpr": "PM_TLBIE_FIN / PM_RUN_INST_CMPL",
562
+
"MetricGroup": "General",
563
+
"MetricName": "TLBIE_PER_INST"
564
+
},
565
+
{
566
+
"BriefDescription": "Average number of STCX instructions finshed per completed instruction",
567
+
"MetricExpr": "PM_STCX_FIN / PM_RUN_INST_CMPL",
568
+
"MetricGroup": "General",
569
+
"MetricName": "STXC_PER_INST"
570
+
},
571
+
{
572
+
"BriefDescription": "Average number of LARX instructions finshed per completed instruction",
573
+
"MetricExpr": "PM_LARX_FIN / PM_RUN_INST_CMPL",
574
+
"MetricGroup": "General",
575
+
"MetricName": "LARX_PER_INST"
576
+
},
577
+
{
578
+
"BriefDescription": "Average number of PTESYNC instructions finshed per completed instruction",
579
+
"MetricExpr": "PM_PTESYNC_FIN / PM_RUN_INST_CMPL",
580
+
"MetricGroup": "General",
581
+
"MetricName": "PTESYNC_PER_INST"
582
+
},
583
+
{
584
+
"BriefDescription": "Average number of simple fixed-point instructions finshed in the store unit per completed instruction",
585
+
"MetricExpr": "PM_FX_LSU_FIN / PM_RUN_INST_CMPL",
586
+
"MetricGroup": "General",
587
+
"MetricName": "FX_PER_INST"
588
+
},
589
+
{
590
+
"BriefDescription": "Percentage of demand load misses that reloaded the L1 cache",
591
+
"MetricExpr": "PM_LD_DEMAND_MISS_L1 / PM_LD_MISS_L1 * 100",
592
+
"MetricGroup": "General",
593
+
"MetricName": "DL1_MISS_RELOADS",
594
+
"ScaleUnit": "1%"
595
+
},
596
+
{
597
+
"BriefDescription": "Percentage of demand load misses that reloaded from beyond the local L2",
598
+
"MetricExpr": "PM_DATA_FROM_L2MISS / PM_LD_DEMAND_MISS_L1 * 100",
599
+
"MetricGroup": "dL1_Reloads",
600
+
"MetricName": "DL1_RELOAD_FROM_L2_MISS",
601
+
"ScaleUnit": "1%"
602
+
},
603
+
{
604
+
"BriefDescription": "Percentage of demand load misses that reloaded from beyond the local L3",
605
+
"MetricExpr": "PM_DATA_FROM_L3MISS / PM_LD_DEMAND_MISS_L1 * 100",
606
+
"MetricGroup": "dL1_Reloads",
607
+
"MetricName": "DL1_RELOAD_FROM_L3_MISS",
608
+
"ScaleUnit": "1%"
609
+
},
610
+
{
611
+
"BriefDescription": "Percentage of cycles stalled due to the NTC instruction waiting for a load miss to resolve from a source beyond the local L2 and local L3",
612
+
"MetricExpr": "DMISS_L3MISS_STALL_CPI / RUN_CPI * 100",
613
+
"MetricGroup": "General",
614
+
"MetricName": "DCACHE_MISS_CPI",
615
+
"ScaleUnit": "1%"
616
+
},
617
+
{
618
+
"BriefDescription": "Percentage of DERAT misses with 2M page size per completed instruction",
619
+
"MetricExpr": "PM_DERAT_MISS_2M / PM_RUN_INST_CMPL * 100",
620
+
"MetricGroup": "Translation",
621
+
"MetricName": "DERAT_2M_MISS_RATE",
622
+
"ScaleUnit": "1%"
623
+
},
624
+
{
625
+
"BriefDescription": "Percentage of DERAT misses with 16M page size per completed instruction",
626
+
"MetricExpr": "PM_DERAT_MISS_16M / PM_RUN_INST_CMPL * 100",
627
+
"MetricGroup": "Translation",
628
+
"MetricName": "DERAT_16M_MISS_RATE",
629
+
"ScaleUnit": "1%"
630
+
},
631
+
{
632
+
"BriefDescription": "DERAT miss ratio for 4K page size",
633
+
"MetricExpr": "PM_DERAT_MISS_4K / PM_DERAT_MISS",
634
+
"MetricGroup": "Translation",
635
+
"MetricName": "DERAT_4K_MISS_RATIO"
636
+
},
637
+
{
638
+
"BriefDescription": "DERAT miss ratio for 2M page size",
639
+
"MetricExpr": "PM_DERAT_MISS_2M / PM_DERAT_MISS",
640
+
"MetricGroup": "Translation",
641
+
"MetricName": "DERAT_2M_MISS_RATIO"
642
+
},
643
+
{
644
+
"BriefDescription": "DERAT miss ratio for 16M page size",
645
+
"MetricExpr": "PM_DERAT_MISS_16M / PM_DERAT_MISS",
646
+
"MetricGroup": "Translation",
647
+
"MetricName": "DERAT_16M_MISS_RATIO"
648
+
},
649
+
{
650
+
"BriefDescription": "DERAT miss ratio for 64K page size",
651
+
"MetricExpr": "PM_DERAT_MISS_64K / PM_DERAT_MISS",
652
+
"MetricGroup": "Translation",
653
+
"MetricName": "DERAT_64K_MISS_RATIO"
654
+
},
655
+
{
656
+
"BriefDescription": "Percentage of DERAT misses that resulted in TLB reloads",
657
+
"MetricExpr": "PM_DTLB_MISS / PM_DERAT_MISS * 100",
658
+
"MetricGroup": "Translation",
659
+
"MetricName": "DERAT_MISS_RELOAD",
660
+
"ScaleUnit": "1%"
661
+
},
662
+
{
663
+
"BriefDescription": "Percentage of icache misses that were reloaded from beyond the local L3",
664
+
"MetricExpr": "PM_INST_FROM_L3MISS / PM_L1_ICACHE_MISS * 100",
665
+
"MetricGroup": "Instruction_Misses",
666
+
"MetricName": "INST_FROM_L3_MISS",
667
+
"ScaleUnit": "1%"
668
+
},
669
+
{
670
+
"BriefDescription": "Percentage of icache reloads from the beyond the L3 per completed instruction",
671
+
"MetricExpr": "PM_INST_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
672
+
"MetricGroup": "Instruction_Misses",
673
+
"MetricName": "INST_FROM_L3_MISS_RATE",
674
+
"ScaleUnit": "1%"
675
+
}
676
+
]